EE445M RTOS
Taken at the University of Texas Spring 2015
Main Page
Related Pages
Modules
Data Structures
Files
File List
Globals
hw_emac.h
Go to the documentation of this file.
1
//*****************************************************************************
2
//
3
// hw_emac.h - Macros used when accessing the EMAC hardware.
4
//
5
// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved.
6
// Software License Agreement
7
//
8
// Redistribution and use in source and binary forms, with or without
9
// modification, are permitted provided that the following conditions
10
// are met:
11
//
12
// Redistributions of source code must retain the above copyright
13
// notice, this list of conditions and the following disclaimer.
14
//
15
// Redistributions in binary form must reproduce the above copyright
16
// notice, this list of conditions and the following disclaimer in the
17
// documentation and/or other materials provided with the
18
// distribution.
19
//
20
// Neither the name of Texas Instruments Incorporated nor the names of
21
// its contributors may be used to endorse or promote products derived
22
// from this software without specific prior written permission.
23
//
24
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
//
36
// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
37
//
38
//*****************************************************************************
39
40
#ifndef __HW_EMAC_H__
41
#define __HW_EMAC_H__
42
43
//*****************************************************************************
44
//
45
// The following are defines for the EMAC register offsets.
46
//
47
//*****************************************************************************
48
#define EMAC_O_CFG 0x00000000 // Ethernet MAC Configuration
49
#define EMAC_O_FRAMEFLTR 0x00000004 // Ethernet MAC Frame Filter
50
#define EMAC_O_HASHTBLH 0x00000008 // Ethernet MAC Hash Table High
51
#define EMAC_O_HASHTBLL 0x0000000C // Ethernet MAC Hash Table Low
52
#define EMAC_O_MIIADDR 0x00000010 // Ethernet MAC MII Address
53
#define EMAC_O_MIIDATA 0x00000014 // Ethernet MAC MII Data Register
54
#define EMAC_O_FLOWCTL 0x00000018 // Ethernet MAC Flow Control
55
#define EMAC_O_VLANTG 0x0000001C // Ethernet MAC VLAN Tag
56
#define EMAC_O_STATUS 0x00000024 // Ethernet MAC Status
57
#define EMAC_O_RWUFF 0x00000028 // Ethernet MAC Remote Wake-Up
58
// Frame Filter
59
#define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and
60
// Status Register
61
#define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt
62
// Status
63
#define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask
64
#define EMAC_O_ADDR0H 0x00000040 // Ethernet MAC Address 0 High
65
#define EMAC_O_ADDR0L 0x00000044 // Ethernet MAC Address 0 Low
66
// Register
67
#define EMAC_O_ADDR1H 0x00000048 // Ethernet MAC Address 1 High
68
#define EMAC_O_ADDR1L 0x0000004C // Ethernet MAC Address 1 Low
69
#define EMAC_O_ADDR2H 0x00000050 // Ethernet MAC Address 2 High
70
#define EMAC_O_ADDR2L 0x00000054 // Ethernet MAC Address 2 Low
71
#define EMAC_O_ADDR3H 0x00000058 // Ethernet MAC Address 3 High
72
#define EMAC_O_ADDR3L 0x0000005C // Ethernet MAC Address 3 Low
73
#define EMAC_O_WDOGTO 0x000000DC // Ethernet MAC Watchdog Timeout
74
#define EMAC_O_MMCCTRL 0x00000100 // Ethernet MAC MMC Control
75
#define EMAC_O_MMCRXRIS 0x00000104 // Ethernet MAC MMC Receive Raw
76
// Interrupt Status
77
#define EMAC_O_MMCTXRIS 0x00000108 // Ethernet MAC MMC Transmit Raw
78
// Interrupt Status
79
#define EMAC_O_MMCRXIM 0x0000010C // Ethernet MAC MMC Receive
80
// Interrupt Mask
81
#define EMAC_O_MMCTXIM 0x00000110 // Ethernet MAC MMC Transmit
82
// Interrupt Mask
83
#define EMAC_O_TXCNTGB 0x00000118 // Ethernet MAC Transmit Frame
84
// Count for Good and Bad Frames
85
#define EMAC_O_TXCNTSCOL 0x0000014C // Ethernet MAC Transmit Frame
86
// Count for Frames Transmitted
87
// after Single Collision
88
#define EMAC_O_TXCNTMCOL 0x00000150 // Ethernet MAC Transmit Frame
89
// Count for Frames Transmitted
90
// after Multiple Collisions
91
#define EMAC_O_TXOCTCNTG 0x00000164 // Ethernet MAC Transmit Octet
92
// Count Good
93
#define EMAC_O_RXCNTGB 0x00000180 // Ethernet MAC Receive Frame Count
94
// for Good and Bad Frames
95
#define EMAC_O_RXCNTCRCERR 0x00000194 // Ethernet MAC Receive Frame Count
96
// for CRC Error Frames
97
#define EMAC_O_RXCNTALGNERR 0x00000198 // Ethernet MAC Receive Frame Count
98
// for Alignment Error Frames
99
#define EMAC_O_RXCNTGUNI 0x000001C4 // Ethernet MAC Receive Frame Count
100
// for Good Unicast Frames
101
#define EMAC_O_VLNINCREP 0x00000584 // Ethernet MAC VLAN Tag Inclusion
102
// or Replacement
103
#define EMAC_O_VLANHASH 0x00000588 // Ethernet MAC VLAN Hash Table
104
#define EMAC_O_TIMSTCTRL 0x00000700 // Ethernet MAC Timestamp Control
105
#define EMAC_O_SUBSECINC 0x00000704 // Ethernet MAC Sub-Second
106
// Increment
107
#define EMAC_O_TIMSEC 0x00000708 // Ethernet MAC System Time -
108
// Seconds
109
#define EMAC_O_TIMNANO 0x0000070C // Ethernet MAC System Time -
110
// Nanoseconds
111
#define EMAC_O_TIMSECU 0x00000710 // Ethernet MAC System Time -
112
// Seconds Update
113
#define EMAC_O_TIMNANOU 0x00000714 // Ethernet MAC System Time -
114
// Nanoseconds Update
115
#define EMAC_O_TIMADD 0x00000718 // Ethernet MAC Timestamp Addend
116
#define EMAC_O_TARGSEC 0x0000071C // Ethernet MAC Target Time Seconds
117
#define EMAC_O_TARGNANO 0x00000720 // Ethernet MAC Target Time
118
// Nanoseconds
119
#define EMAC_O_HWORDSEC 0x00000724 // Ethernet MAC System Time-Higher
120
// Word Seconds
121
#define EMAC_O_TIMSTAT 0x00000728 // Ethernet MAC Timestamp Status
122
#define EMAC_O_PPSCTRL 0x0000072C // Ethernet MAC PPS Control
123
#define EMAC_O_PPS0INTVL 0x00000760 // Ethernet MAC PPS0 Interval
124
#define EMAC_O_PPS0WIDTH 0x00000764 // Ethernet MAC PPS0 Width
125
#define EMAC_O_DMABUSMOD 0x00000C00 // Ethernet MAC DMA Bus Mode
126
#define EMAC_O_TXPOLLD 0x00000C04 // Ethernet MAC Transmit Poll
127
// Demand
128
#define EMAC_O_RXPOLLD 0x00000C08 // Ethernet MAC Receive Poll Demand
129
#define EMAC_O_RXDLADDR 0x00000C0C // Ethernet MAC Receive Descriptor
130
// List Address
131
#define EMAC_O_TXDLADDR 0x00000C10 // Ethernet MAC Transmit Descriptor
132
// List Address
133
#define EMAC_O_DMARIS 0x00000C14 // Ethernet MAC DMA Interrupt
134
// Status
135
#define EMAC_O_DMAOPMODE 0x00000C18 // Ethernet MAC DMA Operation Mode
136
#define EMAC_O_DMAIM 0x00000C1C // Ethernet MAC DMA Interrupt Mask
137
// Register
138
#define EMAC_O_MFBOC 0x00000C20 // Ethernet MAC Missed Frame and
139
// Buffer Overflow Counter
140
#define EMAC_O_RXINTWDT 0x00000C24 // Ethernet MAC Receive Interrupt
141
// Watchdog Timer
142
#define EMAC_O_HOSTXDESC 0x00000C48 // Ethernet MAC Current Host
143
// Transmit Descriptor
144
#define EMAC_O_HOSRXDESC 0x00000C4C // Ethernet MAC Current Host
145
// Receive Descriptor
146
#define EMAC_O_HOSTXBA 0x00000C50 // Ethernet MAC Current Host
147
// Transmit Buffer Address
148
#define EMAC_O_HOSRXBA 0x00000C54 // Ethernet MAC Current Host
149
// Receive Buffer Address
150
#define EMAC_O_PP 0x00000FC0 // Ethernet MAC Peripheral Property
151
// Register
152
#define EMAC_O_PC 0x00000FC4 // Ethernet MAC Peripheral
153
// Configuration Register
154
#define EMAC_O_CC 0x00000FC8 // Ethernet MAC Clock Configuration
155
// Register
156
#define EMAC_O_EPHYRIS 0x00000FD0 // Ethernet PHY Raw Interrupt
157
// Status
158
#define EMAC_O_EPHYIM 0x00000FD4 // Ethernet PHY Interrupt Mask
159
#define EMAC_O_EPHYMISC 0x00000FD8 // Ethernet PHY Masked Interrupt
160
// Status and Clear
161
162
//*****************************************************************************
163
//
164
// The following are defines for the bit fields in the EMAC_O_CFG register.
165
//
166
//*****************************************************************************
167
#define EMAC_CFG_TWOKPEN 0x08000000 // IEEE 802
168
#define EMAC_CFG_CST 0x02000000 // CRC Stripping for Type Frames
169
#define EMAC_CFG_WDDIS 0x00800000 // Watchdog Disable
170
#define EMAC_CFG_JD 0x00400000 // Jabber Disable
171
#define EMAC_CFG_JFEN 0x00100000 // Jumbo Frame Enable
172
#define EMAC_CFG_IFG_M 0x000E0000 // Inter-Frame Gap (IFG)
173
#define EMAC_CFG_IFG_96 0x00000000 // 96 bit times
174
#define EMAC_CFG_IFG_88 0x00020000 // 88 bit times
175
#define EMAC_CFG_IFG_80 0x00040000 // 80 bit times
176
#define EMAC_CFG_IFG_72 0x00060000 // 72 bit times
177
#define EMAC_CFG_IFG_64 0x00080000 // 64 bit times
178
#define EMAC_CFG_IFG_56 0x000A0000 // 56 bit times
179
#define EMAC_CFG_IFG_48 0x000C0000 // 48 bit times
180
#define EMAC_CFG_IFG_40 0x000E0000 // 40 bit times
181
#define EMAC_CFG_DISCRS 0x00010000 // Disable Carrier Sense During
182
// Transmission
183
#define EMAC_CFG_PS 0x00008000 // Port Select
184
#define EMAC_CFG_FES 0x00004000 // Speed
185
#define EMAC_CFG_DRO 0x00002000 // Disable Receive Own
186
#define EMAC_CFG_LOOPBM 0x00001000 // Loopback Mode
187
#define EMAC_CFG_DUPM 0x00000800 // Duplex Mode
188
#define EMAC_CFG_IPC 0x00000400 // Checksum Offload
189
#define EMAC_CFG_DR 0x00000200 // Disable Retry
190
#define EMAC_CFG_ACS 0x00000080 // Automatic Pad or CRC Stripping
191
#define EMAC_CFG_BL_M 0x00000060 // Back-Off Limit
192
#define EMAC_CFG_BL_1024 0x00000000 // k = min (n,10)
193
#define EMAC_CFG_BL_256 0x00000020 // k = min (n,8)
194
#define EMAC_CFG_BL_8 0x00000040 // k = min (n,4)
195
#define EMAC_CFG_BL_2 0x00000060 // k = min (n,1)
196
#define EMAC_CFG_DC 0x00000010 // Deferral Check
197
#define EMAC_CFG_TE 0x00000008 // Transmitter Enable
198
#define EMAC_CFG_RE 0x00000004 // Receiver Enable
199
#define EMAC_CFG_PRELEN_M 0x00000003 // Preamble Length for Transmit
200
// Frames
201
#define EMAC_CFG_PRELEN_7 0x00000000 // 7 bytes of preamble
202
#define EMAC_CFG_PRELEN_5 0x00000001 // 5 bytes of preamble
203
#define EMAC_CFG_PRELEN_3 0x00000002 // 3 bytes of preamble
204
205
//*****************************************************************************
206
//
207
// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR
208
// register.
209
//
210
//*****************************************************************************
211
#define EMAC_FRAMEFLTR_RA 0x80000000 // Receive All
212
#define EMAC_FRAMEFLTR_VTFE 0x00010000 // VLAN Tag Filter Enable
213
#define EMAC_FRAMEFLTR_HPF 0x00000400 // Hash or Perfect Filter
214
#define EMAC_FRAMEFLTR_SAF 0x00000200 // Source Address Filter Enable
215
#define EMAC_FRAMEFLTR_SAIF 0x00000100 // Source Address (SA) Inverse
216
// Filtering
217
#define EMAC_FRAMEFLTR_PCF_M 0x000000C0 // Pass Control Frames
218
#define EMAC_FRAMEFLTR_PCF_ALL 0x00000000 // The MAC filters all control
219
// frames from reaching application
220
#define EMAC_FRAMEFLTR_PCF_PAUSE \
221
0x00000040 // MAC forwards all control frames
222
// except PAUSE control frames to
223
// application even if they fail
224
// the address filter
225
#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080 // MAC forwards all control frames
226
// to application even if they fail
227
// the address Filter
228
#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0 // MAC forwards control frames that
229
// pass the address Filter
230
#define EMAC_FRAMEFLTR_DBF 0x00000020 // Disable Broadcast Frames
231
#define EMAC_FRAMEFLTR_PM 0x00000010 // Pass All Multicast
232
#define EMAC_FRAMEFLTR_DAIF 0x00000008 // Destination Address (DA) Inverse
233
// Filtering
234
#define EMAC_FRAMEFLTR_HMC 0x00000004 // Hash Multicast
235
#define EMAC_FRAMEFLTR_HUC 0x00000002 // Hash Unicast
236
#define EMAC_FRAMEFLTR_PR 0x00000001 // Promiscuous Mode
237
238
//*****************************************************************************
239
//
240
// The following are defines for the bit fields in the EMAC_O_HASHTBLH
241
// register.
242
//
243
//*****************************************************************************
244
#define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF // Hash Table High
245
#define EMAC_HASHTBLH_HTH_S 0
246
247
//*****************************************************************************
248
//
249
// The following are defines for the bit fields in the EMAC_O_HASHTBLL
250
// register.
251
//
252
//*****************************************************************************
253
#define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF // Hash Table Low
254
#define EMAC_HASHTBLL_HTL_S 0
255
256
//*****************************************************************************
257
//
258
// The following are defines for the bit fields in the EMAC_O_MIIADDR register.
259
//
260
//*****************************************************************************
261
#define EMAC_MIIADDR_PLA_M 0x0000F800 // Physical Layer Address
262
#define EMAC_MIIADDR_MII_M 0x000007C0 // MII Register
263
#define EMAC_MIIADDR_CR_M 0x0000003C // Clock Reference Frequency
264
// Selection
265
#define EMAC_MIIADDR_CR_60_100 0x00000000 // The frequency of the System
266
// Clock is 60 to 100 MHz providing
267
// a MDIO clock of SYSCLK/42
268
#define EMAC_MIIADDR_CR_100_150 0x00000004 // The frequency of the System
269
// Clock is 100 to 150 MHz
270
// providing a MDIO clock of
271
// SYSCLK/62
272
#define EMAC_MIIADDR_CR_20_35 0x00000008 // The frequency of the System
273
// Clock is 20-35 MHz providing a
274
// MDIO clock of System Clock/16
275
#define EMAC_MIIADDR_CR_35_60 0x0000000C // The frequency of the System
276
// Clock is 35 to 60 MHz providing
277
// a MDIO clock of System Clock/26
278
#define EMAC_MIIADDR_MIIW 0x00000002 // MII Write
279
#define EMAC_MIIADDR_MIIB 0x00000001 // MII Busy
280
#define EMAC_MIIADDR_PLA_S 11
281
#define EMAC_MIIADDR_MII_S 6
282
283
//*****************************************************************************
284
//
285
// The following are defines for the bit fields in the EMAC_O_MIIDATA register.
286
//
287
//*****************************************************************************
288
#define EMAC_MIIDATA_DATA_M 0x0000FFFF // MII Data
289
#define EMAC_MIIDATA_DATA_S 0
290
291
//*****************************************************************************
292
//
293
// The following are defines for the bit fields in the EMAC_O_FLOWCTL register.
294
//
295
//*****************************************************************************
296
#define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time
297
#define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause
298
#define EMAC_FLOWCTL_PLT_M 0x00000030 // Pause Low Threshold
299
#define EMAC_FLOWCTL_PLT_4 0x00000000 // The threshold is Pause time
300
// minus 4 slot times (PT - 4 slot
301
// times)
302
#define EMAC_FLOWCTL_PLT_28 0x00000010 // The threshold is Pause time
303
// minus 28 slot times (PT - 28
304
// slot times)
305
#define EMAC_FLOWCTL_PLT_144 0x00000020 // The threshold is Pause time
306
// minus 144 slot times (PT - 144
307
// slot times)
308
#define EMAC_FLOWCTL_PLT_156 0x00000030 // The threshold is Pause time
309
// minus 256 slot times (PT - 256
310
// slot times)
311
#define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect
312
#define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable
313
#define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable
314
#define EMAC_FLOWCTL_FCBBPA 0x00000001 // Flow Control Busy or
315
// Back-pressure Activate
316
#define EMAC_FLOWCTL_PT_S 16
317
318
//*****************************************************************************
319
//
320
// The following are defines for the bit fields in the EMAC_O_VLANTG register.
321
//
322
//*****************************************************************************
323
#define EMAC_VLANTG_VTHM 0x00080000 // VLAN Tag Hash Table Match Enable
324
#define EMAC_VLANTG_ESVL 0x00040000 // Enable S-VLAN
325
#define EMAC_VLANTG_VTIM 0x00020000 // VLAN Tag Inverse Match Enable
326
#define EMAC_VLANTG_ETV 0x00010000 // Enable 12-Bit VLAN Tag
327
// Comparison
328
#define EMAC_VLANTG_VL_M 0x0000FFFF // VLAN Tag Identifier for Receive
329
// Frames
330
#define EMAC_VLANTG_VL_S 0
331
332
//*****************************************************************************
333
//
334
// The following are defines for the bit fields in the EMAC_O_STATUS register.
335
//
336
//*****************************************************************************
337
#define EMAC_STATUS_TXFF 0x02000000 // TX/RX Controller TX FIFO Full
338
// Status
339
#define EMAC_STATUS_TXFE 0x01000000 // TX/RX Controller TX FIFO Not
340
// Empty Status
341
#define EMAC_STATUS_TWC 0x00400000 // TX/RX Controller TX FIFO Write
342
// Controller Active Status
343
#define EMAC_STATUS_TRC_M 0x00300000 // TX/RX Controller's TX FIFO Read
344
// Controller Status
345
#define EMAC_STATUS_TRC_IDLE 0x00000000 // IDLE state
346
#define EMAC_STATUS_TRC_READ 0x00100000 // READ state (transferring data to
347
// MAC transmitter)
348
#define EMAC_STATUS_TRC_WAIT 0x00200000 // Waiting for TX Status from MAC
349
// transmitter
350
#define EMAC_STATUS_TRC_WRFLUSH 0x00300000 // Writing the received TX Status
351
// or flushing the TX FIFO
352
#define EMAC_STATUS_TXPAUSED 0x00080000 // MAC Transmitter PAUSE
353
#define EMAC_STATUS_TFC_M 0x00060000 // MAC Transmit Frame Controller
354
// Status
355
#define EMAC_STATUS_TFC_IDLE 0x00000000 // IDLE state
356
#define EMAC_STATUS_TFC_STATUS 0x00020000 // Waiting for status of previous
357
// frame or IFG or backoff period
358
// to be over
359
#define EMAC_STATUS_TFC_PAUSE 0x00040000 // Generating and transmitting a
360
// PAUSE control frame (in the
361
// full-duplex mode)
362
#define EMAC_STATUS_TFC_INPUT 0x00060000 // Transferring input frame for
363
// transmission
364
#define EMAC_STATUS_TPE 0x00010000 // MAC MII Transmit Protocol Engine
365
// Status
366
#define EMAC_STATUS_RXF_M 0x00000300 // TX/RX Controller RX FIFO
367
// Fill-level Status
368
#define EMAC_STATUS_RXF_EMPTY 0x00000000 // RX FIFO Empty
369
#define EMAC_STATUS_RXF_BELOW 0x00000100 // RX FIFO fill level is below the
370
// flow-control deactivate
371
// threshold
372
#define EMAC_STATUS_RXF_ABOVE 0x00000200 // RX FIFO fill level is above the
373
// flow-control activate threshold
374
#define EMAC_STATUS_RXF_FULL 0x00000300 // RX FIFO Full
375
#define EMAC_STATUS_RRC_M 0x00000060 // TX/RX Controller Read Controller
376
// State
377
#define EMAC_STATUS_RRC_IDLE 0x00000000 // IDLE state
378
#define EMAC_STATUS_RRC_STATUS 0x00000020 // Reading frame data
379
#define EMAC_STATUS_RRC_DATA 0x00000040 // Reading frame status (or
380
// timestamp)
381
#define EMAC_STATUS_RRC_FLUSH 0x00000060 // Flushing the frame data and
382
// status
383
#define EMAC_STATUS_RWC 0x00000010 // TX/RX Controller RX FIFO Write
384
// Controller Active Status
385
#define EMAC_STATUS_RFCFC_M 0x00000006 // MAC Receive Frame Controller
386
// FIFO Status
387
#define EMAC_STATUS_RPE 0x00000001 // MAC MII Receive Protocol Engine
388
// Status
389
#define EMAC_STATUS_RFCFC_S 1
390
391
//*****************************************************************************
392
//
393
// The following are defines for the bit fields in the EMAC_O_RWUFF register.
394
//
395
//*****************************************************************************
396
#define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF // Remote Wake-Up Frame Filter
397
#define EMAC_RWUFF_WAKEUPFIL_S 0
398
399
//*****************************************************************************
400
//
401
// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT
402
// register.
403
//
404
//*****************************************************************************
405
#define EMAC_PMTCTLSTAT_WUPFRRST \
406
0x80000000 // Wake-Up Frame Filter Register
407
// Pointer Reset
408
#define EMAC_PMTCTLSTAT_RWKPTR_M \
409
0x07000000 // Remote Wake-Up FIFO Pointer
410
#define EMAC_PMTCTLSTAT_GLBLUCAST \
411
0x00000200 // Global Unicast
412
#define EMAC_PMTCTLSTAT_WUPRX 0x00000040 // Wake-Up Frame Received
413
#define EMAC_PMTCTLSTAT_MGKPRX 0x00000020 // Magic Packet Received
414
#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004 // Wake-Up Frame Enable
415
#define EMAC_PMTCTLSTAT_MGKPKTEN \
416
0x00000002 // Magic Packet Enable
417
#define EMAC_PMTCTLSTAT_PWRDWN 0x00000001 // Power Down
418
#define EMAC_PMTCTLSTAT_RWKPTR_S \
419
24
420
421
//*****************************************************************************
422
//
423
// The following are defines for the bit fields in the EMAC_O_RIS register.
424
//
425
//*****************************************************************************
426
#define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status
427
#define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status
428
#define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status
429
#define EMAC_RIS_MMC 0x00000010 // MMC Interrupt Status
430
#define EMAC_RIS_PMT 0x00000008 // PMT Interrupt Status
431
432
//*****************************************************************************
433
//
434
// The following are defines for the bit fields in the EMAC_O_IM register.
435
//
436
//*****************************************************************************
437
#define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask
438
#define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask
439
440
//*****************************************************************************
441
//
442
// The following are defines for the bit fields in the EMAC_O_ADDR0H register.
443
//
444
//*****************************************************************************
445
#define EMAC_ADDR0H_AE 0x80000000 // Address Enable
446
#define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF // MAC Address0 [47:32]
447
#define EMAC_ADDR0H_ADDRHI_S 0
448
449
//*****************************************************************************
450
//
451
// The following are defines for the bit fields in the EMAC_O_ADDR0L register.
452
//
453
//*****************************************************************************
454
#define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF // MAC Address0 [31:0]
455
#define EMAC_ADDR0L_ADDRLO_S 0
456
457
//*****************************************************************************
458
//
459
// The following are defines for the bit fields in the EMAC_O_ADDR1H register.
460
//
461
//*****************************************************************************
462
#define EMAC_ADDR1H_AE 0x80000000 // Address Enable
463
#define EMAC_ADDR1H_SA 0x40000000 // Source Address
464
#define EMAC_ADDR1H_MBC_M 0x3F000000 // Mask Byte Control
465
#define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF // MAC Address1 [47:32]
466
#define EMAC_ADDR1H_MBC_S 24
467
#define EMAC_ADDR1H_ADDRHI_S 0
468
469
//*****************************************************************************
470
//
471
// The following are defines for the bit fields in the EMAC_O_ADDR1L register.
472
//
473
//*****************************************************************************
474
#define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF // MAC Address1 [31:0]
475
#define EMAC_ADDR1L_ADDRLO_S 0
476
477
//*****************************************************************************
478
//
479
// The following are defines for the bit fields in the EMAC_O_ADDR2H register.
480
//
481
//*****************************************************************************
482
#define EMAC_ADDR2H_AE 0x80000000 // Address Enable
483
#define EMAC_ADDR2H_SA 0x40000000 // Source Address
484
#define EMAC_ADDR2H_MBC_M 0x3F000000 // Mask Byte Control
485
#define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF // MAC Address2 [47:32]
486
#define EMAC_ADDR2H_MBC_S 24
487
#define EMAC_ADDR2H_ADDRHI_S 0
488
489
//*****************************************************************************
490
//
491
// The following are defines for the bit fields in the EMAC_O_ADDR2L register.
492
//
493
//*****************************************************************************
494
#define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF // MAC Address2 [31:0]
495
#define EMAC_ADDR2L_ADDRLO_S 0
496
497
//*****************************************************************************
498
//
499
// The following are defines for the bit fields in the EMAC_O_ADDR3H register.
500
//
501
//*****************************************************************************
502
#define EMAC_ADDR3H_AE 0x80000000 // Address Enable
503
#define EMAC_ADDR3H_SA 0x40000000 // Source Address
504
#define EMAC_ADDR3H_MBC_M 0x3F000000 // Mask Byte Control
505
#define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF // MAC Address3 [47:32]
506
#define EMAC_ADDR3H_MBC_S 24
507
#define EMAC_ADDR3H_ADDRHI_S 0
508
509
//*****************************************************************************
510
//
511
// The following are defines for the bit fields in the EMAC_O_ADDR3L register.
512
//
513
//*****************************************************************************
514
#define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF // MAC Address3 [31:0]
515
#define EMAC_ADDR3L_ADDRLO_S 0
516
517
//*****************************************************************************
518
//
519
// The following are defines for the bit fields in the EMAC_O_WDOGTO register.
520
//
521
//*****************************************************************************
522
#define EMAC_WDOGTO_PWE 0x00010000 // Programmable Watchdog Enable
523
#define EMAC_WDOGTO_WTO_M 0x00003FFF // Watchdog Timeout
524
#define EMAC_WDOGTO_WTO_S 0
525
526
//*****************************************************************************
527
//
528
// The following are defines for the bit fields in the EMAC_O_MMCCTRL register.
529
//
530
//*****************************************************************************
531
#define EMAC_MMCCTRL_UCDBC 0x00000100 // Update MMC Counters for Dropped
532
// Broadcast Frames
533
#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020 // Full/Half Preset Level Value
534
#define EMAC_MMCCTRL_CNTPRST 0x00000010 // Counters Preset
535
#define EMAC_MMCCTRL_CNTFREEZ 0x00000008 // MMC Counter Freeze
536
#define EMAC_MMCCTRL_RSTONRD 0x00000004 // Reset on Read
537
#define EMAC_MMCCTRL_CNTSTPRO 0x00000002 // Counters Stop Rollover
538
#define EMAC_MMCCTRL_CNTRST 0x00000001 // Counters Reset
539
540
//*****************************************************************************
541
//
542
// The following are defines for the bit fields in the EMAC_O_MMCRXRIS
543
// register.
544
//
545
//*****************************************************************************
546
#define EMAC_MMCRXRIS_UCGF 0x00020000 // MMC Receive Unicast Good Frame
547
// Counter Interrupt Status
548
#define EMAC_MMCRXRIS_ALGNERR 0x00000040 // MMC Receive Alignment Error
549
// Frame Counter Interrupt Status
550
#define EMAC_MMCRXRIS_CRCERR 0x00000020 // MMC Receive CRC Error Frame
551
// Counter Interrupt Status
552
#define EMAC_MMCRXRIS_GBF 0x00000001 // MMC Receive Good Bad Frame
553
// Counter Interrupt Status
554
555
//*****************************************************************************
556
//
557
// The following are defines for the bit fields in the EMAC_O_MMCTXRIS
558
// register.
559
//
560
//*****************************************************************************
561
#define EMAC_MMCTXRIS_OCTCNT 0x00100000 // Octet Counter Interrupt Status
562
#define EMAC_MMCTXRIS_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision
563
// Good Frame Counter Interrupt
564
// Status
565
#define EMAC_MMCTXRIS_SCOLLGF 0x00004000 // MMC Transmit Single Collision
566
// Good Frame Counter Interrupt
567
// Status
568
#define EMAC_MMCTXRIS_GBF 0x00000002 // MMC Transmit Good Bad Frame
569
// Counter Interrupt Status
570
571
//*****************************************************************************
572
//
573
// The following are defines for the bit fields in the EMAC_O_MMCRXIM register.
574
//
575
//*****************************************************************************
576
#define EMAC_MMCRXIM_UCGF 0x00020000 // MMC Receive Unicast Good Frame
577
// Counter Interrupt Mask
578
#define EMAC_MMCRXIM_ALGNERR 0x00000040 // MMC Receive Alignment Error
579
// Frame Counter Interrupt Mask
580
#define EMAC_MMCRXIM_CRCERR 0x00000020 // MMC Receive CRC Error Frame
581
// Counter Interrupt Mask
582
#define EMAC_MMCRXIM_GBF 0x00000001 // MMC Receive Good Bad Frame
583
// Counter Interrupt Mask
584
585
//*****************************************************************************
586
//
587
// The following are defines for the bit fields in the EMAC_O_MMCTXIM register.
588
//
589
//*****************************************************************************
590
#define EMAC_MMCTXIM_OCTCNT 0x00100000 // MMC Transmit Good Octet Counter
591
// Interrupt Mask
592
#define EMAC_MMCTXIM_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision
593
// Good Frame Counter Interrupt
594
// Mask
595
#define EMAC_MMCTXIM_SCOLLGF 0x00004000 // MMC Transmit Single Collision
596
// Good Frame Counter Interrupt
597
// Mask
598
#define EMAC_MMCTXIM_GBF 0x00000002 // MMC Transmit Good Bad Frame
599
// Counter Interrupt Mask
600
601
//*****************************************************************************
602
//
603
// The following are defines for the bit fields in the EMAC_O_TXCNTGB register.
604
//
605
//*****************************************************************************
606
#define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF // This field indicates the number
607
// of good and bad frames
608
// transmitted, exclusive of
609
// retried frames
610
#define EMAC_TXCNTGB_TXFRMGB_S 0
611
612
//*****************************************************************************
613
//
614
// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL
615
// register.
616
//
617
//*****************************************************************************
618
#define EMAC_TXCNTSCOL_TXSNGLCOLG_M \
619
0xFFFFFFFF // This field indicates the number
620
// of successfully transmitted
621
// frames after a single collision
622
// in the half-duplex mode
623
#define EMAC_TXCNTSCOL_TXSNGLCOLG_S \
624
0
625
626
//*****************************************************************************
627
//
628
// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL
629
// register.
630
//
631
//*****************************************************************************
632
#define EMAC_TXCNTMCOL_TXMULTCOLG_M \
633
0xFFFFFFFF // This field indicates the number
634
// of successfully transmitted
635
// frames after multiple collisions
636
// in the half-duplex mode
637
#define EMAC_TXCNTMCOL_TXMULTCOLG_S \
638
0
639
640
//*****************************************************************************
641
//
642
// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG
643
// register.
644
//
645
//*****************************************************************************
646
#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF // This field indicates the number
647
// of bytes transmitted, exclusive
648
// of preamble, in good frames
649
#define EMAC_TXOCTCNTG_TXOCTG_S 0
650
651
//*****************************************************************************
652
//
653
// The following are defines for the bit fields in the EMAC_O_RXCNTGB register.
654
//
655
//*****************************************************************************
656
#define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF // This field indicates the number
657
// of received good and bad frames
658
#define EMAC_RXCNTGB_RXFRMGB_S 0
659
660
//*****************************************************************************
661
//
662
// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR
663
// register.
664
//
665
//*****************************************************************************
666
#define EMAC_RXCNTCRCERR_RXCRCERR_M \
667
0xFFFFFFFF // This field indicates the number
668
// of frames received with CRC
669
// error
670
#define EMAC_RXCNTCRCERR_RXCRCERR_S \
671
0
672
673
//*****************************************************************************
674
//
675
// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR
676
// register.
677
//
678
//*****************************************************************************
679
#define EMAC_RXCNTALGNERR_RXALGNERR_M \
680
0xFFFFFFFF // This field indicates the number
681
// of frames received with
682
// alignment (dribble) error
683
#define EMAC_RXCNTALGNERR_RXALGNERR_S \
684
0
685
686
//*****************************************************************************
687
//
688
// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI
689
// register.
690
//
691
//*****************************************************************************
692
#define EMAC_RXCNTGUNI_RXUCASTG_M \
693
0xFFFFFFFF // This field indicates the number
694
// of received good unicast frames
695
#define EMAC_RXCNTGUNI_RXUCASTG_S \
696
0
697
698
//*****************************************************************************
699
//
700
// The following are defines for the bit fields in the EMAC_O_VLNINCREP
701
// register.
702
//
703
//*****************************************************************************
704
#define EMAC_VLNINCREP_CSVL 0x00080000 // C-VLAN or S-VLAN
705
#define EMAC_VLNINCREP_VLP 0x00040000 // VLAN Priority Control
706
#define EMAC_VLNINCREP_VLC_M 0x00030000 // VLAN Tag Control in Transmit
707
// Frames
708
#define EMAC_VLNINCREP_VLC_NONE 0x00000000 // No VLAN tag deletion, insertion,
709
// or replacement
710
#define EMAC_VLNINCREP_VLC_TAGDEL \
711
0x00010000 // VLAN tag deletion
712
#define EMAC_VLNINCREP_VLC_TAGINS \
713
0x00020000 // VLAN tag insertion
714
#define EMAC_VLNINCREP_VLC_TAGREP \
715
0x00030000 // VLAN tag replacement
716
#define EMAC_VLNINCREP_VLT_M 0x0000FFFF // VLAN Tag for Transmit Frames
717
#define EMAC_VLNINCREP_VLT_S 0
718
719
//*****************************************************************************
720
//
721
// The following are defines for the bit fields in the EMAC_O_VLANHASH
722
// register.
723
//
724
//*****************************************************************************
725
#define EMAC_VLANHASH_VLHT_M 0x0000FFFF // VLAN Hash Table
726
#define EMAC_VLANHASH_VLHT_S 0
727
728
//*****************************************************************************
729
//
730
// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL
731
// register.
732
//
733
//*****************************************************************************
734
#define EMAC_TIMSTCTRL_PTPFLTR 0x00040000 // Enable MAC address for PTP Frame
735
// Filtering
736
#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000 // Select PTP packets for Taking
737
// Snapshots
738
#define EMAC_TIMSTCTRL_TSMAST 0x00008000 // Enable Snapshot for Messages
739
// Relevant to Master
740
#define EMAC_TIMSTCTRL_TSEVNT 0x00004000 // Enable Timestamp Snapshot for
741
// Event Messages
742
#define EMAC_TIMSTCTRL_PTPIPV4 0x00002000 // Enable Processing of PTP Frames
743
// Sent over IPv4-UDP
744
#define EMAC_TIMSTCTRL_PTPIPV6 0x00001000 // Enable Processing of PTP Frames
745
// Sent Over IPv6-UDP
746
#define EMAC_TIMSTCTRL_PTPETH 0x00000800 // Enable Processing of PTP Over
747
// Ethernet Frames
748
#define EMAC_TIMSTCTRL_PTPVER2 0x00000400 // Enable PTP Packet Processing For
749
// Version 2 Format
750
#define EMAC_TIMSTCTRL_DGTLBIN 0x00000200 // Timestamp Digital or Binary
751
// Rollover Control
752
#define EMAC_TIMSTCTRL_ALLF 0x00000100 // Enable Timestamp For All Frames
753
#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020 // Addend Register Update
754
#define EMAC_TIMSTCTRL_INTTRIG 0x00000010 // Timestamp Interrupt Trigger
755
// Enable
756
#define EMAC_TIMSTCTRL_TSUPDT 0x00000008 // Timestamp Update
757
#define EMAC_TIMSTCTRL_TSINIT 0x00000004 // Timestamp Initialize
758
#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002 // Timestamp Fine or Coarse Update
759
#define EMAC_TIMSTCTRL_TSEN 0x00000001 // Timestamp Enable
760
#define EMAC_TIMSTCTRL_SELPTP_S 16
761
762
//*****************************************************************************
763
//
764
// The following are defines for the bit fields in the EMAC_O_SUBSECINC
765
// register.
766
//
767
//*****************************************************************************
768
#define EMAC_SUBSECINC_SSINC_M 0x000000FF // Sub-second Increment Value
769
#define EMAC_SUBSECINC_SSINC_S 0
770
771
//*****************************************************************************
772
//
773
// The following are defines for the bit fields in the EMAC_O_TIMSEC register.
774
//
775
//*****************************************************************************
776
#define EMAC_TIMSEC_TSS_M 0xFFFFFFFF // Timestamp Second
777
#define EMAC_TIMSEC_TSS_S 0
778
779
//*****************************************************************************
780
//
781
// The following are defines for the bit fields in the EMAC_O_TIMNANO register.
782
//
783
//*****************************************************************************
784
#define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF // Timestamp Sub-Seconds
785
#define EMAC_TIMNANO_TSSS_S 0
786
787
//*****************************************************************************
788
//
789
// The following are defines for the bit fields in the EMAC_O_TIMSECU register.
790
//
791
//*****************************************************************************
792
#define EMAC_TIMSECU_TSS_M 0xFFFFFFFF // Timestamp Second
793
#define EMAC_TIMSECU_TSS_S 0
794
795
//*****************************************************************************
796
//
797
// The following are defines for the bit fields in the EMAC_O_TIMNANOU
798
// register.
799
//
800
//*****************************************************************************
801
#define EMAC_TIMNANOU_ADDSUB 0x80000000 // Add or subtract time
802
#define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF // Timestamp Sub-Second
803
#define EMAC_TIMNANOU_TSSS_S 0
804
805
//*****************************************************************************
806
//
807
// The following are defines for the bit fields in the EMAC_O_TIMADD register.
808
//
809
//*****************************************************************************
810
#define EMAC_TIMADD_TSAR_M 0xFFFFFFFF // Timestamp Addend Register
811
#define EMAC_TIMADD_TSAR_S 0
812
813
//*****************************************************************************
814
//
815
// The following are defines for the bit fields in the EMAC_O_TARGSEC register.
816
//
817
//*****************************************************************************
818
#define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF // Target Time Seconds Register
819
#define EMAC_TARGSEC_TSTR_S 0
820
821
//*****************************************************************************
822
//
823
// The following are defines for the bit fields in the EMAC_O_TARGNANO
824
// register.
825
//
826
//*****************************************************************************
827
#define EMAC_TARGNANO_TRGTBUSY 0x80000000 // Target Time Register Busy
828
#define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF // Target Timestamp Low Register
829
#define EMAC_TARGNANO_TTSLO_S 0
830
831
//*****************************************************************************
832
//
833
// The following are defines for the bit fields in the EMAC_O_HWORDSEC
834
// register.
835
//
836
//*****************************************************************************
837
#define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF // Target Timestamp Higher Word
838
// Register
839
#define EMAC_HWORDSEC_TSHWR_S 0
840
841
//*****************************************************************************
842
//
843
// The following are defines for the bit fields in the EMAC_O_TIMSTAT register.
844
//
845
//*****************************************************************************
846
#define EMAC_TIMSTAT_TSTARGT 0x00000002 // Timestamp Target Time Reached
847
#define EMAC_TIMSTAT_TSSOVF 0x00000001 // Timestamp Seconds Overflow
848
849
//*****************************************************************************
850
//
851
// The following are defines for the bit fields in the EMAC_O_PPSCTRL register.
852
//
853
//*****************************************************************************
854
#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060 // Target Time Register Mode for
855
// PPS0 Output
856
#define EMAC_PPSCTRL_TRGMODS0_INTONLY \
857
0x00000000 // Indicates that the Target Time
858
// registers are programmed only
859
// for generating the interrupt
860
// event
861
#define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \
862
0x00000040 // Indicates that the Target Time
863
// registers are programmed for
864
// generating the interrupt event
865
// and starting or stopping the
866
// generation of the EN0PPS output
867
// signal
868
#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \
869
0x00000060 // Indicates that the Target Time
870
// registers are programmed only
871
// for starting or stopping the
872
// generation of the EN0PPS output
873
// signal. No interrupt is asserted
874
#define EMAC_PPSCTRL_PPSEN0 0x00000010 // Flexible PPS Output Mode Enable
875
#define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control
876
// (PPSCTRL) or Command Control
877
// (PPSCMD)
878
#define EMAC_PPSCTRL_PPSCTRL_1HZ \
879
0x00000000 // When the PPSEN0 bit = 0x0, the
880
// EN0PPS signal is 1 pulse of the
881
// PTP reference clock.(of width
882
// clk_ptp_i) every second
883
#define EMAC_PPSCTRL_PPSCTRL_2HZ \
884
0x00000001 // When the PPSEN0 bit = 0x0, the
885
// binary rollover is 2 Hz, and the
886
// digital rollover is 1 Hz
887
#define EMAC_PPSCTRL_PPSCTRL_4HZ \
888
0x00000002 // When the PPSEN0 bit = 0x0, the
889
// binary rollover is 4 Hz, and the
890
// digital rollover is 2 Hz
891
#define EMAC_PPSCTRL_PPSCTRL_8HZ \
892
0x00000003 // When thePPSEN0 bit = 0x0, the
893
// binary rollover is 8 Hz, and the
894
// digital rollover is 4 Hz,
895
#define EMAC_PPSCTRL_PPSCTRL_16HZ \
896
0x00000004 // When thePPSEN0 bit = 0x0, the
897
// binary rollover is 16 Hz, and
898
// the digital rollover is 8 Hz
899
#define EMAC_PPSCTRL_PPSCTRL_32HZ \
900
0x00000005 // When thePPSEN0 bit = 0x0, the
901
// binary rollover is 32 Hz, and
902
// the digital rollover is 16 Hz
903
#define EMAC_PPSCTRL_PPSCTRL_64HZ \
904
0x00000006 // When thePPSEN0 bit = 0x0, the
905
// binary rollover is 64 Hz, and
906
// the digital rollover is 32 Hz
907
#define EMAC_PPSCTRL_PPSCTRL_128HZ \
908
0x00000007 // When thePPSEN0 bit = 0x0, the
909
// binary rollover is 128 Hz, and
910
// the digital rollover is 64 Hz
911
#define EMAC_PPSCTRL_PPSCTRL_256HZ \
912
0x00000008 // When thePPSEN0 bit = 0x0, the
913
// binary rollover is 256 Hz, and
914
// the digital rollover is 128 Hz
915
#define EMAC_PPSCTRL_PPSCTRL_512HZ \
916
0x00000009 // When thePPSEN0 bit = 0x0, the
917
// binary rollover is 512 Hz, and
918
// the digital rollover is 256 Hz
919
#define EMAC_PPSCTRL_PPSCTRL_1024HZ \
920
0x0000000A // When the PPSEN0 bit = 0x0, the
921
// binary rollover is 1.024 kHz,
922
// and the digital rollover is 512
923
// Hz
924
#define EMAC_PPSCTRL_PPSCTRL_2048HZ \
925
0x0000000B // When thePPSEN0 bit = 0x0, the
926
// binary rollover is 2.048 kHz,
927
// and the digital rollover is
928
// 1.024 kHz
929
#define EMAC_PPSCTRL_PPSCTRL_4096HZ \
930
0x0000000C // When thePPSEN0 bit = 0x0, the
931
// binary rollover is 4.096 kHz,
932
// and the digital rollover is
933
// 2.048 kHz
934
#define EMAC_PPSCTRL_PPSCTRL_8192HZ \
935
0x0000000D // When thePPSEN0 bit = 0x0, the
936
// binary rollover is 8.192 kHz,
937
// and the digital rollover is
938
// 4.096 kHz
939
#define EMAC_PPSCTRL_PPSCTRL_16384HZ \
940
0x0000000E // When thePPSEN0 bit = 0x0, the
941
// binary rollover is 16.384 kHz,
942
// and the digital rollover is
943
// 8.092 kHz
944
#define EMAC_PPSCTRL_PPSCTRL_32768HZ \
945
0x0000000F // When thePPSEN0 bit = 0x0, the
946
// binary rollover is 32.768 KHz,
947
// and the digital rollover is
948
// 16.384 KHz
949
950
//*****************************************************************************
951
//
952
// The following are defines for the bit fields in the EMAC_O_PPS0INTVL
953
// register.
954
//
955
//*****************************************************************************
956
#define EMAC_PPS0INTVL_PPS0INT_M \
957
0xFFFFFFFF // PPS0 Output Signal Interval
958
#define EMAC_PPS0INTVL_PPS0INT_S \
959
0
960
961
//*****************************************************************************
962
//
963
// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH
964
// register.
965
//
966
//*****************************************************************************
967
#define EMAC_PPS0WIDTH_M 0xFFFFFFFF // EN0PPS Output Signal Width
968
#define EMAC_PPS0WIDTH_S 0
969
970
//*****************************************************************************
971
//
972
// The following are defines for the bit fields in the EMAC_O_DMABUSMOD
973
// register.
974
//
975
//*****************************************************************************
976
#define EMAC_DMABUSMOD_RIB 0x80000000 // Rebuild Burst
977
#define EMAC_DMABUSMOD_TXPR 0x08000000 // Transmit Priority
978
#define EMAC_DMABUSMOD_MB 0x04000000 // Mixed Burst
979
#define EMAC_DMABUSMOD_AAL 0x02000000 // Address Aligned Beats
980
#define EMAC_DMABUSMOD_8XPBL 0x01000000 // 8 x Programmable Burst Length
981
// (PBL) Mode
982
#define EMAC_DMABUSMOD_USP 0x00800000 // Use Separate Programmable Burst
983
// Length (PBL)
984
#define EMAC_DMABUSMOD_RPBL_M 0x007E0000 // RX DMA Programmable Burst Length
985
// (PBL)
986
#define EMAC_DMABUSMOD_FB 0x00010000 // Fixed Burst
987
#define EMAC_DMABUSMOD_PR_M 0x0000C000 // Priority Ratio
988
#define EMAC_DMABUSMOD_PBL_M 0x00003F00 // Programmable Burst Length
989
#define EMAC_DMABUSMOD_ATDS 0x00000080 // Alternate Descriptor Size
990
#define EMAC_DMABUSMOD_DSL_M 0x0000007C // Descriptor Skip Length
991
#define EMAC_DMABUSMOD_DA 0x00000002 // DMA Arbitration Scheme
992
#define EMAC_DMABUSMOD_SWR 0x00000001 // DMA Software Reset
993
#define EMAC_DMABUSMOD_RPBL_S 17
994
#define EMAC_DMABUSMOD_PR_S 14
995
#define EMAC_DMABUSMOD_PBL_S 8
996
#define EMAC_DMABUSMOD_DSL_S 2
997
998
//*****************************************************************************
999
//
1000
// The following are defines for the bit fields in the EMAC_O_TXPOLLD register.
1001
//
1002
//*****************************************************************************
1003
#define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF // Transmit Poll Demand
1004
#define EMAC_TXPOLLD_TPD_S 0
1005
1006
//*****************************************************************************
1007
//
1008
// The following are defines for the bit fields in the EMAC_O_RXPOLLD register.
1009
//
1010
//*****************************************************************************
1011
#define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF // Receive Poll Demand
1012
#define EMAC_RXPOLLD_RPD_S 0
1013
1014
//*****************************************************************************
1015
//
1016
// The following are defines for the bit fields in the EMAC_O_RXDLADDR
1017
// register.
1018
//
1019
//*****************************************************************************
1020
#define EMAC_RXDLADDR_STRXLIST_M \
1021
0xFFFFFFFC // Start of Receive List
1022
#define EMAC_RXDLADDR_STRXLIST_S \
1023
2
1024
1025
//*****************************************************************************
1026
//
1027
// The following are defines for the bit fields in the EMAC_O_TXDLADDR
1028
// register.
1029
//
1030
//*****************************************************************************
1031
#define EMAC_TXDLADDR_TXDLADDR_M \
1032
0xFFFFFFFC // Start of Transmit List Base
1033
// Address
1034
#define EMAC_TXDLADDR_TXDLADDR_S \
1035
2
1036
1037
//*****************************************************************************
1038
//
1039
// The following are defines for the bit fields in the EMAC_O_DMARIS register.
1040
//
1041
//*****************************************************************************
1042
#define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt
1043
// Status
1044
#define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status
1045
#define EMAC_DMARIS_MMC 0x08000000 // MAC MMC Interrupt
1046
#define EMAC_DMARIS_AE_M 0x03800000 // Access Error
1047
#define EMAC_DMARIS_AE_RXDMAWD 0x00000000 // Error during RX DMA Write Data
1048
// Transfer
1049
#define EMAC_DMARIS_AE_TXDMARD 0x01800000 // Error during TX DMA Read Data
1050
// Transfer
1051
#define EMAC_DMARIS_AE_RXDMADW 0x02000000 // Error during RX DMA Descriptor
1052
// Write Access
1053
#define EMAC_DMARIS_AE_TXDMADW 0x02800000 // Error during TX DMA Descriptor
1054
// Write Access
1055
#define EMAC_DMARIS_AE_RXDMADR 0x03000000 // Error during RX DMA Descriptor
1056
// Read Access
1057
#define EMAC_DMARIS_AE_TXDMADR 0x03800000 // Error during TX DMA Descriptor
1058
// Read Access
1059
#define EMAC_DMARIS_TS_M 0x00700000 // Transmit Process State
1060
#define EMAC_DMARIS_TS_STOP 0x00000000 // Stopped; Reset or Stop transmit
1061
// command processed
1062
#define EMAC_DMARIS_TS_RUNTXTD 0x00100000 // Running; Fetching transmit
1063
// transfer descriptor
1064
#define EMAC_DMARIS_TS_STATUS 0x00200000 // Running; Waiting for status
1065
#define EMAC_DMARIS_TS_RUNTX 0x00300000 // Running; Reading data from host
1066
// memory buffer and queuing it to
1067
// transmit buffer (TX FIFO)
1068
#define EMAC_DMARIS_TS_TSTAMP 0x00400000 // Writing Timestamp
1069
#define EMAC_DMARIS_TS_SUSPEND 0x00600000 // Suspended; Transmit descriptor
1070
// unavailable or transmit buffer
1071
// underflow
1072
#define EMAC_DMARIS_TS_RUNCTD 0x00700000 // Running; Closing transmit
1073
// descriptor
1074
#define EMAC_DMARIS_RS_M 0x000E0000 // Received Process State
1075
#define EMAC_DMARIS_RS_STOP 0x00000000 // Stopped: Reset or stop receive
1076
// command issued
1077
#define EMAC_DMARIS_RS_RUNRXTD 0x00020000 // Running: Fetching receive
1078
// transfer descriptor
1079
#define EMAC_DMARIS_RS_RUNRXD 0x00060000 // Running: Waiting for receive
1080
// packet
1081
#define EMAC_DMARIS_RS_SUSPEND 0x00080000 // Suspended: Receive descriptor
1082
// unavailable
1083
#define EMAC_DMARIS_RS_RUNCRD 0x000A0000 // Running: Closing receive
1084
// descriptor
1085
#define EMAC_DMARIS_RS_TSWS 0x000C0000 // Writing Timestamp
1086
#define EMAC_DMARIS_RS_RUNTXD 0x000E0000 // Running: Transferring the
1087
// receive packet data from receive
1088
// buffer to host memory
1089
#define EMAC_DMARIS_NIS 0x00010000 // Normal Interrupt Summary
1090
#define EMAC_DMARIS_AIS 0x00008000 // Abnormal Interrupt Summary
1091
#define EMAC_DMARIS_ERI 0x00004000 // Early Receive Interrupt
1092
#define EMAC_DMARIS_FBI 0x00002000 // Fatal Bus Error Interrupt
1093
#define EMAC_DMARIS_ETI 0x00000400 // Early Transmit Interrupt
1094
#define EMAC_DMARIS_RWT 0x00000200 // Receive Watchdog Timeout
1095
#define EMAC_DMARIS_RPS 0x00000100 // Receive Process Stopped
1096
#define EMAC_DMARIS_RU 0x00000080 // Receive Buffer Unavailable
1097
#define EMAC_DMARIS_RI 0x00000040 // Receive Interrupt
1098
#define EMAC_DMARIS_UNF 0x00000020 // Transmit Underflow
1099
#define EMAC_DMARIS_OVF 0x00000010 // Receive Overflow
1100
#define EMAC_DMARIS_TJT 0x00000008 // Transmit Jabber Timeout
1101
#define EMAC_DMARIS_TU 0x00000004 // Transmit Buffer Unavailable
1102
#define EMAC_DMARIS_TPS 0x00000002 // Transmit Process Stopped
1103
#define EMAC_DMARIS_TI 0x00000001 // Transmit Interrupt
1104
1105
//*****************************************************************************
1106
//
1107
// The following are defines for the bit fields in the EMAC_O_DMAOPMODE
1108
// register.
1109
//
1110
//*****************************************************************************
1111
#define EMAC_DMAOPMODE_DT 0x04000000 // Disable Dropping of TCP/IP
1112
// Checksum Error Frames
1113
#define EMAC_DMAOPMODE_RSF 0x02000000 // Receive Store and Forward
1114
#define EMAC_DMAOPMODE_DFF 0x01000000 // Disable Flushing of Received
1115
// Frames
1116
#define EMAC_DMAOPMODE_TSF 0x00200000 // Transmit Store and Forward
1117
#define EMAC_DMAOPMODE_FTF 0x00100000 // Flush Transmit FIFO
1118
#define EMAC_DMAOPMODE_TTC_M 0x0001C000 // Transmit Threshold Control
1119
#define EMAC_DMAOPMODE_TTC_64 0x00000000 // 64 bytes
1120
#define EMAC_DMAOPMODE_TTC_128 0x00004000 // 128 bytes
1121
#define EMAC_DMAOPMODE_TTC_192 0x00008000 // 192 bytes
1122
#define EMAC_DMAOPMODE_TTC_256 0x0000C000 // 256 bytes
1123
#define EMAC_DMAOPMODE_TTC_40 0x00010000 // 40 bytes
1124
#define EMAC_DMAOPMODE_TTC_32 0x00014000 // 32 bytes
1125
#define EMAC_DMAOPMODE_TTC_24 0x00018000 // 24 bytes
1126
#define EMAC_DMAOPMODE_TTC_16 0x0001C000 // 16 bytes
1127
#define EMAC_DMAOPMODE_ST 0x00002000 // Start or Stop Transmission
1128
// Command
1129
#define EMAC_DMAOPMODE_FEF 0x00000080 // Forward Error Frames
1130
#define EMAC_DMAOPMODE_FUF 0x00000040 // Forward Undersized Good Frames
1131
#define EMAC_DMAOPMODE_DGF 0x00000020 // Drop Giant Frame Enable
1132
#define EMAC_DMAOPMODE_RTC_M 0x00000018 // Receive Threshold Control
1133
#define EMAC_DMAOPMODE_RTC_64 0x00000000 // 64 bytes
1134
#define EMAC_DMAOPMODE_RTC_32 0x00000008 // 32 bytes
1135
#define EMAC_DMAOPMODE_RTC_96 0x00000010 // 96 bytes
1136
#define EMAC_DMAOPMODE_RTC_128 0x00000018 // 128 bytes
1137
#define EMAC_DMAOPMODE_OSF 0x00000004 // Operate on Second Frame
1138
#define EMAC_DMAOPMODE_SR 0x00000002 // Start or Stop Receive
1139
1140
//*****************************************************************************
1141
//
1142
// The following are defines for the bit fields in the EMAC_O_DMAIM register.
1143
//
1144
//*****************************************************************************
1145
#define EMAC_DMAIM_NIE 0x00010000 // Normal Interrupt Summary Enable
1146
#define EMAC_DMAIM_AIE 0x00008000 // Abnormal Interrupt Summary
1147
// Enable
1148
#define EMAC_DMAIM_ERE 0x00004000 // Early Receive Interrupt Enable
1149
#define EMAC_DMAIM_FBE 0x00002000 // Fatal Bus Error Enable
1150
#define EMAC_DMAIM_ETE 0x00000400 // Early Transmit Interrupt Enable
1151
#define EMAC_DMAIM_RWE 0x00000200 // Receive Watchdog Timeout Enable
1152
#define EMAC_DMAIM_RSE 0x00000100 // Receive Stopped Enable
1153
#define EMAC_DMAIM_RUE 0x00000080 // Receive Buffer Unavailable
1154
// Enable
1155
#define EMAC_DMAIM_RIE 0x00000040 // Receive Interrupt Enable
1156
#define EMAC_DMAIM_UNE 0x00000020 // Underflow Interrupt Enable
1157
#define EMAC_DMAIM_OVE 0x00000010 // Overflow Interrupt Enable
1158
#define EMAC_DMAIM_TJE 0x00000008 // Transmit Jabber Timeout Enable
1159
#define EMAC_DMAIM_TUE 0x00000004 // Transmit Buffer Unvailable
1160
// Enable
1161
#define EMAC_DMAIM_TSE 0x00000002 // Transmit Stopped Enable
1162
#define EMAC_DMAIM_TIE 0x00000001 // Transmit Interrupt Enable
1163
1164
//*****************************************************************************
1165
//
1166
// The following are defines for the bit fields in the EMAC_O_MFBOC register.
1167
//
1168
//*****************************************************************************
1169
#define EMAC_MFBOC_OVFCNTOVF 0x10000000 // Overflow Bit for FIFO Overflow
1170
// Counter
1171
#define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000 // Overflow Frame Counter
1172
#define EMAC_MFBOC_MISCNTOVF 0x00010000 // Overflow bit for Missed Frame
1173
// Counter
1174
#define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF // Missed Frame Counter
1175
#define EMAC_MFBOC_OVFFRMCNT_S 17
1176
#define EMAC_MFBOC_MISFRMCNT_S 0
1177
1178
//*****************************************************************************
1179
//
1180
// The following are defines for the bit fields in the EMAC_O_RXINTWDT
1181
// register.
1182
//
1183
//*****************************************************************************
1184
#define EMAC_RXINTWDT_RIWT_M 0x000000FF // Receive Interrupt Watchdog Timer
1185
// Count
1186
#define EMAC_RXINTWDT_RIWT_S 0
1187
1188
//*****************************************************************************
1189
//
1190
// The following are defines for the bit fields in the EMAC_O_HOSTXDESC
1191
// register.
1192
//
1193
//*****************************************************************************
1194
#define EMAC_HOSTXDESC_CURTXDESC_M \
1195
0xFFFFFFFF // Host Transmit Descriptor Address
1196
// Pointer
1197
#define EMAC_HOSTXDESC_CURTXDESC_S \
1198
0
1199
1200
//*****************************************************************************
1201
//
1202
// The following are defines for the bit fields in the EMAC_O_HOSRXDESC
1203
// register.
1204
//
1205
//*****************************************************************************
1206
#define EMAC_HOSRXDESC_CURRXDESC_M \
1207
0xFFFFFFFF // Host Receive Descriptor Address
1208
// Pointer
1209
#define EMAC_HOSRXDESC_CURRXDESC_S \
1210
0
1211
1212
//*****************************************************************************
1213
//
1214
// The following are defines for the bit fields in the EMAC_O_HOSTXBA register.
1215
//
1216
//*****************************************************************************
1217
#define EMAC_HOSTXBA_CURTXBUFA_M \
1218
0xFFFFFFFF // Host Transmit Buffer Address
1219
// Pointer
1220
#define EMAC_HOSTXBA_CURTXBUFA_S \
1221
0
1222
1223
//*****************************************************************************
1224
//
1225
// The following are defines for the bit fields in the EMAC_O_HOSRXBA register.
1226
//
1227
//*****************************************************************************
1228
#define EMAC_HOSRXBA_CURRXBUFA_M \
1229
0xFFFFFFFF // Host Receive Buffer Address
1230
// Pointer
1231
#define EMAC_HOSRXBA_CURRXBUFA_S \
1232
0
1233
1234
//*****************************************************************************
1235
//
1236
// The following are defines for the bit fields in the EMAC_O_PP register.
1237
//
1238
//*****************************************************************************
1239
#define EMAC_PP_MACTYPE_M 0x00000700 // Ethernet MAC Type
1240
#define EMAC_PP_MACTYPE_1 0x00000100 // Tiva TM4E129x-class MAC
1241
#define EMAC_PP_PHYTYPE_M 0x00000007 // Ethernet PHY Type
1242
#define EMAC_PP_PHYTYPE_NONE 0x00000000 // No PHY
1243
#define EMAC_PP_PHYTYPE_1 0x00000003 // Snowflake class PHY
1244
1245
//*****************************************************************************
1246
//
1247
// The following are defines for the bit fields in the EMAC_O_PC register.
1248
//
1249
//*****************************************************************************
1250
#define EMAC_PC_PHYEXT 0x80000000 // PHY Select
1251
#define EMAC_PC_PINTFS_M 0x70000000 // Ethernet Interface Select
1252
#define EMAC_PC_PINTFS_IMII 0x00000000 // MII (default) Used for internal
1253
// PHY or external PHY connected
1254
// via MII
1255
#define EMAC_PC_PINTFS_RMII 0x40000000 // RMII: Used for external PHY
1256
// connected via RMII
1257
#define EMAC_PC_DIGRESTART 0x02000000 // PHY Soft Restart
1258
#define EMAC_PC_NIBDETDIS 0x01000000 // Odd Nibble TXER Detection
1259
// Disable
1260
#define EMAC_PC_RXERIDLE 0x00800000 // RXER Detection During Idle
1261
#define EMAC_PC_ISOMIILL 0x00400000 // Isolate MII in Link Loss
1262
#define EMAC_PC_LRR 0x00200000 // Link Loss Recovery
1263
#define EMAC_PC_TDRRUN 0x00100000 // TDR Auto Run
1264
#define EMAC_PC_FASTLDMODE_M 0x000F8000 // Fast Link Down Mode
1265
#define EMAC_PC_POLSWAP 0x00004000 // Polarity Swap
1266
#define EMAC_PC_MDISWAP 0x00002000 // MDI Swap
1267
#define EMAC_PC_RBSTMDIX 0x00001000 // Robust Auto MDI-X
1268
#define EMAC_PC_FASTMDIX 0x00000800 // Fast Auto MDI-X
1269
#define EMAC_PC_MDIXEN 0x00000400 // MDIX Enable
1270
#define EMAC_PC_FASTRXDV 0x00000200 // Fast RXDV Detection
1271
#define EMAC_PC_FASTLUPD 0x00000100 // FAST Link-Up in Parallel Detect
1272
#define EMAC_PC_EXTFD 0x00000080 // Extended Full Duplex Ability
1273
#define EMAC_PC_FASTANEN 0x00000040 // Fast Auto Negotiation Enable
1274
#define EMAC_PC_FASTANSEL_M 0x00000030 // Fast Auto Negotiation Select
1275
#define EMAC_PC_ANEN 0x00000008 // Auto Negotiation Enable
1276
#define EMAC_PC_ANMODE_M 0x00000006 // Auto Negotiation Mode
1277
#define EMAC_PC_ANMODE_10HD 0x00000000 // When ANEN = 0x0, the mode is
1278
// 10Base-T, Half-Duplex
1279
#define EMAC_PC_ANMODE_10FD 0x00000002 // When ANEN = 0x0, the mode is
1280
// 10Base-T, Full-Duplex
1281
#define EMAC_PC_ANMODE_100HD 0x00000004 // When ANEN = 0x0, the mode is
1282
// 100Base-TX, Half-Duplex
1283
#define EMAC_PC_ANMODE_100FD 0x00000006 // When ANEN = 0x0, the mode is
1284
// 100Base-TX, Full-Duplex
1285
#define EMAC_PC_PHYHOLD 0x00000001 // Ethernet PHY Hold
1286
#define EMAC_PC_FASTLDMODE_S 15
1287
#define EMAC_PC_FASTANSEL_S 4
1288
1289
//*****************************************************************************
1290
//
1291
// The following are defines for the bit fields in the EMAC_O_CC register.
1292
//
1293
//*****************************************************************************
1294
#define EMAC_CC_PTPCEN 0x00040000 // PTP Clock Reference Enable
1295
#define EMAC_CC_POL 0x00020000 // LED Polarity Control
1296
#define EMAC_CC_CLKEN 0x00010000 // EN0RREF_CLK Signal Enable
1297
1298
//*****************************************************************************
1299
//
1300
// The following are defines for the bit fields in the EMAC_O_EPHYRIS register.
1301
//
1302
//*****************************************************************************
1303
#define EMAC_EPHYRIS_INT 0x00000001 // Ethernet PHY Raw Interrupt
1304
// Status
1305
1306
//*****************************************************************************
1307
//
1308
// The following are defines for the bit fields in the EMAC_O_EPHYIM register.
1309
//
1310
//*****************************************************************************
1311
#define EMAC_EPHYIM_INT 0x00000001 // Ethernet PHY Interrupt Mask
1312
1313
//*****************************************************************************
1314
//
1315
// The following are defines for the bit fields in the EMAC_O_EPHYMISC
1316
// register.
1317
//
1318
//*****************************************************************************
1319
#define EMAC_EPHYMISC_INT 0x00000001 // Ethernet PHY Status and Clear
1320
// register
1321
1322
//*****************************************************************************
1323
//
1324
// The following are defines for the EPHY register offsets.
1325
//
1326
//*****************************************************************************
1327
#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control
1328
#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status
1329
#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register
1330
// 1
1331
#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register
1332
// 2
1333
#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation
1334
// Advertisement
1335
#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation
1336
// Link Partner Ability
1337
#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation
1338
// Expansion
1339
#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation
1340
// Next Page TX
1341
#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation
1342
// Link Partner Ability Next Page
1343
#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1
1344
#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2
1345
#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3
1346
#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control
1347
#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data
1348
#define EPHY_STS 0x00000010 // Ethernet PHY Status
1349
#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control
1350
#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt
1351
// Status 1
1352
#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt
1353
// Status 2
1354
#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense
1355
// Counter
1356
#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count
1357
#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control
1358
#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control
1359
#define EPHY_CTL 0x00000019 // Ethernet PHY Control
1360
#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T
1361
// Status/Control - MR26
1362
#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and
1363
// Status 1
1364
#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and
1365
// Status 2
1366
#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic
1367
// Control
1368
#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control
1369
#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration
1370
1371
//*****************************************************************************
1372
//
1373
// The following are defines for the bit fields in the EPHY_BMCR register.
1374
//
1375
//*****************************************************************************
1376
#define EPHY_BMCR_MIIRESET 0x00008000 // MII Register reset
1377
#define EPHY_BMCR_MIILOOPBK 0x00004000 // MII Loopback
1378
#define EPHY_BMCR_SPEED 0x00002000 // Speed Select
1379
#define EPHY_BMCR_ANEN 0x00001000 // Auto-Negotiate Enable
1380
#define EPHY_BMCR_PWRDWN 0x00000800 // Power Down
1381
#define EPHY_BMCR_ISOLATE 0x00000400 // Port Isolate
1382
#define EPHY_BMCR_RESTARTAN 0x00000200 // Restart Auto-Negotiation
1383
#define EPHY_BMCR_DUPLEXM 0x00000100 // Duplex Mode
1384
#define EPHY_BMCR_COLLTST 0x00000080 // Collision Test
1385
1386
//*****************************************************************************
1387
//
1388
// The following are defines for the bit fields in the EPHY_BMSR register.
1389
//
1390
//*****************************************************************************
1391
#define EPHY_BMSR_100BTXFD 0x00004000 // 100Base-TX Full Duplex Capable
1392
#define EPHY_BMSR_100BTXHD 0x00002000 // 100Base-TX Half Duplex Capable
1393
#define EPHY_BMSR_10BTFD 0x00001000 // 10 Base-T Full Duplex Capable
1394
#define EPHY_BMSR_10BTHD 0x00000800 // 10 Base-T Half Duplex Capable
1395
#define EPHY_BMSR_MFPRESUP 0x00000040 // Preamble Suppression Capable
1396
#define EPHY_BMSR_ANC 0x00000020 // Auto-Negotiation Complete
1397
#define EPHY_BMSR_RFAULT 0x00000010 // Remote Fault
1398
#define EPHY_BMSR_ANEN 0x00000008 // Auto Negotiation Enabled
1399
#define EPHY_BMSR_LINKSTAT 0x00000004 // Link Status
1400
#define EPHY_BMSR_JABBER 0x00000002 // Jabber Detect
1401
#define EPHY_BMSR_EXTEN 0x00000001 // Extended Capability Enable
1402
1403
//*****************************************************************************
1404
//
1405
// The following are defines for the bit fields in the EPHY_ID1 register.
1406
//
1407
//*****************************************************************************
1408
#define EPHY_ID1_OUIMSB_M 0x0000FFFF // OUI Most Significant Bits
1409
#define EPHY_ID1_OUIMSB_S 0
1410
1411
//*****************************************************************************
1412
//
1413
// The following are defines for the bit fields in the EPHY_ID2 register.
1414
//
1415
//*****************************************************************************
1416
#define EPHY_ID2_OUILSB_M 0x0000FC00 // OUI Least Significant Bits
1417
#define EPHY_ID2_VNDRMDL_M 0x000003F0 // Vendor Model Number
1418
#define EPHY_ID2_MDLREV_M 0x0000000F // Model Revision Number
1419
#define EPHY_ID2_OUILSB_S 10
1420
#define EPHY_ID2_VNDRMDL_S 4
1421
#define EPHY_ID2_MDLREV_S 0
1422
1423
//*****************************************************************************
1424
//
1425
// The following are defines for the bit fields in the EPHY_ANA register.
1426
//
1427
//*****************************************************************************
1428
#define EPHY_ANA_NP 0x00008000 // Next Page Indication
1429
#define EPHY_ANA_RF 0x00002000 // Remote Fault
1430
#define EPHY_ANA_ASMDUP 0x00000800 // Asymmetric PAUSE support for
1431
// Full Duplex Links
1432
#define EPHY_ANA_PAUSE 0x00000400 // PAUSE Support for Full Duplex
1433
// Links
1434
#define EPHY_ANA_100BT4 0x00000200 // 100Base-T4 Support
1435
#define EPHY_ANA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support
1436
#define EPHY_ANA_100BTX 0x00000080 // 100Base-TX Support
1437
#define EPHY_ANA_10BTFD 0x00000040 // 10Base-T Full Duplex Support
1438
#define EPHY_ANA_10BT 0x00000020 // 10Base-T Support
1439
#define EPHY_ANA_SELECT_M 0x0000001F // Protocol Selection
1440
#define EPHY_ANA_SELECT_S 0
1441
1442
//*****************************************************************************
1443
//
1444
// The following are defines for the bit fields in the EPHY_ANLPA register.
1445
//
1446
//*****************************************************************************
1447
#define EPHY_ANLPA_NP 0x00008000 // Next Page Indication
1448
#define EPHY_ANLPA_ACK 0x00004000 // Acknowledge
1449
#define EPHY_ANLPA_RF 0x00002000 // Remote Fault
1450
#define EPHY_ANLPA_ASMDUP 0x00000800 // Asymmetric PAUSE
1451
#define EPHY_ANLPA_PAUSE 0x00000400 // PAUSE
1452
#define EPHY_ANLPA_100BT4 0x00000200 // 100Base-T4 Support
1453
#define EPHY_ANLPA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support
1454
#define EPHY_ANLPA_100BTX 0x00000080 // 100Base-TX Support
1455
#define EPHY_ANLPA_10BTFD 0x00000040 // 10Base-T Full Duplex Support
1456
#define EPHY_ANLPA_10BT 0x00000020 // 10Base-T Support
1457
#define EPHY_ANLPA_SELECT_M 0x0000001F // Protocol Selection
1458
#define EPHY_ANLPA_SELECT_S 0
1459
1460
//*****************************************************************************
1461
//
1462
// The following are defines for the bit fields in the EPHY_ANER register.
1463
//
1464
//*****************************************************************************
1465
#define EPHY_ANER_PDF 0x00000010 // Parallel Detection Fault
1466
#define EPHY_ANER_LPNPABLE 0x00000008 // Link Partner Next Page Able
1467
#define EPHY_ANER_NPABLE 0x00000004 // Next Page Able
1468
#define EPHY_ANER_PAGERX 0x00000002 // Link Code Word Page Received
1469
#define EPHY_ANER_LPANABLE 0x00000001 // Link Partner Auto-Negotiation
1470
// Able
1471
1472
//*****************************************************************************
1473
//
1474
// The following are defines for the bit fields in the EPHY_ANNPTR register.
1475
//
1476
//*****************************************************************************
1477
#define EPHY_ANNPTR_NP 0x00008000 // Next Page Indication
1478
#define EPHY_ANNPTR_MP 0x00002000 // Message Page
1479
#define EPHY_ANNPTR_ACK2 0x00001000 // Acknowledge 2
1480
#define EPHY_ANNPTR_TOGTX 0x00000800 // Toggle
1481
#define EPHY_ANNPTR_CODE_M 0x000007FF // Code
1482
#define EPHY_ANNPTR_CODE_S 0
1483
1484
//*****************************************************************************
1485
//
1486
// The following are defines for the bit fields in the EPHY_ANLNPTR register.
1487
//
1488
//*****************************************************************************
1489
#define EPHY_ANLNPTR_NP 0x00008000 // Next Page Indication
1490
#define EPHY_ANLNPTR_ACK 0x00004000 // Acknowledge
1491
#define EPHY_ANLNPTR_MP 0x00002000 // Message Page
1492
#define EPHY_ANLNPTR_ACK2 0x00001000 // Acknowledge 2
1493
#define EPHY_ANLNPTR_TOG 0x00000800 // Toggle
1494
#define EPHY_ANLNPTR_CODE_M 0x000007FF // Code
1495
#define EPHY_ANLNPTR_CODE_S 0
1496
1497
//*****************************************************************************
1498
//
1499
// The following are defines for the bit fields in the EPHY_CFG1 register.
1500
//
1501
//*****************************************************************************
1502
#define EPHY_CFG1_DONE 0x00008000 // Configuration Done
1503
#define EPHY_CFG1_TDRAR 0x00000100 // TDR Auto-Run at Link Down
1504
#define EPHY_CFG1_LLR 0x00000080 // Link Loss Recovery
1505
#define EPHY_CFG1_FAMDIX 0x00000040 // Fast Auto MDI/MDIX
1506
#define EPHY_CFG1_RAMDIX 0x00000020 // Robust Auto MDI/MDIX
1507
#define EPHY_CFG1_FASTANEN 0x00000010 // Fast Auto Negotiation Enable
1508
#define EPHY_CFG1_FANSEL_M 0x0000000C // Fast Auto-Negotiation Select
1509
// Configuration
1510
#define EPHY_CFG1_FANSEL_BLT80 0x00000000 // Break Link Timer: 80 ms
1511
#define EPHY_CFG1_FANSEL_BLT120 0x00000004 // Break Link Timer: 120 ms
1512
#define EPHY_CFG1_FANSEL_BLT240 0x00000008 // Break Link Timer: 240 ms
1513
#define EPHY_CFG1_FRXDVDET 0x00000002 // FAST RXDV Detection
1514
1515
//*****************************************************************************
1516
//
1517
// The following are defines for the bit fields in the EPHY_CFG2 register.
1518
//
1519
//*****************************************************************************
1520
#define EPHY_CFG2_FLUPPD 0x00000040 // Fast Link-Up in Parallel Detect
1521
// Mode
1522
#define EPHY_CFG2_EXTFD 0x00000020 // Extended Full-Duplex Ability
1523
#define EPHY_CFG2_ENLEDLINK 0x00000010 // Enhanced LED Functionality
1524
#define EPHY_CFG2_ISOMIILL 0x00000008 // Isolate MII outputs when
1525
// Enhanced Link is not Achievable
1526
#define EPHY_CFG2_RXERRIDLE 0x00000004 // Detection of Receive Symbol
1527
// Error During IDLE State
1528
#define EPHY_CFG2_ODDNDETDIS 0x00000002 // Detection of Transmit Error
1529
1530
//*****************************************************************************
1531
//
1532
// The following are defines for the bit fields in the EPHY_CFG3 register.
1533
//
1534
//*****************************************************************************
1535
#define EPHY_CFG3_POLSWAP 0x00000080 // Polarity Swap
1536
#define EPHY_CFG3_MDIMDIXS 0x00000040 // MDI/MDIX Swap
1537
#define EPHY_CFG3_FLDWNM_M 0x0000001F // Fast Link Down Modes
1538
#define EPHY_CFG3_FLDWNM_S 0
1539
1540
//*****************************************************************************
1541
//
1542
// The following are defines for the bit fields in the EPHY_REGCTL register.
1543
//
1544
//*****************************************************************************
1545
#define EPHY_REGCTL_FUNC_M 0x0000C000 // Function
1546
#define EPHY_REGCTL_FUNC_ADDR 0x00000000 // Address
1547
#define EPHY_REGCTL_FUNC_DATANI 0x00004000 // Data, no post increment
1548
#define EPHY_REGCTL_FUNC_DATAPIRW \
1549
0x00008000 // Data, post increment on read and
1550
// write
1551
#define EPHY_REGCTL_FUNC_DATAPIWO \
1552
0x0000C000 // Data, post increment on write
1553
// only
1554
#define EPHY_REGCTL_DEVAD_M 0x0000001F // Device Address
1555
#define EPHY_REGCTL_DEVAD_S 0
1556
1557
//*****************************************************************************
1558
//
1559
// The following are defines for the bit fields in the EPHY_ADDAR register.
1560
//
1561
//*****************************************************************************
1562
#define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF // Address or Data
1563
#define EPHY_ADDAR_ADDRDATA_S 0
1564
1565
//*****************************************************************************
1566
//
1567
// The following are defines for the bit fields in the EPHY_STS register.
1568
//
1569
//*****************************************************************************
1570
#define EPHY_STS_MDIXM 0x00004000 // MDI-X Mode
1571
#define EPHY_STS_RXLERR 0x00002000 // Receive Error Latch
1572
#define EPHY_STS_POLSTAT 0x00001000 // Polarity Status
1573
#define EPHY_STS_FCSL 0x00000800 // False Carrier Sense Latch
1574
#define EPHY_STS_SD 0x00000400 // Signal Detect
1575
#define EPHY_STS_DL 0x00000200 // Descrambler Lock
1576
#define EPHY_STS_PAGERX 0x00000100 // Link Code Page Received
1577
#define EPHY_STS_MIIREQ 0x00000080 // MII Interrupt Pending
1578
#define EPHY_STS_RF 0x00000040 // Remote Fault
1579
#define EPHY_STS_JD 0x00000020 // Jabber Detect
1580
#define EPHY_STS_ANS 0x00000010 // Auto-Negotiation Status
1581
#define EPHY_STS_MIILB 0x00000008 // MII Loopback Status
1582
#define EPHY_STS_DUPLEX 0x00000004 // Duplex Status
1583
#define EPHY_STS_SPEED 0x00000002 // Speed Status
1584
#define EPHY_STS_LINK 0x00000001 // Link Status
1585
1586
//*****************************************************************************
1587
//
1588
// The following are defines for the bit fields in the EPHY_SCR register.
1589
//
1590
//*****************************************************************************
1591
#define EPHY_SCR_DISCLK 0x00008000 // Disable CLK
1592
#define EPHY_SCR_PSEN 0x00004000 // Power Saving Modes Enable
1593
#define EPHY_SCR_PSMODE_M 0x00003000 // Power Saving Modes
1594
#define EPHY_SCR_PSMODE_NORMAL 0x00000000 // Normal: Normal operation mode.
1595
// PHY is fully functional
1596
#define EPHY_SCR_PSMODE_LOWPWR 0x00001000 // IEEE Power Down
1597
#define EPHY_SCR_PSMODE_ACTWOL 0x00002000 // Active Sleep
1598
#define EPHY_SCR_PSMODE_PASWOL 0x00003000 // Passive Sleep
1599
#define EPHY_SCR_SBPYASS 0x00000800 // Scrambler Bypass
1600
#define EPHY_SCR_LBFIFO_M 0x00000300 // Loopback FIFO Depth
1601
#define EPHY_SCR_LBFIFO_4 0x00000000 // Four nibble FIFO
1602
#define EPHY_SCR_LBFIFO_5 0x00000100 // Five nibble FIFO
1603
#define EPHY_SCR_LBFIFO_6 0x00000200 // Six nibble FIFO
1604
#define EPHY_SCR_LBFIFO_8 0x00000300 // Eight nibble FIFO
1605
#define EPHY_SCR_COLFDM 0x00000010 // Collision in Full-Duplex Mode
1606
#define EPHY_SCR_TINT 0x00000004 // Test Interrupt
1607
#define EPHY_SCR_INTEN 0x00000002 // Interrupt Enable
1608
1609
//*****************************************************************************
1610
//
1611
// The following are defines for the bit fields in the EPHY_MISR1 register.
1612
//
1613
//*****************************************************************************
1614
#define EPHY_MISR1_LINKSTAT 0x00002000 // Change of Link Status Interrupt
1615
#define EPHY_MISR1_SPEED 0x00001000 // Change of Speed Status Interrupt
1616
#define EPHY_MISR1_DUPLEXM 0x00000800 // Change of Duplex Status
1617
// Interrupt
1618
#define EPHY_MISR1_ANC 0x00000400 // Auto-Negotiation Complete
1619
// Interrupt
1620
#define EPHY_MISR1_FCHF 0x00000200 // False Carrier Counter Half-Full
1621
// Interrupt
1622
#define EPHY_MISR1_RXHF 0x00000100 // Receive Error Counter Half-Full
1623
// Interrupt
1624
#define EPHY_MISR1_LINKSTATEN 0x00000020 // Link Status Interrupt Enable
1625
#define EPHY_MISR1_SPEEDEN 0x00000010 // Speed Change Interrupt Enable
1626
#define EPHY_MISR1_DUPLEXMEN 0x00000008 // Duplex Status Interrupt Enable
1627
#define EPHY_MISR1_ANCEN 0x00000004 // Auto-Negotiation Complete
1628
// Interrupt Enable
1629
#define EPHY_MISR1_FCHFEN 0x00000002 // False Carrier Counter Register
1630
// half-full Interrupt Enable
1631
#define EPHY_MISR1_RXHFEN 0x00000001 // Receive Error Counter Register
1632
// Half-Full Event Interrupt
1633
1634
//*****************************************************************************
1635
//
1636
// The following are defines for the bit fields in the EPHY_MISR2 register.
1637
//
1638
//*****************************************************************************
1639
#define EPHY_MISR2_ANERR 0x00004000 // Auto-Negotiation Error Interrupt
1640
#define EPHY_MISR2_PAGERX 0x00002000 // Page Receive Interrupt
1641
#define EPHY_MISR2_LBFIFO 0x00001000 // Loopback FIFO Overflow/Underflow
1642
// Event Interrupt
1643
#define EPHY_MISR2_MDICO 0x00000800 // MDI/MDIX Crossover Status
1644
// Changed Interrupt
1645
#define EPHY_MISR2_SLEEP 0x00000400 // Sleep Mode Event Interrupt
1646
#define EPHY_MISR2_POLINT 0x00000200 // Polarity Changed Interrupt
1647
#define EPHY_MISR2_JABBER 0x00000100 // Jabber Detect Event Interrupt
1648
#define EPHY_MISR2_ANERREN 0x00000040 // Auto-Negotiation Error Interrupt
1649
// Enable
1650
#define EPHY_MISR2_PAGERXEN 0x00000020 // Page Receive Interrupt Enable
1651
#define EPHY_MISR2_LBFIFOEN 0x00000010 // Loopback FIFO Overflow/Underflow
1652
// Interrupt Enable
1653
#define EPHY_MISR2_MDICOEN 0x00000008 // MDI/MDIX Crossover Status
1654
// Changed Interrupt Enable
1655
#define EPHY_MISR2_SLEEPEN 0x00000004 // Sleep Mode Event Interrupt
1656
// Enable
1657
#define EPHY_MISR2_POLINTEN 0x00000002 // Polarity Changed Interrupt
1658
// Enable
1659
#define EPHY_MISR2_JABBEREN 0x00000001 // Jabber Detect Event Interrupt
1660
// Enable
1661
1662
//*****************************************************************************
1663
//
1664
// The following are defines for the bit fields in the EPHY_FCSCR register.
1665
//
1666
//*****************************************************************************
1667
#define EPHY_FCSCR_FCSCNT_M 0x000000FF // False Carrier Event Counter
1668
#define EPHY_FCSCR_FCSCNT_S 0
1669
1670
//*****************************************************************************
1671
//
1672
// The following are defines for the bit fields in the EPHY_RXERCNT register.
1673
//
1674
//*****************************************************************************
1675
#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF // Receive Error Count
1676
#define EPHY_RXERCNT_RXERRCNT_S 0
1677
1678
//*****************************************************************************
1679
//
1680
// The following are defines for the bit fields in the EPHY_BISTCR register.
1681
//
1682
//*****************************************************************************
1683
#define EPHY_BISTCR_PRBSM 0x00004000 // PRBS Single/Continuous Mode
1684
#define EPHY_BISTCR_PRBSPKT 0x00002000 // Generated PRBS Packets
1685
#define EPHY_BISTCR_PKTEN 0x00001000 // Packet Generation Enable
1686
#define EPHY_BISTCR_PRBSCHKLK 0x00000800 // PRBS Checker Lock Indication
1687
#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400 // PRBS Checker Lock Sync Loss
1688
// Indication
1689
#define EPHY_BISTCR_PKTGENSTAT 0x00000200 // Packet Generator Status
1690
// Indication
1691
#define EPHY_BISTCR_PWRMODE 0x00000100 // Power Mode Indication
1692
#define EPHY_BISTCR_TXMIILB 0x00000040 // Transmit Data in MII Loopback
1693
// Mode
1694
#define EPHY_BISTCR_LBMODE_M 0x0000001F // Loopback Mode Select
1695
#define EPHY_BISTCR_LBMODE_NPCSIN \
1696
0x00000001 // Near-end loopback: PCS Input
1697
// Loopback
1698
#define EPHY_BISTCR_LBMODE_NPCSOUT \
1699
0x00000002 // Near-end loopback: PCS Output
1700
// Loopback (In 100Base-TX only)
1701
#define EPHY_BISTCR_LBMODE_NDIG 0x00000004 // Near-end loopback: Digital
1702
// Loopback
1703
#define EPHY_BISTCR_LBMODE_NANA 0x00000008 // Near-end loopback: Analog
1704
// Loopback (requires 100 Ohm
1705
// termination)
1706
#define EPHY_BISTCR_LBMODE_FREV 0x00000010 // Far-end Loopback: Reverse
1707
// Loopback
1708
1709
//*****************************************************************************
1710
//
1711
// The following are defines for the bit fields in the EPHY_LEDCR register.
1712
//
1713
//*****************************************************************************
1714
#define EPHY_LEDCR_BLINKRATE_M 0x00000600 // LED Blinking Rate (ON/OFF
1715
// duration):
1716
#define EPHY_LEDCR_BLINKRATE_20HZ \
1717
0x00000000 // 20 Hz (50 ms)
1718
#define EPHY_LEDCR_BLINKRATE_10HZ \
1719
0x00000200 // 10 Hz (100 ms)
1720
#define EPHY_LEDCR_BLINKRATE_5HZ \
1721
0x00000400 // 5 Hz (200 ms)
1722
#define EPHY_LEDCR_BLINKRATE_2HZ \
1723
0x00000600 // 2 Hz (500 ms)
1724
1725
//*****************************************************************************
1726
//
1727
// The following are defines for the bit fields in the EPHY_CTL register.
1728
//
1729
//*****************************************************************************
1730
#define EPHY_CTL_AUTOMDI 0x00008000 // Auto-MDIX Enable
1731
#define EPHY_CTL_FORCEMDI 0x00004000 // Force MDIX
1732
#define EPHY_CTL_PAUSERX 0x00002000 // Pause Receive Negotiated Status
1733
#define EPHY_CTL_PAUSETX 0x00001000 // Pause Transmit Negotiated Status
1734
#define EPHY_CTL_MIILNKSTAT 0x00000800 // MII Link Status
1735
#define EPHY_CTL_BYPLEDSTRCH 0x00000080 // Bypass LED Stretching
1736
1737
//*****************************************************************************
1738
//
1739
// The following are defines for the bit fields in the EPHY_10BTSC register.
1740
//
1741
//*****************************************************************************
1742
#define EPHY_10BTSC_RXTHEN 0x00002000 // Lower Receiver Threshold Enable
1743
#define EPHY_10BTSC_SQUELCH_M 0x00001E00 // Squelch Configuration
1744
#define EPHY_10BTSC_NLPDIS 0x00000080 // Normal Link Pulse (NLP)
1745
// Transmission Control
1746
#define EPHY_10BTSC_POLSTAT 0x00000010 // 10 Mb Polarity Status
1747
#define EPHY_10BTSC_JABBERD 0x00000001 // Jabber Disable
1748
#define EPHY_10BTSC_SQUELCH_S 9
1749
1750
//*****************************************************************************
1751
//
1752
// The following are defines for the bit fields in the EPHY_BICSR1 register.
1753
//
1754
//*****************************************************************************
1755
#define EPHY_BICSR1_ERRCNT_M 0x0000FF00 // BIST Error Count
1756
#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF // BIST IPG Length
1757
#define EPHY_BICSR1_ERRCNT_S 8
1758
#define EPHY_BICSR1_IPGLENGTH_S 0
1759
1760
//*****************************************************************************
1761
//
1762
// The following are defines for the bit fields in the EPHY_BICSR2 register.
1763
//
1764
//*****************************************************************************
1765
#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF // BIST Packet Length
1766
#define EPHY_BICSR2_PKTLENGTH_S 0
1767
1768
//*****************************************************************************
1769
//
1770
// The following are defines for the bit fields in the EPHY_CDCR register.
1771
//
1772
//*****************************************************************************
1773
#define EPHY_CDCR_START 0x00008000 // Cable Diagnostic Process Start
1774
#define EPHY_CDCR_LINKQUAL_M 0x00000300 // Link Quality Indication
1775
#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100 // Good Quality Link Indication
1776
#define EPHY_CDCR_LINKQUAL_MILD 0x00000200 // Mid- Quality Link Indication
1777
#define EPHY_CDCR_LINKQUAL_POOR 0x00000300 // Poor Quality Link Indication
1778
#define EPHY_CDCR_DONE 0x00000002 // Cable Diagnostic Process Done
1779
#define EPHY_CDCR_FAIL 0x00000001 // Cable Diagnostic Process Fail
1780
1781
//*****************************************************************************
1782
//
1783
// The following are defines for the bit fields in the EPHY_RCR register.
1784
//
1785
//*****************************************************************************
1786
#define EPHY_RCR_SWRST 0x00008000 // Software Reset
1787
#define EPHY_RCR_SWRESTART 0x00004000 // Software Restart
1788
1789
//*****************************************************************************
1790
//
1791
// The following are defines for the bit fields in the EPHY_LEDCFG register.
1792
//
1793
//*****************************************************************************
1794
#define EPHY_LEDCFG_LED2_M 0x00000F00 // LED2 Configuration
1795
#define EPHY_LEDCFG_LED2_LINK 0x00000000 // Link OK
1796
#define EPHY_LEDCFG_LED2_RXTX 0x00000100 // RX/TX Activity
1797
#define EPHY_LEDCFG_LED2_TX 0x00000200 // TX Activity
1798
#define EPHY_LEDCFG_LED2_RX 0x00000300 // RX Activity
1799
#define EPHY_LEDCFG_LED2_COL 0x00000400 // Collision
1800
#define EPHY_LEDCFG_LED2_100BT 0x00000500 // 100-Base TX
1801
#define EPHY_LEDCFG_LED2_10BT 0x00000600 // 10-Base TX
1802
#define EPHY_LEDCFG_LED2_FD 0x00000700 // Full Duplex
1803
#define EPHY_LEDCFG_LED2_LINKTXRX \
1804
0x00000800 // Link OK/Blink on TX/RX Activity
1805
#define EPHY_LEDCFG_LED1_M 0x000000F0 // LED1 Configuration
1806
#define EPHY_LEDCFG_LED1_LINK 0x00000000 // Link OK
1807
#define EPHY_LEDCFG_LED1_RXTX 0x00000010 // RX/TX Activity
1808
#define EPHY_LEDCFG_LED1_TX 0x00000020 // TX Activity
1809
#define EPHY_LEDCFG_LED1_RX 0x00000030 // RX Activity
1810
#define EPHY_LEDCFG_LED1_COL 0x00000040 // Collision
1811
#define EPHY_LEDCFG_LED1_100BT 0x00000050 // 100-Base TX
1812
#define EPHY_LEDCFG_LED1_10BT 0x00000060 // 10-Base TX
1813
#define EPHY_LEDCFG_LED1_FD 0x00000070 // Full Duplex
1814
#define EPHY_LEDCFG_LED1_LINKTXRX \
1815
0x00000080 // Link OK/Blink on TX/RX Activity
1816
#define EPHY_LEDCFG_LED0_M 0x0000000F // LED0 Configuration
1817
#define EPHY_LEDCFG_LED0_LINK 0x00000000 // Link OK
1818
#define EPHY_LEDCFG_LED0_RXTX 0x00000001 // RX/TX Activity
1819
#define EPHY_LEDCFG_LED0_TX 0x00000002 // TX Activity
1820
#define EPHY_LEDCFG_LED0_RX 0x00000003 // RX Activity
1821
#define EPHY_LEDCFG_LED0_COL 0x00000004 // Collision
1822
#define EPHY_LEDCFG_LED0_100BT 0x00000005 // 100-Base TX
1823
#define EPHY_LEDCFG_LED0_10BT 0x00000006 // 10-Base TX
1824
#define EPHY_LEDCFG_LED0_FD 0x00000007 // Full Duplex
1825
#define EPHY_LEDCFG_LED0_LINKTXRX \
1826
0x00000008 // Link OK/Blink on TX/RX Activity
1827
1828
//*****************************************************************************
1829
//
1830
// The following definitions are deprecated.
1831
//
1832
//*****************************************************************************
1833
#ifndef DEPRECATED
1834
1835
//*****************************************************************************
1836
//
1837
// The following are deprecated defines for the bit fields in the EMAC_O_CC
1838
// register.
1839
//
1840
//*****************************************************************************
1841
#define EMAC_CC_CS_PA7 0x00000001 // GPIO
1842
1843
#endif
1844
1845
#endif // __HW_EMAC_H__
inc
hw_emac.h
Generated on Fri Mar 13 2015 21:18:37 for EE445M RTOS by
1.8.9.1
1.8.9.1 
