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hw_sysctl.h
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//*****************************************************************************
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//
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// hw_sysctl.h - Macros used when accessing the system control hardware.
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//
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// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_SYSCTL_H__
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#define __HW_SYSCTL_H__
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//*****************************************************************************
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//
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// The following are defines for the System Control register addresses.
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//
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//*****************************************************************************
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#define SYSCTL_DID0 0x400FE000 // Device Identification 0
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#define SYSCTL_DID1 0x400FE004 // Device Identification 1
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#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0
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#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1
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#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2
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#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3
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#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4
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#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5
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#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6
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#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7
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#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8
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#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control
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#define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control
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#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0
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#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1
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#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2
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#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status
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#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control
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#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and
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// Clear
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#define SYSCTL_RESC 0x400FE05C // Reset Cause
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#define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause
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#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration
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#define SYSCTL_NMIC 0x400FE064 // NMI Cause Register
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#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus
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// Control
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#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2
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#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
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#define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration
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// Register
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#define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register
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// 0 for Main Flash and EEPROM
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#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control
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// Register 0
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#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control
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// Register 1
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#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control
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// Register 2
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#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control
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// Register 0
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#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control
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// Register 1
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#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control
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// Register 2
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#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating
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// Control Register 0
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#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating
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// Control Register 1
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#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating
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// Control Register 2
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#define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration
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#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
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#define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
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// Register
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#define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock
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// Configuration
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#define SYSCTL_SYSPROP 0x400FE14C // System Properties
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#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
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// Calibration
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#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
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// Statistics
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#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0
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#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1
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#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status
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#define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration
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#define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration
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#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9
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#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information
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#define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control
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#define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control
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#define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register
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#define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request
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#define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status
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#define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control
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#define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status
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#define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power
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// Control
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#define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control
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#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral
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// Present
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#define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer
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// Peripheral Present
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#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output
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// Peripheral Present
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#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access
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// Peripheral Present
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#define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present
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#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present
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#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous
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// Receiver/Transmitter Peripheral
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// Present
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#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface
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// Peripheral Present
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#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit
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// Peripheral Present
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#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral
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// Present
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#define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present
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#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network
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// Peripheral Present
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#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter
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// Peripheral Present
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#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral
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// Present
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#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral
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// Present
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#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface
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// Peripheral Present
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#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface
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// Peripheral Present
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#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control
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// Interface Peripheral Present
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#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present
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#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present
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#define SYSCTL_PPWTIMER 0x400FE35C // 32/64-Bit Wide General-Purpose
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// Timer Peripheral Present
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#define SYSCTL_PPRTS 0x400FE370 // Remote Temperature Sensor
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// Peripheral Present
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#define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules
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// Peripheral Present
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#define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present
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#define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present
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#define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present
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#define SYSCTL_PPHIM 0x400FE3A4 // Human Interface Master
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// Peripheral Present
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#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset
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#define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer
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// Software Reset
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#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output
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// Software Reset
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#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access
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// Software Reset
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#define SYSCTL_SREPI 0x400FE510 // EPI Software Reset
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#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset
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#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous
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// Receiver/Transmitter Software
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// Reset
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#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface
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// Software Reset
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#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit
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// Software Reset
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#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software
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// Reset
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#define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset
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#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software
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// Reset
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#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter
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// Software Reset
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#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset
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#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software
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// Reset
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#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface
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// Software Reset
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#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset
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#define SYSCTL_SRWTIMER 0x400FE55C // 32/64-Bit Wide General-Purpose
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// Timer Software Reset
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#define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules
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// Software Reset
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#define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset
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#define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset
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#define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset
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#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer
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// Run Mode Clock Gating Control
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#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous
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// Receiver/Transmitter Run Mode
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// Clock Gating Control
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#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode
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// Clock Gating Control
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#define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode
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// Clock Gating Control
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#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode
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// Clock Gating Control
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#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run
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// Mode Clock Gating Control
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#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCWTIMER 0x400FE65C // 32/64-Bit Wide General-Purpose
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// Timer Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules
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// Run Mode Clock Gating Control
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#define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock
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// Gating Control
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#define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating
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// Control
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#define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock
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// Gating Control
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#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock
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// Gating Control
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#define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep
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// Mode Clock Gating Control
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#define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating
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// Control
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#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock
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// Gating Control
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#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous
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// Receiver/Transmitter Sleep Mode
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// Clock Gating Control
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#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep
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// Mode Clock Gating Control
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#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode
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// Clock Gating Control
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#define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock
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// Gating Control
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#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep
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// Mode Clock Gating Control
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#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode
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// Clock Gating Control
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#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode
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// Clock Gating Control
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#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating
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// Control
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#define SYSCTL_SCGCWTIMER 0x400FE75C // 32/64-Bit Wide General-Purpose
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// Timer Sleep Mode Clock Gating
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// Control
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#define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules
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// Sleep Mode Clock Gating Control
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#define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock
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// Gating Control
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#define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating
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// Control
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#define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock
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// Gating Control
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#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode
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// Clock Gating Control
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#define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode
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// Clock Gating Control
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#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous
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// Receiver/Transmitter Deep-Sleep
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// Mode Clock Gating Control
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#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep
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// Mode Clock Gating Control
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#define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode
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// Clock Gating Control
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#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep
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// Mode Clock Gating Control
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#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep
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// Mode Clock Gating Control
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#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock
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// Gating Control
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#define SYSCTL_DCGCWTIMER 0x400FE85C // 32/64-Bit Wide General-Purpose
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// Timer Deep-Sleep Mode Clock
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// Gating Control
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#define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules
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// Deep-Sleep Mode Clock Gating
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// Control
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#define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode
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// Clock Gating Control
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#define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock
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// Gating Control
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#define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode
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// Clock Gating Control
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#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control
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#define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer
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// Power Control
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#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output
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// Power Control
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#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power
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// Control
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#define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface
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// Power Control
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#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control
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#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous
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// Receiver/Transmitter Power
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// Control
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#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface
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// Power Control
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#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power
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// Control
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#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power
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// Control
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#define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control
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#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power
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// Control
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#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter
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// Power Control
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#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control
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#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power
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// Control
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#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface
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// Power Control
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#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control
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#define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules
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// Power Control
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#define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control
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#define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control
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#define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control
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#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready
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#define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer
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// Peripheral Ready
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#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output
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// Peripheral Ready
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#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access
397
// Peripheral Ready
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#define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready
399
#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready
400
#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous
401
// Receiver/Transmitter Peripheral
402
// Ready
403
#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface
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// Peripheral Ready
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#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit
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// Peripheral Ready
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#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral
408
// Ready
409
#define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready
410
#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network
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// Peripheral Ready
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#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter
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// Peripheral Ready
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#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral
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// Ready
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#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral
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// Ready
418
#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface
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// Peripheral Ready
420
#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready
421
#define SYSCTL_PRWTIMER 0x400FEA5C // 32/64-Bit Wide General-Purpose
422
// Timer Peripheral Ready
423
#define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules
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// Peripheral Ready
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#define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready
426
#define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready
427
#define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready
428
#define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock
429
// Gating Request
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SYSCTL_DID0 register.
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//
435
//*****************************************************************************
436
#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
437
#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
438
// register format.
439
#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
440
#define SYSCTL_DID0_CLASS_TM4C123 \
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0x00050000 // Tiva TM4C123x and TM4E123x
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// microcontrollers
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#define SYSCTL_DID0_CLASS_TM4C129 \
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0x000A0000 // Tiva(TM) TM4C129-class
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// microcontrollers
446
#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
447
#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
448
#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
449
// revision)
450
#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
451
// revision)
452
#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
453
#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
454
// revision update
455
#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
456
#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
457
458
//*****************************************************************************
459
//
460
// The following are defines for the bit fields in the SYSCTL_DID1 register.
461
//
462
//*****************************************************************************
463
#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
464
#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib
465
#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
466
#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers
467
#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
468
#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \
469
0x00220000 // TM4C1230C3PM
470
#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \
471
0x00230000 // TM4C1230D5PM
472
#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \
473
0x00200000 // TM4C1230E6PM
474
#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \
475
0x00210000 // TM4C1230H6PM
476
#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \
477
0x00180000 // TM4C1231C3PM
478
#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \
479
0x00190000 // TM4C1231D5PM
480
#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \
481
0x00360000 // TM4C1231D5PZ
482
#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \
483
0x00100000 // TM4C1231E6PM
484
#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \
485
0x00300000 // TM4C1231E6PZ
486
#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \
487
0x00350000 // TM4C1231H6PGE
488
#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \
489
0x00110000 // TM4C1231H6PM
490
#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \
491
0x00310000 // TM4C1231H6PZ
492
#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \
493
0x00080000 // TM4C1232C3PM
494
#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \
495
0x00090000 // TM4C1232D5PM
496
#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \
497
0x000A0000 // TM4C1232E6PM
498
#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \
499
0x000B0000 // TM4C1232H6PM
500
#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \
501
0x00010000 // TM4C1233C3PM
502
#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \
503
0x00020000 // TM4C1233D5PM
504
#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \
505
0x00D00000 // TM4C1233D5PZ
506
#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \
507
0x00030000 // TM4C1233E6PM
508
#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \
509
0x00D10000 // TM4C1233E6PZ
510
#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \
511
0x00D60000 // TM4C1233H6PGE
512
#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \
513
0x00040000 // TM4C1233H6PM
514
#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \
515
0x00D20000 // TM4C1233H6PZ
516
#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \
517
0x00520000 // TM4C1236D5PM
518
#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \
519
0x00500000 // TM4C1236E6PM
520
#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \
521
0x00510000 // TM4C1236H6PM
522
#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \
523
0x00480000 // TM4C1237D5PM
524
#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \
525
0x00660000 // TM4C1237D5PZ
526
#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \
527
0x00400000 // TM4C1237E6PM
528
#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \
529
0x00600000 // TM4C1237E6PZ
530
#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \
531
0x00650000 // TM4C1237H6PGE
532
#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \
533
0x00410000 // TM4C1237H6PM
534
#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \
535
0x00610000 // TM4C1237H6PZ
536
#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \
537
0x00800000 // TM4C123AE6PM
538
#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \
539
0x00830000 // TM4C123AH6PM
540
#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \
541
0x00700000 // TM4C123BE6PM
542
#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \
543
0x00C30000 // TM4C123BE6PZ
544
#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \
545
0x00C60000 // TM4C123BH6PGE
546
#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \
547
0x00730000 // TM4C123BH6PM
548
#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \
549
0x00C40000 // TM4C123BH6PZ
550
#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \
551
0x00E90000 // TM4C123BH6ZRB
552
#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \
553
0x00B00000 // TM4C123FE6PM
554
#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \
555
0x00B10000 // TM4C123FH6PM
556
#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \
557
0x00A00000 // TM4C123GE6PM
558
#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \
559
0x00C00000 // TM4C123GE6PZ
560
#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \
561
0x00C50000 // TM4C123GH6PGE
562
#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \
563
0x00A10000 // TM4C123GH6PM
564
#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \
565
0x00C10000 // TM4C123GH6PZ
566
#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \
567
0x00E30000 // TM4C123GH6ZRB
568
#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT \
569
0x00190000 // TM4C1290NCPDT
570
#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD \
571
0x001B0000 // TM4C1290NCZAD
572
#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT \
573
0x001C0000 // TM4C1292NCPDT
574
#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD \
575
0x001E0000 // TM4C1292NCZAD
576
#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT \
577
0x00340000 // TM4C1294KCPDT
578
#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \
579
0x001F0000 // TM4C1294NCPDT
580
#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD \
581
0x00210000 // TM4C1294NCZAD
582
#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD \
583
0x00220000 // TM4C1297NCZAD
584
#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD \
585
0x00360000 // TM4C1299KCZAD
586
#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD \
587
0x00230000 // TM4C1299NCZAD
588
#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT \
589
0x00240000 // TM4C129CNCPDT
590
#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD \
591
0x00260000 // TM4C129CNCZAD
592
#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT \
593
0x00270000 // TM4C129DNCPDT
594
#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD \
595
0x00290000 // TM4C129DNCZAD
596
#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT \
597
0x00350000 // TM4C129EKCPDT
598
#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT \
599
0x002D0000 // TM4C129ENCPDT
600
#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD \
601
0x002F0000 // TM4C129ENCZAD
602
#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD \
603
0x00300000 // TM4C129LNCZAD
604
#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD \
605
0x00370000 // TM4C129XKCZAD
606
#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD \
607
0x00320000 // TM4C129XNCZAD
608
#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
609
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package
610
#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package
611
#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package
612
#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package
613
#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package
614
#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
615
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range
616
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
617
#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range
618
#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial
619
// temperature range (-40C to 85C)
620
// and extended temperature range
621
// (-40C to 105C) devices. See
622
#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
623
#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package
624
#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
625
#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
626
#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
627
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
628
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
629
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
630
631
//*****************************************************************************
632
//
633
// The following are defines for the bit fields in the SYSCTL_DC0 register.
634
//
635
//*****************************************************************************
636
#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
637
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
638
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
639
#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
640
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
641
#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
642
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
643
#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
644
#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
645
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
646
#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
647
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
648
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
649
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
650
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
651
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
652
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
653
#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
654
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
655
656
//*****************************************************************************
657
//
658
// The following are defines for the bit fields in the SYSCTL_DC1 register.
659
//
660
//*****************************************************************************
661
#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
662
#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
663
#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
664
#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
665
#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
666
#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
667
#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
668
#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
669
#define SYSCTL_DC1_MINSYSDIV_80 0x00001000 // Specifies an 80-MHz CPU clock
670
// with a PLL divider of 2.5
671
#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Specifies a 66-MHz CPU clock
672
// with a PLL divider of 3
673
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
674
// with a PLL divider of 4
675
#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
676
// with a PLL divider of 5
677
#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
678
// PLL divider of 8
679
#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
680
// PLL divider of 10
681
#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
682
#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
683
#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
684
#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
685
#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
686
#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
687
#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
688
#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
689
#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
690
#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
691
#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
692
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
693
#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
694
#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
695
#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
696
#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
697
#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
698
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
699
700
//*****************************************************************************
701
//
702
// The following are defines for the bit fields in the SYSCTL_DC2 register.
703
//
704
//*****************************************************************************
705
#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
706
#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
707
#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
708
#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
709
#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
710
#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
711
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
712
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
713
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
714
#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
715
#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
716
#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
717
#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
718
#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
719
#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
720
#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
721
#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
722
#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
723
#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
724
#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
725
726
//*****************************************************************************
727
//
728
// The following are defines for the bit fields in the SYSCTL_DC3 register.
729
//
730
//*****************************************************************************
731
#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
732
#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present
733
#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present
734
#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present
735
#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present
736
#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present
737
#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present
738
#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
739
#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
740
#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
741
#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
742
#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
743
#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
744
#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
745
#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
746
#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
747
#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
748
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
749
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
750
#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
751
#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
752
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
753
#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
754
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
755
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
756
#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
757
#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
758
#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
759
#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
760
#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
761
#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
762
763
//*****************************************************************************
764
//
765
// The following are defines for the bit fields in the SYSCTL_DC4 register.
766
//
767
//*****************************************************************************
768
#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
769
#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
770
#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
771
#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
772
#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present
773
#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present
774
#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
775
#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
776
#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
777
#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
778
#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
779
#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
780
#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
781
#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
782
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
783
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
784
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
785
786
//*****************************************************************************
787
//
788
// The following are defines for the bit fields in the SYSCTL_DC5 register.
789
//
790
//*****************************************************************************
791
#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
792
#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
793
#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
794
#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
795
#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
796
#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
797
#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
798
#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
799
#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
800
#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
801
#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
802
#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
803
#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
804
#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
805
806
//*****************************************************************************
807
//
808
// The following are defines for the bit fields in the SYSCTL_DC6 register.
809
//
810
//*****************************************************************************
811
#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
812
#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
813
#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
814
#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
815
#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
816
817
//*****************************************************************************
818
//
819
// The following are defines for the bit fields in the SYSCTL_DC7 register.
820
//
821
//*****************************************************************************
822
#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30
823
#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29
824
#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28
825
#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27
826
#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26
827
#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25
828
#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24
829
#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23
830
#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22
831
#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21
832
#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20
833
#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19
834
#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18
835
#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17
836
#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16
837
#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15
838
#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14
839
#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13
840
#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12
841
#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11
842
#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10
843
#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9
844
#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8
845
#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7
846
#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6
847
#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5
848
#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4
849
#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3
850
#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2
851
#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1
852
#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0
853
854
//*****************************************************************************
855
//
856
// The following are defines for the bit fields in the SYSCTL_DC8 register.
857
//
858
//*****************************************************************************
859
#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
860
#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
861
#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
862
#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
863
#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
864
#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
865
#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
866
#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
867
#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
868
#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
869
#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
870
#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
871
#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
872
#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
873
#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
874
#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
875
#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
876
#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
877
#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
878
#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
879
#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
880
#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
881
#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
882
#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
883
#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
884
#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
885
#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
886
#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
887
#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
888
#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
889
#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
890
#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
891
892
//*****************************************************************************
893
//
894
// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
895
//
896
//*****************************************************************************
897
#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action
898
#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action
899
900
//*****************************************************************************
901
//
902
// The following are defines for the bit fields in the SYSCTL_PTBOCTL register.
903
//
904
//*****************************************************************************
905
#define SYSCTL_PTBOCTL_VDDA_UBOR_M \
906
0x00000300 // VDDA under BOR Event Action
907
#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \
908
0x00000000 // No Action
909
#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \
910
0x00000100 // System control interrupt
911
#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \
912
0x00000200 // NMI
913
#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \
914
0x00000300 // Reset
915
#define SYSCTL_PTBOCTL_VDD_UBOR_M \
916
0x00000003 // VDD (VDDS) under BOR Event
917
// Action
918
#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \
919
0x00000000 // No Action
920
#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \
921
0x00000001 // System control interrupt
922
#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \
923
0x00000002 // NMI
924
#define SYSCTL_PTBOCTL_VDD_UBOR_RST \
925
0x00000003 // Reset
926
927
//*****************************************************************************
928
//
929
// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
930
//
931
//*****************************************************************************
932
#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
933
#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
934
#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
935
#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
936
#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
937
#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
938
#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
939
#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
940
941
//*****************************************************************************
942
//
943
// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
944
//
945
//*****************************************************************************
946
#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
947
#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
948
#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
949
#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
950
#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
951
#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
952
#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
953
#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
954
#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
955
#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
956
#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
957
#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
958
#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
959
#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
960
#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
961
#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
962
963
//*****************************************************************************
964
//
965
// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
966
//
967
//*****************************************************************************
968
#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
969
#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
970
#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
971
#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
972
#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
973
#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
974
#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
975
#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
976
#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
977
#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
978
#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
979
980
//*****************************************************************************
981
//
982
// The following are defines for the bit fields in the SYSCTL_RIS register.
983
//
984
//*****************************************************************************
985
#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt
986
// Status
987
#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw
988
// Interrupt Status
989
#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
990
// Status
991
#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
992
// Status
993
#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
994
#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw
995
// Interrupt Status
996
#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt
997
// Status
998
#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
999
// Status
1000
1001
//*****************************************************************************
1002
//
1003
// The following are defines for the bit fields in the SYSCTL_IMC register.
1004
//
1005
//*****************************************************************************
1006
#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask
1007
#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask
1008
#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
1009
#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
1010
#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
1011
#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure
1012
// Interrupt Mask
1013
#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
1014
#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask
1015
1016
//*****************************************************************************
1017
//
1018
// The following are defines for the bit fields in the SYSCTL_MISC register.
1019
//
1020
//*****************************************************************************
1021
#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt
1022
// Status
1023
#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt
1024
// Status
1025
#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
1026
// Status
1027
#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
1028
// Status
1029
#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
1030
#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked
1031
// Interrupt Status
1032
#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
1033
#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt
1034
// Status
1035
1036
//*****************************************************************************
1037
//
1038
// The following are defines for the bit fields in the SYSCTL_RESC register.
1039
//
1040
//*****************************************************************************
1041
#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
1042
#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset
1043
#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset
1044
#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
1045
#define SYSCTL_RESC_SW 0x00000010 // Software Reset
1046
#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
1047
#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
1048
#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
1049
#define SYSCTL_RESC_EXT 0x00000001 // External Reset
1050
1051
//*****************************************************************************
1052
//
1053
// The following are defines for the bit fields in the SYSCTL_PWRTC register.
1054
//
1055
//*****************************************************************************
1056
#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status
1057
#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status
1058
1059
//*****************************************************************************
1060
//
1061
// The following are defines for the bit fields in the SYSCTL_RCC register.
1062
//
1063
//*****************************************************************************
1064
#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
1065
#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
1066
#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
1067
#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor
1068
#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor
1069
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
1070
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
1071
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
1072
#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
1073
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
1074
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
1075
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
1076
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
1077
#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
1078
#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
1079
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
1080
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
1081
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
1082
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
1083
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
1084
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
1085
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
1086
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
1087
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
1088
#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
1089
#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
1090
#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
1091
#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
1092
#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
1093
#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
1094
#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
1095
#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB)
1096
#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB)
1097
#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB)
1098
#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB)
1099
#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
1100
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
1101
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
1102
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
1103
#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC
1104
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
1105
#define SYSCTL_RCC_SYSDIV_S 23
1106
#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
1107
1108
//*****************************************************************************
1109
//
1110
// The following are defines for the bit fields in the SYSCTL_NMIC register.
1111
//
1112
//*****************************************************************************
1113
#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI
1114
#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI
1115
#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI
1116
#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI
1117
#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI
1118
#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI
1119
1120
//*****************************************************************************
1121
//
1122
// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
1123
// register.
1124
//
1125
//*****************************************************************************
1126
#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance
1127
// Bus
1128
#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance
1129
// Bus
1130
#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance
1131
// Bus
1132
#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
1133
// Bus
1134
#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
1135
// Bus
1136
#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
1137
// Bus
1138
#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
1139
// Bus
1140
#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
1141
// Bus
1142
#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
1143
// Bus
1144
1145
//*****************************************************************************
1146
//
1147
// The following are defines for the bit fields in the SYSCTL_RCC2 register.
1148
//
1149
//*****************************************************************************
1150
#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
1151
#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
1152
// MHz
1153
#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
1154
#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
1155
#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
1156
#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
1157
#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
1158
#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
1159
#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
1160
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
1161
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
1162
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC
1163
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
1164
#define SYSCTL_RCC2_SYSDIV2_S 23
1165
1166
//*****************************************************************************
1167
//
1168
// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
1169
//
1170
//*****************************************************************************
1171
#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range
1172
#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down
1173
#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
1174
#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
1175
#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
1176
1177
//*****************************************************************************
1178
//
1179
// The following are defines for the bit fields in the SYSCTL_RSCLKCFG
1180
// register.
1181
//
1182
//*****************************************************************************
1183
#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update
1184
#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept
1185
#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating
1186
#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL
1187
#define SYSCTL_RSCLKCFG_PLLSRC_M \
1188
0x0F000000 // PLL Source
1189
#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \
1190
0x00000000 // PIOSC is PLL input clock source
1191
#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \
1192
0x03000000 // MOSC is the PLL input clock
1193
// source
1194
#define SYSCTL_RSCLKCFG_OSCSRC_M \
1195
0x00F00000 // Oscillator Source
1196
#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \
1197
0x00000000 // PIOSC is oscillator source
1198
#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \
1199
0x00200000 // LFIOSC is oscillator source
1200
#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \
1201
0x00300000 // MOSC is oscillator source
1202
#define SYSCTL_RSCLKCFG_OSCSRC_RTC \
1203
0x00400000 // Hibernation Module RTC
1204
// Oscillator (RTCOSC)
1205
#define SYSCTL_RSCLKCFG_OSYSDIV_M \
1206
0x000FFC00 // Oscillator System Clock Divisor
1207
#define SYSCTL_RSCLKCFG_PSYSDIV_M \
1208
0x000003FF // PLL System Clock Divisor
1209
#define SYSCTL_RSCLKCFG_OSYSDIV_S \
1210
10
1211
#define SYSCTL_RSCLKCFG_PSYSDIV_S \
1212
0
1213
1214
//*****************************************************************************
1215
//
1216
// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register.
1217
//
1218
//*****************************************************************************
1219
#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time
1220
#define SYSCTL_MEMTIM0_EBCHT_0_5 \
1221
0x00000000 // 1/2 system clock period
1222
#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period
1223
#define SYSCTL_MEMTIM0_EBCHT_1_5 \
1224
0x00800000 // 1.5 system clock periods
1225
#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods
1226
#define SYSCTL_MEMTIM0_EBCHT_2_5 \
1227
0x01000000 // 2.5 system clock periods
1228
#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods
1229
#define SYSCTL_MEMTIM0_EBCHT_3_5 \
1230
0x01800000 // 3.5 system clock periods
1231
#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods
1232
#define SYSCTL_MEMTIM0_EBCHT_4_5 \
1233
0x02000000 // 4.5 system clock periods
1234
#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge
1235
#define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one
1236
#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States
1237
#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time
1238
#define SYSCTL_MEMTIM0_FBCHT_0_5 \
1239
0x00000000 // 1/2 system clock period
1240
#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period
1241
#define SYSCTL_MEMTIM0_FBCHT_1_5 \
1242
0x00000080 // 1.5 system clock periods
1243
#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods
1244
#define SYSCTL_MEMTIM0_FBCHT_2_5 \
1245
0x00000100 // 2.5 system clock periods
1246
#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods
1247
#define SYSCTL_MEMTIM0_FBCHT_3_5 \
1248
0x00000180 // 3.5 system clock periods
1249
#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods
1250
#define SYSCTL_MEMTIM0_FBCHT_4_5 \
1251
0x00000200 // 4.5 system clock periods
1252
#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge
1253
#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State
1254
#define SYSCTL_MEMTIM0_EWS_S 16
1255
#define SYSCTL_MEMTIM0_FWS_S 0
1256
1257
//*****************************************************************************
1258
//
1259
// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
1260
//
1261
//*****************************************************************************
1262
#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
1263
#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
1264
#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
1265
#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
1266
#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
1267
#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
1268
#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
1269
#define SYSCTL_RCGC0_ADC1SPD_125K \
1270
0x00000000 // 125K samples/second
1271
#define SYSCTL_RCGC0_ADC1SPD_250K \
1272
0x00000400 // 250K samples/second
1273
#define SYSCTL_RCGC0_ADC1SPD_500K \
1274
0x00000800 // 500K samples/second
1275
#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
1276
#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
1277
#define SYSCTL_RCGC0_ADC0SPD_125K \
1278
0x00000000 // 125K samples/second
1279
#define SYSCTL_RCGC0_ADC0SPD_250K \
1280
0x00000100 // 250K samples/second
1281
#define SYSCTL_RCGC0_ADC0SPD_500K \
1282
0x00000200 // 500K samples/second
1283
#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
1284
#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
1285
#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
1286
1287
//*****************************************************************************
1288
//
1289
// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
1290
//
1291
//*****************************************************************************
1292
#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
1293
#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
1294
#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
1295
#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
1296
#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
1297
#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
1298
#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
1299
#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
1300
#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
1301
#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
1302
#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
1303
#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
1304
#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
1305
#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
1306
#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
1307
#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
1308
1309
//*****************************************************************************
1310
//
1311
// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
1312
//
1313
//*****************************************************************************
1314
#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
1315
#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
1316
#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
1317
#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
1318
#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
1319
#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
1320
#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
1321
#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
1322
#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
1323
#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
1324
#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
1325
1326
//*****************************************************************************
1327
//
1328
// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
1329
//
1330
//*****************************************************************************
1331
#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
1332
#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
1333
#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
1334
#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
1335
#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
1336
#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
1337
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
1338
#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
1339
#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
1340
1341
//*****************************************************************************
1342
//
1343
// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
1344
//
1345
//*****************************************************************************
1346
#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
1347
#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
1348
#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
1349
#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
1350
#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
1351
#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
1352
#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
1353
#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
1354
#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
1355
#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
1356
#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
1357
#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
1358
#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
1359
#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
1360
#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
1361
#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
1362
1363
//*****************************************************************************
1364
//
1365
// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
1366
//
1367
//*****************************************************************************
1368
#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
1369
#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
1370
#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
1371
#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
1372
#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
1373
#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
1374
#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
1375
#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
1376
#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
1377
#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
1378
#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
1379
1380
//*****************************************************************************
1381
//
1382
// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
1383
//
1384
//*****************************************************************************
1385
#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
1386
#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
1387
#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
1388
#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
1389
#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
1390
#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
1391
#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
1392
#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
1393
1394
//*****************************************************************************
1395
//
1396
// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
1397
//
1398
//*****************************************************************************
1399
#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
1400
#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
1401
#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
1402
#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
1403
#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
1404
#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
1405
#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
1406
#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
1407
#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
1408
#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
1409
#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
1410
#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
1411
#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
1412
#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
1413
#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
1414
#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
1415
1416
//*****************************************************************************
1417
//
1418
// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
1419
//
1420
//*****************************************************************************
1421
#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
1422
#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
1423
#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
1424
#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
1425
#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
1426
#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
1427
#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
1428
#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
1429
#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
1430
#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
1431
#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
1432
1433
//*****************************************************************************
1434
//
1435
// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG
1436
// register.
1437
//
1438
//*****************************************************************************
1439
#define SYSCTL_ALTCLKCFG_ALTCLK_M \
1440
0x0000000F // Alternate Clock Source
1441
#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \
1442
0x00000000 // PIOSC
1443
#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \
1444
0x00000003 // Hibernation Module Real-time
1445
// clock output (RTCOSC)
1446
#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \
1447
0x00000004 // Low-frequency internal
1448
// oscillator (LFIOSC)
1449
1450
//*****************************************************************************
1451
//
1452
// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
1453
// register.
1454
//
1455
//*****************************************************************************
1456
#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
1457
#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
1458
#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
1459
#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
1460
#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC
1461
#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
1462
#define SYSCTL_DSLPCLKCFG_PIOSCPD \
1463
0x00000002 // PIOSC Power Down Request
1464
#define SYSCTL_DSLPCLKCFG_D_S 23
1465
1466
//*****************************************************************************
1467
//
1468
// The following are defines for the bit fields in the SYSCTL_DSCLKCFG
1469
// register.
1470
//
1471
//*****************************************************************************
1472
#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down
1473
#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down
1474
#define SYSCTL_DSCLKCFG_DSOSCSRC_M \
1475
0x00F00000 // Deep Sleep Oscillator Source
1476
#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \
1477
0x00000000 // PIOSC
1478
#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \
1479
0x00200000 // LFIOSC
1480
#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \
1481
0x00300000 // MOSC
1482
#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \
1483
0x00400000 // Hibernation Module RTCOSC
1484
#define SYSCTL_DSCLKCFG_DSSYSDIV_M \
1485
0x000003FF // Deep Sleep Clock Divisor
1486
#define SYSCTL_DSCLKCFG_DSSYSDIV_S \
1487
0
1488
1489
//*****************************************************************************
1490
//
1491
// The following are defines for the bit fields in the SYSCTL_DIVSCLK register.
1492
//
1493
//*****************************************************************************
1494
#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable
1495
#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source
1496
#define SYSCTL_DIVSCLK_SRC_SYSCLK \
1497
0x00000000 // System Clock
1498
#define SYSCTL_DIVSCLK_SRC_PIOSC \
1499
0x00010000 // PIOSC
1500
#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC
1501
#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value
1502
#define SYSCTL_DIVSCLK_DIV_S 0
1503
1504
//*****************************************************************************
1505
//
1506
// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
1507
//
1508
//*****************************************************************************
1509
#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
1510
1511
//*****************************************************************************
1512
//
1513
// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
1514
// register.
1515
//
1516
//*****************************************************************************
1517
#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
1518
#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
1519
#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
1520
#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
1521
#define SYSCTL_PIOSCCAL_UT_S 0
1522
1523
//*****************************************************************************
1524
//
1525
// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
1526
// register.
1527
//
1528
//*****************************************************************************
1529
#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
1530
#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
1531
#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
1532
// attempted
1533
#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
1534
// completed to meet 1% accuracy
1535
#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
1536
// failed to meet 1% accuracy
1537
#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
1538
#define SYSCTL_PIOSCSTAT_DT_S 16
1539
#define SYSCTL_PIOSCSTAT_CT_S 0
1540
1541
//*****************************************************************************
1542
//
1543
// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
1544
// register.
1545
//
1546
//*****************************************************************************
1547
#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power
1548
#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
1549
#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
1550
#define SYSCTL_PLLFREQ0_MFRAC_S 10
1551
#define SYSCTL_PLLFREQ0_MINT_S 0
1552
1553
//*****************************************************************************
1554
//
1555
// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
1556
// register.
1557
//
1558
//*****************************************************************************
1559
#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
1560
#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
1561
#define SYSCTL_PLLFREQ1_Q_S 8
1562
#define SYSCTL_PLLFREQ1_N_S 0
1563
1564
//*****************************************************************************
1565
//
1566
// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
1567
//
1568
//*****************************************************************************
1569
#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
1570
1571
//*****************************************************************************
1572
//
1573
// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
1574
// register.
1575
//
1576
//*****************************************************************************
1577
#define SYSCTL_SLPPWRCFG_FLASHPM_M \
1578
0x00000030 // Flash Power Modes
1579
#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \
1580
0x00000000 // Active Mode
1581
#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \
1582
0x00000020 // Low Power Mode
1583
#define SYSCTL_SLPPWRCFG_SRAMPM_M \
1584
0x00000003 // SRAM Power Modes
1585
#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \
1586
0x00000000 // Active Mode
1587
#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \
1588
0x00000001 // Standby Mode
1589
#define SYSCTL_SLPPWRCFG_SRAMPM_LP \
1590
0x00000003 // Low Power Mode
1591
1592
//*****************************************************************************
1593
//
1594
// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
1595
// register.
1596
//
1597
//*****************************************************************************
1598
#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode
1599
#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down
1600
#define SYSCTL_DSLPPWRCFG_FLASHPM_M \
1601
0x00000030 // Flash Power Modes
1602
#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \
1603
0x00000000 // Active Mode
1604
#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \
1605
0x00000020 // Low Power Mode
1606
#define SYSCTL_DSLPPWRCFG_SRAMPM_M \
1607
0x00000003 // SRAM Power Modes
1608
#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \
1609
0x00000000 // Active Mode
1610
#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \
1611
0x00000001 // Standby Mode
1612
#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \
1613
0x00000003 // Low Power Mode
1614
1615
//*****************************************************************************
1616
//
1617
// The following are defines for the bit fields in the SYSCTL_DC9 register.
1618
//
1619
//*****************************************************************************
1620
#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
1621
#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
1622
#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
1623
#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
1624
#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
1625
#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
1626
#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
1627
#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
1628
#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
1629
#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
1630
#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
1631
#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
1632
#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
1633
#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
1634
#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
1635
#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
1636
1637
//*****************************************************************************
1638
//
1639
// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
1640
//
1641
//*****************************************************************************
1642
#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
1643
// Available
1644
1645
//*****************************************************************************
1646
//
1647
// The following are defines for the bit fields in the SYSCTL_LDOSPCTL
1648
// register.
1649
//
1650
//*****************************************************************************
1651
#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable
1652
#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage
1653
#define SYSCTL_LDOSPCTL_VLDO_0_90V \
1654
0x00000012 // 0.90 V
1655
#define SYSCTL_LDOSPCTL_VLDO_0_95V \
1656
0x00000013 // 0.95 V
1657
#define SYSCTL_LDOSPCTL_VLDO_1_00V \
1658
0x00000014 // 1.00 V
1659
#define SYSCTL_LDOSPCTL_VLDO_1_05V \
1660
0x00000015 // 1.05 V
1661
#define SYSCTL_LDOSPCTL_VLDO_1_10V \
1662
0x00000016 // 1.10 V
1663
#define SYSCTL_LDOSPCTL_VLDO_1_15V \
1664
0x00000017 // 1.15 V
1665
#define SYSCTL_LDOSPCTL_VLDO_1_20V \
1666
0x00000018 // 1.20 V
1667
1668
//*****************************************************************************
1669
//
1670
// The following are defines for the bit fields in the SYSCTL_LDODPCTL
1671
// register.
1672
//
1673
//*****************************************************************************
1674
#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable
1675
#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage
1676
#define SYSCTL_LDODPCTL_VLDO_0_90V \
1677
0x00000012 // 0.90 V
1678
#define SYSCTL_LDODPCTL_VLDO_0_95V \
1679
0x00000013 // 0.95 V
1680
#define SYSCTL_LDODPCTL_VLDO_1_00V \
1681
0x00000014 // 1.00 V
1682
#define SYSCTL_LDODPCTL_VLDO_1_05V \
1683
0x00000015 // 1.05 V
1684
#define SYSCTL_LDODPCTL_VLDO_1_10V \
1685
0x00000016 // 1.10 V
1686
#define SYSCTL_LDODPCTL_VLDO_1_15V \
1687
0x00000017 // 1.15 V
1688
#define SYSCTL_LDODPCTL_VLDO_1_20V \
1689
0x00000018 // 1.20 V
1690
#define SYSCTL_LDODPCTL_VLDO_1_25V \
1691
0x00000019 // 1.25 V
1692
#define SYSCTL_LDODPCTL_VLDO_1_30V \
1693
0x0000001A // 1.30 V
1694
#define SYSCTL_LDODPCTL_VLDO_1_35V \
1695
0x0000001B // 1.35 V
1696
1697
//*****************************************************************************
1698
//
1699
// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL
1700
// register.
1701
//
1702
//*****************************************************************************
1703
#define SYSCTL_RESBEHAVCTL_WDOG1_M \
1704
0x000000C0 // Watchdog 1 Reset Operation
1705
#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \
1706
0x00000080 // Watchdog 1 issues a system
1707
// reset. The application starts
1708
// within 10 us
1709
#define SYSCTL_RESBEHAVCTL_WDOG1_POR \
1710
0x000000C0 // Watchdog 1 issues a simulated
1711
// POR sequence. Application starts
1712
// less than 500 us after
1713
// deassertion (Default)
1714
#define SYSCTL_RESBEHAVCTL_WDOG0_M \
1715
0x00000030 // Watchdog 0 Reset Operation
1716
#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \
1717
0x00000020 // Watchdog 0 issues a system
1718
// reset. The application starts
1719
// within 10 us
1720
#define SYSCTL_RESBEHAVCTL_WDOG0_POR \
1721
0x00000030 // Watchdog 0 issues a simulated
1722
// POR sequence. Application starts
1723
// less than 500 us after
1724
// deassertion (Default)
1725
#define SYSCTL_RESBEHAVCTL_BOR_M \
1726
0x0000000C // BOR Reset operation
1727
#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \
1728
0x00000008 // Brown Out Reset issues system
1729
// reset. The application starts
1730
// within 10 us
1731
#define SYSCTL_RESBEHAVCTL_BOR_POR \
1732
0x0000000C // Brown Out Reset issues a
1733
// simulated POR sequence. The
1734
// application starts less than 500
1735
// us after deassertion (Default)
1736
#define SYSCTL_RESBEHAVCTL_EXTRES_M \
1737
0x00000003 // External RST Pin Operation
1738
#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \
1739
0x00000002 // External RST assertion issues a
1740
// system reset. The application
1741
// starts within 10 us
1742
#define SYSCTL_RESBEHAVCTL_EXTRES_POR \
1743
0x00000003 // External RST assertion issues a
1744
// simulated POR sequence.
1745
// Application starts less than 500
1746
// us after deassertion (Default)
1747
1748
//*****************************************************************************
1749
//
1750
// The following are defines for the bit fields in the SYSCTL_HSSR register.
1751
//
1752
//*****************************************************************************
1753
#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key
1754
#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer
1755
#define SYSCTL_HSSR_KEY_S 24
1756
#define SYSCTL_HSSR_CDOFF_S 0
1757
1758
//*****************************************************************************
1759
//
1760
// The following are defines for the bit fields in the SYSCTL_USBPDS register.
1761
//
1762
//*****************************************************************************
1763
#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status
1764
#define SYSCTL_USBPDS_MEMSTAT_OFF \
1765
0x00000000 // Array OFF
1766
#define SYSCTL_USBPDS_MEMSTAT_RETAIN \
1767
0x00000004 // SRAM Retention
1768
#define SYSCTL_USBPDS_MEMSTAT_ON \
1769
0x0000000C // Array On
1770
#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status
1771
#define SYSCTL_USBPDS_PWRSTAT_OFF \
1772
0x00000000 // OFF
1773
#define SYSCTL_USBPDS_PWRSTAT_ON \
1774
0x00000003 // ON
1775
1776
//*****************************************************************************
1777
//
1778
// The following are defines for the bit fields in the SYSCTL_USBMPC register.
1779
//
1780
//*****************************************************************************
1781
#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
1782
#define SYSCTL_USBMPC_PWRCTL_OFF \
1783
0x00000000 // Array OFF
1784
#define SYSCTL_USBMPC_PWRCTL_RETAIN \
1785
0x00000001 // SRAM Retention
1786
#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On
1787
1788
//*****************************************************************************
1789
//
1790
// The following are defines for the bit fields in the SYSCTL_EMACPDS register.
1791
//
1792
//*****************************************************************************
1793
#define SYSCTL_EMACPDS_MEMSTAT_M \
1794
0x0000000C // Memory Array Power Status
1795
#define SYSCTL_EMACPDS_MEMSTAT_OFF \
1796
0x00000000 // Array OFF
1797
#define SYSCTL_EMACPDS_MEMSTAT_ON \
1798
0x0000000C // Array On
1799
#define SYSCTL_EMACPDS_PWRSTAT_M \
1800
0x00000003 // Power Domain Status
1801
#define SYSCTL_EMACPDS_PWRSTAT_OFF \
1802
0x00000000 // OFF
1803
#define SYSCTL_EMACPDS_PWRSTAT_ON \
1804
0x00000003 // ON
1805
1806
//*****************************************************************************
1807
//
1808
// The following are defines for the bit fields in the SYSCTL_EMACMPC register.
1809
//
1810
//*****************************************************************************
1811
#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
1812
#define SYSCTL_EMACMPC_PWRCTL_OFF \
1813
0x00000000 // Array OFF
1814
#define SYSCTL_EMACMPC_PWRCTL_ON \
1815
0x00000003 // Array On
1816
1817
//*****************************************************************************
1818
//
1819
// The following are defines for the bit fields in the SYSCTL_LCDMPC register.
1820
//
1821
//*****************************************************************************
1822
#define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
1823
#define SYSCTL_LCDMPC_PWRCTL_OFF \
1824
0x00000000 // Array OFF
1825
#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On
1826
1827
//*****************************************************************************
1828
//
1829
// The following are defines for the bit fields in the SYSCTL_PPWD register.
1830
//
1831
//*****************************************************************************
1832
#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
1833
#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
1834
1835
//*****************************************************************************
1836
//
1837
// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
1838
//
1839
//*****************************************************************************
1840
#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer
1841
// 7 Present
1842
#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer
1843
// 6 Present
1844
#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer
1845
// 5 Present
1846
#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer
1847
// 4 Present
1848
#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer
1849
// 3 Present
1850
#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer
1851
// 2 Present
1852
#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer
1853
// 1 Present
1854
#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer
1855
// 0 Present
1856
1857
//*****************************************************************************
1858
//
1859
// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
1860
//
1861
//*****************************************************************************
1862
#define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present
1863
#define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present
1864
#define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present
1865
#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
1866
#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
1867
#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
1868
#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
1869
#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
1870
#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
1871
#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
1872
#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
1873
#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
1874
#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
1875
#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
1876
#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
1877
#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
1878
#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
1879
#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
1880
1881
//*****************************************************************************
1882
//
1883
// The following are defines for the bit fields in the SYSCTL_PPDMA register.
1884
//
1885
//*****************************************************************************
1886
#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
1887
1888
//*****************************************************************************
1889
//
1890
// The following are defines for the bit fields in the SYSCTL_PPEPI register.
1891
//
1892
//*****************************************************************************
1893
#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present
1894
1895
//*****************************************************************************
1896
//
1897
// The following are defines for the bit fields in the SYSCTL_PPHIB register.
1898
//
1899
//*****************************************************************************
1900
#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
1901
1902
//*****************************************************************************
1903
//
1904
// The following are defines for the bit fields in the SYSCTL_PPUART register.
1905
//
1906
//*****************************************************************************
1907
#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
1908
#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
1909
#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
1910
#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
1911
#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
1912
#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
1913
#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
1914
#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
1915
1916
//*****************************************************************************
1917
//
1918
// The following are defines for the bit fields in the SYSCTL_PPSSI register.
1919
//
1920
//*****************************************************************************
1921
#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
1922
#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
1923
#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
1924
#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
1925
1926
//*****************************************************************************
1927
//
1928
// The following are defines for the bit fields in the SYSCTL_PPI2C register.
1929
//
1930
//*****************************************************************************
1931
#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present
1932
#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present
1933
#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present
1934
#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present
1935
#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
1936
#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
1937
#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
1938
#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
1939
#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
1940
#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
1941
1942
//*****************************************************************************
1943
//
1944
// The following are defines for the bit fields in the SYSCTL_PPUSB register.
1945
//
1946
//*****************************************************************************
1947
#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
1948
1949
//*****************************************************************************
1950
//
1951
// The following are defines for the bit fields in the SYSCTL_PPEPHY register.
1952
//
1953
//*****************************************************************************
1954
#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present
1955
1956
//*****************************************************************************
1957
//
1958
// The following are defines for the bit fields in the SYSCTL_PPCAN register.
1959
//
1960
//*****************************************************************************
1961
#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
1962
#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
1963
1964
//*****************************************************************************
1965
//
1966
// The following are defines for the bit fields in the SYSCTL_PPADC register.
1967
//
1968
//*****************************************************************************
1969
#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
1970
#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
1971
1972
//*****************************************************************************
1973
//
1974
// The following are defines for the bit fields in the SYSCTL_PPACMP register.
1975
//
1976
//*****************************************************************************
1977
#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
1978
1979
//*****************************************************************************
1980
//
1981
// The following are defines for the bit fields in the SYSCTL_PPPWM register.
1982
//
1983
//*****************************************************************************
1984
#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
1985
#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
1986
1987
//*****************************************************************************
1988
//
1989
// The following are defines for the bit fields in the SYSCTL_PPQEI register.
1990
//
1991
//*****************************************************************************
1992
#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
1993
#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
1994
1995
//*****************************************************************************
1996
//
1997
// The following are defines for the bit fields in the SYSCTL_PPLPC register.
1998
//
1999
//*****************************************************************************
2000
#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present
2001
2002
//*****************************************************************************
2003
//
2004
// The following are defines for the bit fields in the SYSCTL_PPPECI register.
2005
//
2006
//*****************************************************************************
2007
#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present
2008
2009
//*****************************************************************************
2010
//
2011
// The following are defines for the bit fields in the SYSCTL_PPFAN register.
2012
//
2013
//*****************************************************************************
2014
#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present
2015
2016
//*****************************************************************************
2017
//
2018
// The following are defines for the bit fields in the SYSCTL_PPEEPROM
2019
// register.
2020
//
2021
//*****************************************************************************
2022
#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
2023
2024
//*****************************************************************************
2025
//
2026
// The following are defines for the bit fields in the SYSCTL_PPWTIMER
2027
// register.
2028
//
2029
//*****************************************************************************
2030
#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose
2031
// Timer 5 Present
2032
#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose
2033
// Timer 4 Present
2034
#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose
2035
// Timer 3 Present
2036
#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose
2037
// Timer 2 Present
2038
#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose
2039
// Timer 1 Present
2040
#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose
2041
// Timer 0 Present
2042
2043
//*****************************************************************************
2044
//
2045
// The following are defines for the bit fields in the SYSCTL_PPRTS register.
2046
//
2047
//*****************************************************************************
2048
#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present
2049
2050
//*****************************************************************************
2051
//
2052
// The following are defines for the bit fields in the SYSCTL_PPCCM register.
2053
//
2054
//*****************************************************************************
2055
#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules
2056
// Present
2057
2058
//*****************************************************************************
2059
//
2060
// The following are defines for the bit fields in the SYSCTL_PPLCD register.
2061
//
2062
//*****************************************************************************
2063
#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present
2064
2065
//*****************************************************************************
2066
//
2067
// The following are defines for the bit fields in the SYSCTL_PPOWIRE register.
2068
//
2069
//*****************************************************************************
2070
#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present
2071
2072
//*****************************************************************************
2073
//
2074
// The following are defines for the bit fields in the SYSCTL_PPEMAC register.
2075
//
2076
//*****************************************************************************
2077
#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module
2078
// Present
2079
2080
//*****************************************************************************
2081
//
2082
// The following are defines for the bit fields in the SYSCTL_PPHIM register.
2083
//
2084
//*****************************************************************************
2085
#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present
2086
2087
//*****************************************************************************
2088
//
2089
// The following are defines for the bit fields in the SYSCTL_SRWD register.
2090
//
2091
//*****************************************************************************
2092
#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
2093
#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
2094
2095
//*****************************************************************************
2096
//
2097
// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
2098
//
2099
//*****************************************************************************
2100
#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
2101
// 7 Software Reset
2102
#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
2103
// 6 Software Reset
2104
#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
2105
// 5 Software Reset
2106
#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
2107
// 4 Software Reset
2108
#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
2109
// 3 Software Reset
2110
#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
2111
// 2 Software Reset
2112
#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
2113
// 1 Software Reset
2114
#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
2115
// 0 Software Reset
2116
2117
//*****************************************************************************
2118
//
2119
// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
2120
//
2121
//*****************************************************************************
2122
#define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset
2123
#define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset
2124
#define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset
2125
#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset
2126
#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
2127
#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
2128
#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
2129
#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
2130
#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
2131
#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
2132
#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
2133
#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
2134
#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
2135
#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
2136
#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
2137
#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
2138
#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
2139
#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
2140
2141
//*****************************************************************************
2142
//
2143
// The following are defines for the bit fields in the SYSCTL_SRDMA register.
2144
//
2145
//*****************************************************************************
2146
#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
2147
2148
//*****************************************************************************
2149
//
2150
// The following are defines for the bit fields in the SYSCTL_SREPI register.
2151
//
2152
//*****************************************************************************
2153
#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset
2154
2155
//*****************************************************************************
2156
//
2157
// The following are defines for the bit fields in the SYSCTL_SRHIB register.
2158
//
2159
//*****************************************************************************
2160
#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
2161
// Reset
2162
2163
//*****************************************************************************
2164
//
2165
// The following are defines for the bit fields in the SYSCTL_SRUART register.
2166
//
2167
//*****************************************************************************
2168
#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
2169
#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
2170
#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
2171
#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
2172
#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
2173
#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
2174
#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
2175
#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
2176
2177
//*****************************************************************************
2178
//
2179
// The following are defines for the bit fields in the SYSCTL_SRSSI register.
2180
//
2181
//*****************************************************************************
2182
#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
2183
#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
2184
#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
2185
#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
2186
2187
//*****************************************************************************
2188
//
2189
// The following are defines for the bit fields in the SYSCTL_SRI2C register.
2190
//
2191
//*****************************************************************************
2192
#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset
2193
#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset
2194
#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset
2195
#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset
2196
#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
2197
#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
2198
#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
2199
#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
2200
#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
2201
#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
2202
2203
//*****************************************************************************
2204
//
2205
// The following are defines for the bit fields in the SYSCTL_SRUSB register.
2206
//
2207
//*****************************************************************************
2208
#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
2209
2210
//*****************************************************************************
2211
//
2212
// The following are defines for the bit fields in the SYSCTL_SREPHY register.
2213
//
2214
//*****************************************************************************
2215
#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software
2216
// Reset
2217
2218
//*****************************************************************************
2219
//
2220
// The following are defines for the bit fields in the SYSCTL_SRCAN register.
2221
//
2222
//*****************************************************************************
2223
#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
2224
#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
2225
2226
//*****************************************************************************
2227
//
2228
// The following are defines for the bit fields in the SYSCTL_SRADC register.
2229
//
2230
//*****************************************************************************
2231
#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
2232
#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
2233
2234
//*****************************************************************************
2235
//
2236
// The following are defines for the bit fields in the SYSCTL_SRACMP register.
2237
//
2238
//*****************************************************************************
2239
#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
2240
// Software Reset
2241
2242
//*****************************************************************************
2243
//
2244
// The following are defines for the bit fields in the SYSCTL_SRPWM register.
2245
//
2246
//*****************************************************************************
2247
#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset
2248
#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset
2249
2250
//*****************************************************************************
2251
//
2252
// The following are defines for the bit fields in the SYSCTL_SRQEI register.
2253
//
2254
//*****************************************************************************
2255
#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset
2256
#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset
2257
2258
//*****************************************************************************
2259
//
2260
// The following are defines for the bit fields in the SYSCTL_SREEPROM
2261
// register.
2262
//
2263
//*****************************************************************************
2264
#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
2265
2266
//*****************************************************************************
2267
//
2268
// The following are defines for the bit fields in the SYSCTL_SRWTIMER
2269
// register.
2270
//
2271
//*****************************************************************************
2272
#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose
2273
// Timer 5 Software Reset
2274
#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose
2275
// Timer 4 Software Reset
2276
#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose
2277
// Timer 3 Software Reset
2278
#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose
2279
// Timer 2 Software Reset
2280
#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose
2281
// Timer 1 Software Reset
2282
#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose
2283
// Timer 0 Software Reset
2284
2285
//*****************************************************************************
2286
//
2287
// The following are defines for the bit fields in the SYSCTL_SRCCM register.
2288
//
2289
//*****************************************************************************
2290
#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules
2291
// Software Reset
2292
2293
//*****************************************************************************
2294
//
2295
// The following are defines for the bit fields in the SYSCTL_SRLCD register.
2296
//
2297
//*****************************************************************************
2298
#define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset
2299
2300
//*****************************************************************************
2301
//
2302
// The following are defines for the bit fields in the SYSCTL_SROWIRE register.
2303
//
2304
//*****************************************************************************
2305
#define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset
2306
2307
//*****************************************************************************
2308
//
2309
// The following are defines for the bit fields in the SYSCTL_SREMAC register.
2310
//
2311
//*****************************************************************************
2312
#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0
2313
// Software Reset
2314
2315
//*****************************************************************************
2316
//
2317
// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
2318
//
2319
//*****************************************************************************
2320
#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
2321
// Gating Control
2322
#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
2323
// Gating Control
2324
2325
//*****************************************************************************
2326
//
2327
// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
2328
// register.
2329
//
2330
//*****************************************************************************
2331
#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
2332
// 7 Run Mode Clock Gating Control
2333
#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
2334
// 6 Run Mode Clock Gating Control
2335
#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
2336
// 5 Run Mode Clock Gating Control
2337
#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
2338
// 4 Run Mode Clock Gating Control
2339
#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
2340
// 3 Run Mode Clock Gating Control
2341
#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
2342
// 2 Run Mode Clock Gating Control
2343
#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
2344
// 1 Run Mode Clock Gating Control
2345
#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
2346
// 0 Run Mode Clock Gating Control
2347
2348
//*****************************************************************************
2349
//
2350
// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
2351
// register.
2352
//
2353
//*****************************************************************************
2354
#define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock
2355
// Gating Control
2356
#define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock
2357
// Gating Control
2358
#define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock
2359
// Gating Control
2360
#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock
2361
// Gating Control
2362
#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
2363
// Gating Control
2364
#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
2365
// Gating Control
2366
#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
2367
// Gating Control
2368
#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
2369
// Gating Control
2370
#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
2371
// Gating Control
2372
#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
2373
// Gating Control
2374
#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
2375
// Gating Control
2376
#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
2377
// Gating Control
2378
#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
2379
// Gating Control
2380
#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
2381
// Gating Control
2382
#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
2383
// Gating Control
2384
#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
2385
// Gating Control
2386
#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
2387
// Gating Control
2388
#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
2389
// Gating Control
2390
2391
//*****************************************************************************
2392
//
2393
// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
2394
//
2395
//*****************************************************************************
2396
#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
2397
// Gating Control
2398
2399
//*****************************************************************************
2400
//
2401
// The following are defines for the bit fields in the SYSCTL_RCGCEPI register.
2402
//
2403
//*****************************************************************************
2404
#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating
2405
// Control
2406
2407
//*****************************************************************************
2408
//
2409
// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
2410
//
2411
//*****************************************************************************
2412
#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
2413
// Clock Gating Control
2414
2415
//*****************************************************************************
2416
//
2417
// The following are defines for the bit fields in the SYSCTL_RCGCUART
2418
// register.
2419
//
2420
//*****************************************************************************
2421
#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
2422
// Gating Control
2423
#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
2424
// Gating Control
2425
#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
2426
// Gating Control
2427
#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
2428
// Gating Control
2429
#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
2430
// Gating Control
2431
#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
2432
// Gating Control
2433
#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
2434
// Gating Control
2435
#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
2436
// Gating Control
2437
2438
//*****************************************************************************
2439
//
2440
// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
2441
//
2442
//*****************************************************************************
2443
#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
2444
// Gating Control
2445
#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
2446
// Gating Control
2447
#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
2448
// Gating Control
2449
#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
2450
// Gating Control
2451
2452
//*****************************************************************************
2453
//
2454
// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
2455
//
2456
//*****************************************************************************
2457
#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock
2458
// Gating Control
2459
#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock
2460
// Gating Control
2461
#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock
2462
// Gating Control
2463
#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock
2464
// Gating Control
2465
#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
2466
// Gating Control
2467
#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
2468
// Gating Control
2469
#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
2470
// Gating Control
2471
#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
2472
// Gating Control
2473
#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
2474
// Gating Control
2475
#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
2476
// Gating Control
2477
2478
//*****************************************************************************
2479
//
2480
// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
2481
//
2482
//*****************************************************************************
2483
#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
2484
// Control
2485
2486
//*****************************************************************************
2487
//
2488
// The following are defines for the bit fields in the SYSCTL_RCGCEPHY
2489
// register.
2490
//
2491
//*****************************************************************************
2492
#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode
2493
// Clock Gating Control
2494
2495
//*****************************************************************************
2496
//
2497
// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
2498
//
2499
//*****************************************************************************
2500
#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
2501
// Gating Control
2502
#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
2503
// Gating Control
2504
2505
//*****************************************************************************
2506
//
2507
// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
2508
//
2509
//*****************************************************************************
2510
#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
2511
// Gating Control
2512
#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
2513
// Gating Control
2514
2515
//*****************************************************************************
2516
//
2517
// The following are defines for the bit fields in the SYSCTL_RCGCACMP
2518
// register.
2519
//
2520
//*****************************************************************************
2521
#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
2522
// Mode Clock Gating Control
2523
2524
//*****************************************************************************
2525
//
2526
// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
2527
//
2528
//*****************************************************************************
2529
#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock
2530
// Gating Control
2531
#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock
2532
// Gating Control
2533
2534
//*****************************************************************************
2535
//
2536
// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
2537
//
2538
//*****************************************************************************
2539
#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock
2540
// Gating Control
2541
#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock
2542
// Gating Control
2543
2544
//*****************************************************************************
2545
//
2546
// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
2547
// register.
2548
//
2549
//*****************************************************************************
2550
#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
2551
// Gating Control
2552
2553
//*****************************************************************************
2554
//
2555
// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
2556
// register.
2557
//
2558
//*****************************************************************************
2559
#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose
2560
// Timer 5 Run Mode Clock Gating
2561
// Control
2562
#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose
2563
// Timer 4 Run Mode Clock Gating
2564
// Control
2565
#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose
2566
// Timer 3 Run Mode Clock Gating
2567
// Control
2568
#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose
2569
// Timer 2 Run Mode Clock Gating
2570
// Control
2571
#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose
2572
// Timer 1 Run Mode Clock Gating
2573
// Control
2574
#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose
2575
// Timer 0 Run Mode Clock Gating
2576
// Control
2577
2578
//*****************************************************************************
2579
//
2580
// The following are defines for the bit fields in the SYSCTL_RCGCCCM register.
2581
//
2582
//*****************************************************************************
2583
#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules
2584
// Run Mode Clock Gating Control
2585
2586
//*****************************************************************************
2587
//
2588
// The following are defines for the bit fields in the SYSCTL_RCGCLCD register.
2589
//
2590
//*****************************************************************************
2591
#define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode
2592
// Clock Gating Control
2593
2594
//*****************************************************************************
2595
//
2596
// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE
2597
// register.
2598
//
2599
//*****************************************************************************
2600
#define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock
2601
// Gating Control
2602
2603
//*****************************************************************************
2604
//
2605
// The following are defines for the bit fields in the SYSCTL_RCGCEMAC
2606
// register.
2607
//
2608
//*****************************************************************************
2609
#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode
2610
// Clock Gating Control
2611
2612
//*****************************************************************************
2613
//
2614
// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
2615
//
2616
//*****************************************************************************
2617
#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
2618
// Clock Gating Control
2619
#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
2620
// Clock Gating Control
2621
2622
//*****************************************************************************
2623
//
2624
// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
2625
// register.
2626
//
2627
//*****************************************************************************
2628
#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer
2629
// 7 Sleep Mode Clock Gating
2630
// Control
2631
#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer
2632
// 6 Sleep Mode Clock Gating
2633
// Control
2634
#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer
2635
// 5 Sleep Mode Clock Gating
2636
// Control
2637
#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer
2638
// 4 Sleep Mode Clock Gating
2639
// Control
2640
#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer
2641
// 3 Sleep Mode Clock Gating
2642
// Control
2643
#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer
2644
// 2 Sleep Mode Clock Gating
2645
// Control
2646
#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer
2647
// 1 Sleep Mode Clock Gating
2648
// Control
2649
#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer
2650
// 0 Sleep Mode Clock Gating
2651
// Control
2652
2653
//*****************************************************************************
2654
//
2655
// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
2656
// register.
2657
//
2658
//*****************************************************************************
2659
#define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock
2660
// Gating Control
2661
#define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock
2662
// Gating Control
2663
#define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock
2664
// Gating Control
2665
#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock
2666
// Gating Control
2667
#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
2668
// Gating Control
2669
#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
2670
// Gating Control
2671
#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
2672
// Gating Control
2673
#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
2674
// Gating Control
2675
#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
2676
// Gating Control
2677
#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
2678
// Gating Control
2679
#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
2680
// Gating Control
2681
#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
2682
// Gating Control
2683
#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
2684
// Gating Control
2685
#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
2686
// Gating Control
2687
#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
2688
// Gating Control
2689
#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
2690
// Gating Control
2691
#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
2692
// Gating Control
2693
#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
2694
// Gating Control
2695
2696
//*****************************************************************************
2697
//
2698
// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
2699
//
2700
//*****************************************************************************
2701
#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
2702
// Gating Control
2703
2704
//*****************************************************************************
2705
//
2706
// The following are defines for the bit fields in the SYSCTL_SCGCEPI register.
2707
//
2708
//*****************************************************************************
2709
#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock
2710
// Gating Control
2711
2712
//*****************************************************************************
2713
//
2714
// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
2715
//
2716
//*****************************************************************************
2717
#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
2718
// Clock Gating Control
2719
2720
//*****************************************************************************
2721
//
2722
// The following are defines for the bit fields in the SYSCTL_SCGCUART
2723
// register.
2724
//
2725
//*****************************************************************************
2726
#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
2727
// Gating Control
2728
#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
2729
// Gating Control
2730
#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
2731
// Gating Control
2732
#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
2733
// Gating Control
2734
#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
2735
// Gating Control
2736
#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
2737
// Gating Control
2738
#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
2739
// Gating Control
2740
#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
2741
// Gating Control
2742
2743
//*****************************************************************************
2744
//
2745
// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
2746
//
2747
//*****************************************************************************
2748
#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
2749
// Gating Control
2750
#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
2751
// Gating Control
2752
#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
2753
// Gating Control
2754
#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
2755
// Gating Control
2756
2757
//*****************************************************************************
2758
//
2759
// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
2760
//
2761
//*****************************************************************************
2762
#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock
2763
// Gating Control
2764
#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock
2765
// Gating Control
2766
#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock
2767
// Gating Control
2768
#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock
2769
// Gating Control
2770
#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
2771
// Gating Control
2772
#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
2773
// Gating Control
2774
#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
2775
// Gating Control
2776
#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
2777
// Gating Control
2778
#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
2779
// Gating Control
2780
#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
2781
// Gating Control
2782
2783
//*****************************************************************************
2784
//
2785
// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
2786
//
2787
//*****************************************************************************
2788
#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
2789
// Gating Control
2790
2791
//*****************************************************************************
2792
//
2793
// The following are defines for the bit fields in the SYSCTL_SCGCEPHY
2794
// register.
2795
//
2796
//*****************************************************************************
2797
#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock
2798
// Gating Control
2799
2800
//*****************************************************************************
2801
//
2802
// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
2803
//
2804
//*****************************************************************************
2805
#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
2806
// Gating Control
2807
#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
2808
// Gating Control
2809
2810
//*****************************************************************************
2811
//
2812
// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
2813
//
2814
//*****************************************************************************
2815
#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
2816
// Gating Control
2817
#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
2818
// Gating Control
2819
2820
//*****************************************************************************
2821
//
2822
// The following are defines for the bit fields in the SYSCTL_SCGCACMP
2823
// register.
2824
//
2825
//*****************************************************************************
2826
#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
2827
// Mode Clock Gating Control
2828
2829
//*****************************************************************************
2830
//
2831
// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
2832
//
2833
//*****************************************************************************
2834
#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock
2835
// Gating Control
2836
#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock
2837
// Gating Control
2838
2839
//*****************************************************************************
2840
//
2841
// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
2842
//
2843
//*****************************************************************************
2844
#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock
2845
// Gating Control
2846
#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock
2847
// Gating Control
2848
2849
//*****************************************************************************
2850
//
2851
// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
2852
// register.
2853
//
2854
//*****************************************************************************
2855
#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
2856
// Gating Control
2857
2858
//*****************************************************************************
2859
//
2860
// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
2861
// register.
2862
//
2863
//*****************************************************************************
2864
#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose
2865
// Timer 5 Sleep Mode Clock Gating
2866
// Control
2867
#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose
2868
// Timer 4 Sleep Mode Clock Gating
2869
// Control
2870
#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose
2871
// Timer 3 Sleep Mode Clock Gating
2872
// Control
2873
#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose
2874
// Timer 2 Sleep Mode Clock Gating
2875
// Control
2876
#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose
2877
// Timer 1 Sleep Mode Clock Gating
2878
// Control
2879
#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose
2880
// Timer 0 Sleep Mode Clock Gating
2881
// Control
2882
2883
//*****************************************************************************
2884
//
2885
// The following are defines for the bit fields in the SYSCTL_SCGCCCM register.
2886
//
2887
//*****************************************************************************
2888
#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules
2889
// Sleep Mode Clock Gating Control
2890
2891
//*****************************************************************************
2892
//
2893
// The following are defines for the bit fields in the SYSCTL_SCGCLCD register.
2894
//
2895
//*****************************************************************************
2896
#define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep
2897
// Mode Clock Gating Control
2898
2899
//*****************************************************************************
2900
//
2901
// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE
2902
// register.
2903
//
2904
//*****************************************************************************
2905
#define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock
2906
// Gating Control
2907
2908
//*****************************************************************************
2909
//
2910
// The following are defines for the bit fields in the SYSCTL_SCGCEMAC
2911
// register.
2912
//
2913
//*****************************************************************************
2914
#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode
2915
// Clock Gating Control
2916
2917
//*****************************************************************************
2918
//
2919
// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
2920
//
2921
//*****************************************************************************
2922
#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
2923
// Clock Gating Control
2924
#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
2925
// Clock Gating Control
2926
2927
//*****************************************************************************
2928
//
2929
// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
2930
// register.
2931
//
2932
//*****************************************************************************
2933
#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer
2934
// 7 Deep-Sleep Mode Clock Gating
2935
// Control
2936
#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer
2937
// 6 Deep-Sleep Mode Clock Gating
2938
// Control
2939
#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer
2940
// 5 Deep-Sleep Mode Clock Gating
2941
// Control
2942
#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer
2943
// 4 Deep-Sleep Mode Clock Gating
2944
// Control
2945
#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer
2946
// 3 Deep-Sleep Mode Clock Gating
2947
// Control
2948
#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer
2949
// 2 Deep-Sleep Mode Clock Gating
2950
// Control
2951
#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer
2952
// 1 Deep-Sleep Mode Clock Gating
2953
// Control
2954
#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer
2955
// 0 Deep-Sleep Mode Clock Gating
2956
// Control
2957
2958
//*****************************************************************************
2959
//
2960
// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
2961
// register.
2962
//
2963
//*****************************************************************************
2964
#define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode
2965
// Clock Gating Control
2966
#define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode
2967
// Clock Gating Control
2968
#define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode
2969
// Clock Gating Control
2970
#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode
2971
// Clock Gating Control
2972
#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
2973
// Clock Gating Control
2974
#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
2975
// Clock Gating Control
2976
#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
2977
// Clock Gating Control
2978
#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
2979
// Clock Gating Control
2980
#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
2981
// Clock Gating Control
2982
#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
2983
// Clock Gating Control
2984
#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
2985
// Clock Gating Control
2986
#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
2987
// Clock Gating Control
2988
#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
2989
// Clock Gating Control
2990
#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
2991
// Clock Gating Control
2992
#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
2993
// Clock Gating Control
2994
#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
2995
// Clock Gating Control
2996
#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
2997
// Clock Gating Control
2998
#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
2999
// Clock Gating Control
3000
3001
//*****************************************************************************
3002
//
3003
// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
3004
//
3005
//*****************************************************************************
3006
#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
3007
// Clock Gating Control
3008
3009
//*****************************************************************************
3010
//
3011
// The following are defines for the bit fields in the SYSCTL_DCGCEPI register.
3012
//
3013
//*****************************************************************************
3014
#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock
3015
// Gating Control
3016
3017
//*****************************************************************************
3018
//
3019
// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
3020
//
3021
//*****************************************************************************
3022
#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
3023
// Mode Clock Gating Control
3024
3025
//*****************************************************************************
3026
//
3027
// The following are defines for the bit fields in the SYSCTL_DCGCUART
3028
// register.
3029
//
3030
//*****************************************************************************
3031
#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
3032
// Clock Gating Control
3033
#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
3034
// Clock Gating Control
3035
#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
3036
// Clock Gating Control
3037
#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
3038
// Clock Gating Control
3039
#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
3040
// Clock Gating Control
3041
#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
3042
// Clock Gating Control
3043
#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
3044
// Clock Gating Control
3045
#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
3046
// Clock Gating Control
3047
3048
//*****************************************************************************
3049
//
3050
// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
3051
//
3052
//*****************************************************************************
3053
#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
3054
// Clock Gating Control
3055
#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
3056
// Clock Gating Control
3057
#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
3058
// Clock Gating Control
3059
#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
3060
// Clock Gating Control
3061
3062
//*****************************************************************************
3063
//
3064
// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
3065
//
3066
//*****************************************************************************
3067
#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode
3068
// Clock Gating Control
3069
#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode
3070
// Clock Gating Control
3071
#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode
3072
// Clock Gating Control
3073
#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode
3074
// Clock Gating Control
3075
#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
3076
// Clock Gating Control
3077
#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
3078
// Clock Gating Control
3079
#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
3080
// Clock Gating Control
3081
#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
3082
// Clock Gating Control
3083
#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
3084
// Clock Gating Control
3085
#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
3086
// Clock Gating Control
3087
3088
//*****************************************************************************
3089
//
3090
// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
3091
//
3092
//*****************************************************************************
3093
#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
3094
// Gating Control
3095
3096
//*****************************************************************************
3097
//
3098
// The following are defines for the bit fields in the SYSCTL_DCGCEPHY
3099
// register.
3100
//
3101
//*****************************************************************************
3102
#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock
3103
// Gating Control
3104
3105
//*****************************************************************************
3106
//
3107
// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
3108
//
3109
//*****************************************************************************
3110
#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
3111
// Clock Gating Control
3112
#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
3113
// Clock Gating Control
3114
3115
//*****************************************************************************
3116
//
3117
// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
3118
//
3119
//*****************************************************************************
3120
#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
3121
// Clock Gating Control
3122
#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
3123
// Clock Gating Control
3124
3125
//*****************************************************************************
3126
//
3127
// The following are defines for the bit fields in the SYSCTL_DCGCACMP
3128
// register.
3129
//
3130
//*****************************************************************************
3131
#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
3132
// Deep-Sleep Mode Clock Gating
3133
// Control
3134
3135
//*****************************************************************************
3136
//
3137
// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
3138
//
3139
//*****************************************************************************
3140
#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode
3141
// Clock Gating Control
3142
#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode
3143
// Clock Gating Control
3144
3145
//*****************************************************************************
3146
//
3147
// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
3148
//
3149
//*****************************************************************************
3150
#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode
3151
// Clock Gating Control
3152
#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode
3153
// Clock Gating Control
3154
3155
//*****************************************************************************
3156
//
3157
// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
3158
// register.
3159
//
3160
//*****************************************************************************
3161
#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
3162
// Clock Gating Control
3163
3164
//*****************************************************************************
3165
//
3166
// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
3167
// register.
3168
//
3169
//*****************************************************************************
3170
#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose
3171
// Timer 5 Deep-Sleep Mode Clock
3172
// Gating Control
3173
#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose
3174
// Timer 4 Deep-Sleep Mode Clock
3175
// Gating Control
3176
#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose
3177
// Timer 3 Deep-Sleep Mode Clock
3178
// Gating Control
3179
#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose
3180
// Timer 2 Deep-Sleep Mode Clock
3181
// Gating Control
3182
#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose
3183
// Timer 1 Deep-Sleep Mode Clock
3184
// Gating Control
3185
#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose
3186
// Timer 0 Deep-Sleep Mode Clock
3187
// Gating Control
3188
3189
//*****************************************************************************
3190
//
3191
// The following are defines for the bit fields in the SYSCTL_DCGCCCM register.
3192
//
3193
//*****************************************************************************
3194
#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules
3195
// Deep-Sleep Mode Clock Gating
3196
// Control
3197
3198
//*****************************************************************************
3199
//
3200
// The following are defines for the bit fields in the SYSCTL_DCGCLCD register.
3201
//
3202
//*****************************************************************************
3203
#define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0
3204
// Deep-Sleep Mode Clock Gating
3205
// Control
3206
3207
//*****************************************************************************
3208
//
3209
// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE
3210
// register.
3211
//
3212
//*****************************************************************************
3213
#define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode
3214
// Clock Gating Control
3215
3216
//*****************************************************************************
3217
//
3218
// The following are defines for the bit fields in the SYSCTL_DCGCEMAC
3219
// register.
3220
//
3221
//*****************************************************************************
3222
#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep
3223
// Mode Clock Gating Control
3224
3225
//*****************************************************************************
3226
//
3227
// The following are defines for the bit fields in the SYSCTL_PCWD register.
3228
//
3229
//*****************************************************************************
3230
#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control
3231
#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control
3232
3233
//*****************************************************************************
3234
//
3235
// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
3236
//
3237
//*****************************************************************************
3238
#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power
3239
// Control
3240
#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power
3241
// Control
3242
#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power
3243
// Control
3244
#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power
3245
// Control
3246
#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power
3247
// Control
3248
#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power
3249
// Control
3250
#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power
3251
// Control
3252
#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power
3253
// Control
3254
3255
//*****************************************************************************
3256
//
3257
// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
3258
//
3259
//*****************************************************************************
3260
#define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control
3261
#define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control
3262
#define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control
3263
#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control
3264
#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control
3265
#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control
3266
#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control
3267
#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control
3268
#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control
3269
#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control
3270
#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control
3271
#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control
3272
#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control
3273
#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control
3274
#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control
3275
#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control
3276
#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control
3277
#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control
3278
3279
//*****************************************************************************
3280
//
3281
// The following are defines for the bit fields in the SYSCTL_PCDMA register.
3282
//
3283
//*****************************************************************************
3284
#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control
3285
3286
//*****************************************************************************
3287
//
3288
// The following are defines for the bit fields in the SYSCTL_PCEPI register.
3289
//
3290
//*****************************************************************************
3291
#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control
3292
3293
//*****************************************************************************
3294
//
3295
// The following are defines for the bit fields in the SYSCTL_PCHIB register.
3296
//
3297
//*****************************************************************************
3298
#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control
3299
3300
//*****************************************************************************
3301
//
3302
// The following are defines for the bit fields in the SYSCTL_PCUART register.
3303
//
3304
//*****************************************************************************
3305
#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control
3306
#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control
3307
#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control
3308
#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control
3309
#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control
3310
#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control
3311
#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control
3312
#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control
3313
3314
//*****************************************************************************
3315
//
3316
// The following are defines for the bit fields in the SYSCTL_PCSSI register.
3317
//
3318
//*****************************************************************************
3319
#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control
3320
#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control
3321
#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control
3322
#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control
3323
3324
//*****************************************************************************
3325
//
3326
// The following are defines for the bit fields in the SYSCTL_PCI2C register.
3327
//
3328
//*****************************************************************************
3329
#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control
3330
#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control
3331
#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control
3332
#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control
3333
#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control
3334
#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control
3335
#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control
3336
#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control
3337
#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control
3338
#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control
3339
3340
//*****************************************************************************
3341
//
3342
// The following are defines for the bit fields in the SYSCTL_PCUSB register.
3343
//
3344
//*****************************************************************************
3345
#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control
3346
3347
//*****************************************************************************
3348
//
3349
// The following are defines for the bit fields in the SYSCTL_PCEPHY register.
3350
//
3351
//*****************************************************************************
3352
#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power
3353
// Control
3354
3355
//*****************************************************************************
3356
//
3357
// The following are defines for the bit fields in the SYSCTL_PCCAN register.
3358
//
3359
//*****************************************************************************
3360
#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control
3361
#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control
3362
3363
//*****************************************************************************
3364
//
3365
// The following are defines for the bit fields in the SYSCTL_PCADC register.
3366
//
3367
//*****************************************************************************
3368
#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control
3369
#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control
3370
3371
//*****************************************************************************
3372
//
3373
// The following are defines for the bit fields in the SYSCTL_PCACMP register.
3374
//
3375
//*****************************************************************************
3376
#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power
3377
// Control
3378
3379
//*****************************************************************************
3380
//
3381
// The following are defines for the bit fields in the SYSCTL_PCPWM register.
3382
//
3383
//*****************************************************************************
3384
#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control
3385
3386
//*****************************************************************************
3387
//
3388
// The following are defines for the bit fields in the SYSCTL_PCQEI register.
3389
//
3390
//*****************************************************************************
3391
#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control
3392
3393
//*****************************************************************************
3394
//
3395
// The following are defines for the bit fields in the SYSCTL_PCEEPROM
3396
// register.
3397
//
3398
//*****************************************************************************
3399
#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control
3400
3401
//*****************************************************************************
3402
//
3403
// The following are defines for the bit fields in the SYSCTL_PCCCM register.
3404
//
3405
//*****************************************************************************
3406
#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules
3407
// Power Control
3408
3409
//*****************************************************************************
3410
//
3411
// The following are defines for the bit fields in the SYSCTL_PCLCD register.
3412
//
3413
//*****************************************************************************
3414
#define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power
3415
// Control
3416
3417
//*****************************************************************************
3418
//
3419
// The following are defines for the bit fields in the SYSCTL_PCOWIRE register.
3420
//
3421
//*****************************************************************************
3422
#define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control
3423
3424
//*****************************************************************************
3425
//
3426
// The following are defines for the bit fields in the SYSCTL_PCEMAC register.
3427
//
3428
//*****************************************************************************
3429
#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power
3430
// Control
3431
3432
//*****************************************************************************
3433
//
3434
// The following are defines for the bit fields in the SYSCTL_PRWD register.
3435
//
3436
//*****************************************************************************
3437
#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
3438
// Ready
3439
#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
3440
// Ready
3441
3442
//*****************************************************************************
3443
//
3444
// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
3445
//
3446
//*****************************************************************************
3447
#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
3448
// 7 Peripheral Ready
3449
#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
3450
// 6 Peripheral Ready
3451
#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
3452
// 5 Peripheral Ready
3453
#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
3454
// 4 Peripheral Ready
3455
#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
3456
// 3 Peripheral Ready
3457
#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
3458
// 2 Peripheral Ready
3459
#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
3460
// 1 Peripheral Ready
3461
#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
3462
// 0 Peripheral Ready
3463
3464
//*****************************************************************************
3465
//
3466
// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
3467
//
3468
//*****************************************************************************
3469
#define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready
3470
#define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready
3471
#define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready
3472
#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready
3473
#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
3474
#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
3475
#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
3476
#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
3477
#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
3478
#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
3479
#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
3480
#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
3481
#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
3482
#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
3483
#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
3484
#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
3485
#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
3486
#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
3487
3488
//*****************************************************************************
3489
//
3490
// The following are defines for the bit fields in the SYSCTL_PRDMA register.
3491
//
3492
//*****************************************************************************
3493
#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
3494
3495
//*****************************************************************************
3496
//
3497
// The following are defines for the bit fields in the SYSCTL_PREPI register.
3498
//
3499
//*****************************************************************************
3500
#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready
3501
3502
//*****************************************************************************
3503
//
3504
// The following are defines for the bit fields in the SYSCTL_PRHIB register.
3505
//
3506
//*****************************************************************************
3507
#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
3508
// Ready
3509
3510
//*****************************************************************************
3511
//
3512
// The following are defines for the bit fields in the SYSCTL_PRUART register.
3513
//
3514
//*****************************************************************************
3515
#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
3516
#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
3517
#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
3518
#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
3519
#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
3520
#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
3521
#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
3522
#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
3523
3524
//*****************************************************************************
3525
//
3526
// The following are defines for the bit fields in the SYSCTL_PRSSI register.
3527
//
3528
//*****************************************************************************
3529
#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
3530
#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
3531
#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
3532
#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
3533
3534
//*****************************************************************************
3535
//
3536
// The following are defines for the bit fields in the SYSCTL_PRI2C register.
3537
//
3538
//*****************************************************************************
3539
#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready
3540
#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready
3541
#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready
3542
#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready
3543
#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
3544
#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
3545
#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
3546
#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
3547
#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
3548
#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
3549
3550
//*****************************************************************************
3551
//
3552
// The following are defines for the bit fields in the SYSCTL_PRUSB register.
3553
//
3554
//*****************************************************************************
3555
#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
3556
3557
//*****************************************************************************
3558
//
3559
// The following are defines for the bit fields in the SYSCTL_PREPHY register.
3560
//
3561
//*****************************************************************************
3562
#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral
3563
// Ready
3564
3565
//*****************************************************************************
3566
//
3567
// The following are defines for the bit fields in the SYSCTL_PRCAN register.
3568
//
3569
//*****************************************************************************
3570
#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
3571
#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
3572
3573
//*****************************************************************************
3574
//
3575
// The following are defines for the bit fields in the SYSCTL_PRADC register.
3576
//
3577
//*****************************************************************************
3578
#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
3579
#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
3580
3581
//*****************************************************************************
3582
//
3583
// The following are defines for the bit fields in the SYSCTL_PRACMP register.
3584
//
3585
//*****************************************************************************
3586
#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
3587
// Peripheral Ready
3588
3589
//*****************************************************************************
3590
//
3591
// The following are defines for the bit fields in the SYSCTL_PRPWM register.
3592
//
3593
//*****************************************************************************
3594
#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready
3595
#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready
3596
3597
//*****************************************************************************
3598
//
3599
// The following are defines for the bit fields in the SYSCTL_PRQEI register.
3600
//
3601
//*****************************************************************************
3602
#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready
3603
#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready
3604
3605
//*****************************************************************************
3606
//
3607
// The following are defines for the bit fields in the SYSCTL_PREEPROM
3608
// register.
3609
//
3610
//*****************************************************************************
3611
#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
3612
3613
//*****************************************************************************
3614
//
3615
// The following are defines for the bit fields in the SYSCTL_PRWTIMER
3616
// register.
3617
//
3618
//*****************************************************************************
3619
#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose
3620
// Timer 5 Peripheral Ready
3621
#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose
3622
// Timer 4 Peripheral Ready
3623
#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose
3624
// Timer 3 Peripheral Ready
3625
#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose
3626
// Timer 2 Peripheral Ready
3627
#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose
3628
// Timer 1 Peripheral Ready
3629
#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose
3630
// Timer 0 Peripheral Ready
3631
3632
//*****************************************************************************
3633
//
3634
// The following are defines for the bit fields in the SYSCTL_PRCCM register.
3635
//
3636
//*****************************************************************************
3637
#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules
3638
// Peripheral Ready
3639
3640
//*****************************************************************************
3641
//
3642
// The following are defines for the bit fields in the SYSCTL_PRLCD register.
3643
//
3644
//*****************************************************************************
3645
#define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0
3646
// Peripheral Ready
3647
3648
//*****************************************************************************
3649
//
3650
// The following are defines for the bit fields in the SYSCTL_PROWIRE register.
3651
//
3652
//*****************************************************************************
3653
#define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready
3654
3655
//*****************************************************************************
3656
//
3657
// The following are defines for the bit fields in the SYSCTL_PREMAC register.
3658
//
3659
//*****************************************************************************
3660
#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral
3661
// Ready
3662
3663
//*****************************************************************************
3664
//
3665
// The following are defines for the bit fields in the SYSCTL_CCMCGREQ
3666
// register.
3667
//
3668
//*****************************************************************************
3669
#define SYSCTL_CCMCGREQ_DESCFG 0x00000004 // DES Clock Gating Request
3670
#define SYSCTL_CCMCGREQ_AESCFG 0x00000002 // AES Clock Gating Request
3671
#define SYSCTL_CCMCGREQ_SHACFG 0x00000001 // SHA/MD5 Clock Gating Request
3672
3673
//*****************************************************************************
3674
//
3675
// The following definitions are deprecated.
3676
//
3677
//*****************************************************************************
3678
#ifndef DEPRECATED
3679
3680
//*****************************************************************************
3681
//
3682
// The following are deprecated defines for the bit fields in the SYSCTL_DID0
3683
// register.
3684
//
3685
//*****************************************************************************
3686
#define SYSCTL_DID0_CLASS_BLIZZARD \
3687
0x00050000 // Tiva(TM) C Series TM4C123-class
3688
// microcontrollers
3689
#define SYSCTL_DID0_CLASS_SNOWFLAKE \
3690
0x000A0000 // Tiva(TM) C Series TM4C129-class
3691
// microcontrollers
3692
3693
//*****************************************************************************
3694
//
3695
// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC
3696
// register.
3697
//
3698
//*****************************************************************************
3699
#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status
3700
#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status
3701
3702
#endif
3703
3704
#endif // __HW_SYSCTL_H__
inc
hw_sysctl.h
Generated on Fri Mar 13 2015 21:18:37 for EE445M RTOS by
1.8.9.1
1.8.9.1 
