EE445M RTOS
Taken at the University of Texas Spring 2015
hw_watchdog.h
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1 //*****************************************************************************
2 //
3 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
4 //
5 // Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
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35 //
36 // This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
37 //
38 //*****************************************************************************
39 
40 #ifndef __HW_WATCHDOG_H__
41 #define __HW_WATCHDOG_H__
42 
43 //*****************************************************************************
44 //
45 // The following are defines for the Watchdog Timer register offsets.
46 //
47 //*****************************************************************************
48 #define WDT_O_LOAD 0x00000000 // Watchdog Load
49 #define WDT_O_VALUE 0x00000004 // Watchdog Value
50 #define WDT_O_CTL 0x00000008 // Watchdog Control
51 #define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
52 #define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
53 #define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
54 #define WDT_O_TEST 0x00000418 // Watchdog Test
55 #define WDT_O_LOCK 0x00000C00 // Watchdog Lock
56 
57 //*****************************************************************************
58 //
59 // The following are defines for the bit fields in the WDT_O_LOAD register.
60 //
61 //*****************************************************************************
62 #define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
63 #define WDT_LOAD_S 0
64 
65 //*****************************************************************************
66 //
67 // The following are defines for the bit fields in the WDT_O_VALUE register.
68 //
69 //*****************************************************************************
70 #define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
71 #define WDT_VALUE_S 0
72 
73 //*****************************************************************************
74 //
75 // The following are defines for the bit fields in the WDT_O_CTL register.
76 //
77 //*****************************************************************************
78 #define WDT_CTL_WRC 0x80000000 // Write Complete
79 #define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
80 #define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
81 #define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
82 
83 //*****************************************************************************
84 //
85 // The following are defines for the bit fields in the WDT_O_ICR register.
86 //
87 //*****************************************************************************
88 #define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
89 #define WDT_ICR_S 0
90 
91 //*****************************************************************************
92 //
93 // The following are defines for the bit fields in the WDT_O_RIS register.
94 //
95 //*****************************************************************************
96 #define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
97 
98 //*****************************************************************************
99 //
100 // The following are defines for the bit fields in the WDT_O_MIS register.
101 //
102 //*****************************************************************************
103 #define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
104 
105 //*****************************************************************************
106 //
107 // The following are defines for the bit fields in the WDT_O_TEST register.
108 //
109 //*****************************************************************************
110 #define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
111 
112 //*****************************************************************************
113 //
114 // The following are defines for the bit fields in the WDT_O_LOCK register.
115 //
116 //*****************************************************************************
117 #define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
118 #define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
119 #define WDT_LOCK_LOCKED 0x00000001 // Locked
120 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
121 
122 #endif // __HW_WATCHDOG_H__