ee445m-labs/tm4c123fe6pm_8h_source.html

//*****************************************************************************

//

// tm4c123fe6pm.h - TM4C123FE6PM Register Definitions

//

// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.

// Software License Agreement

//

//   Redistribution and use in source and binary forms, with or without

//   modification, are permitted provided that the following conditions

//   are met:

//

//   Redistributions of source code must retain the above copyright

//   notice, this list of conditions and the following disclaimer.

//

//   Redistributions in binary form must reproduce the above copyright

//   notice, this list of conditions and the following disclaimer in the

//   documentation and/or other materials provided with the

//   distribution.

//

//   Neither the name of Texas Instruments Incorporated nor the names of

//   its contributors may be used to endorse or promote products derived

//   from this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

//

// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.

//

//*****************************************************************************


#ifndef __TM4C123FE6PM_H__

#define __TM4C123FE6PM_H__


//*****************************************************************************

//

// Interrupt assignments

//

//*****************************************************************************

#define INT_GPIOA               16          // GPIO Port A

#define INT_GPIOB               17          // GPIO Port B

#define INT_GPIOC               18          // GPIO Port C

#define INT_GPIOD               19          // GPIO Port D

#define INT_GPIOE               20          // GPIO Port E

#define INT_UART0               21          // UART0

#define INT_UART1               22          // UART1

#define INT_SSI0                23          // SSI0

#define INT_I2C0                24          // I2C0

#define INT_PWM0_FAULT          25          // PWM0 Fault

#define INT_PWM0_0              26          // PWM0 Generator 0

#define INT_PWM0_1              27          // PWM0 Generator 1

#define INT_PWM0_2              28          // PWM0 Generator 2

#define INT_QEI0                29          // QEI0

#define INT_ADC0SS0             30          // ADC0 Sequence 0

#define INT_ADC0SS1             31          // ADC0 Sequence 1

#define INT_ADC0SS2             32          // ADC0 Sequence 2

#define INT_ADC0SS3             33          // ADC0 Sequence 3

#define INT_WATCHDOG            34          // Watchdog Timers 0 and 1

#define INT_TIMER0A             35          // 16/32-Bit Timer 0A

#define INT_TIMER0B             36          // 16/32-Bit Timer 0B

#define INT_TIMER1A             37          // 16/32-Bit Timer 1A

#define INT_TIMER1B             38          // 16/32-Bit Timer 1B

#define INT_TIMER2A             39          // 16/32-Bit Timer 2A

#define INT_TIMER2B             40          // 16/32-Bit Timer 2B

#define INT_COMP0               41          // Analog Comparator 0

#define INT_COMP1               42          // Analog Comparator 1

#define INT_SYSCTL              44          // System Control

#define INT_FLASH               45          // Flash Memory Control and EEPROM

                                            // Control

#define INT_GPIOF               46          // GPIO Port F

#define INT_GPIOG               47          // GPIO Port G

#define INT_UART2               49          // UART2

#define INT_SSI1                50          // SSI1

#define INT_TIMER3A             51          // 16/32-Bit Timer 3A

#define INT_TIMER3B             52          // Timer 3B

#define INT_I2C1                53          // I2C1

#define INT_QEI1                54          // QEI1

#define INT_CAN0                55          // CAN0

#define INT_CAN1                56          // CAN1

#define INT_USB0                60          // USB

#define INT_PWM0_3              61          // PWM Generator 3

#define INT_UDMA                62          // uDMA Software

#define INT_UDMAERR             63          // uDMA Error

#define INT_ADC1SS0             64          // ADC1 Sequence 0

#define INT_ADC1SS1             65          // ADC1 Sequence 1

#define INT_ADC1SS2             66          // ADC1 Sequence 2

#define INT_ADC1SS3             67          // ADC1 Sequence 3

#define INT_SSI2                73          // SSI2

#define INT_SSI3                74          // SSI3

#define INT_UART3               75          // UART3

#define INT_UART4               76          // UART4

#define INT_UART5               77          // UART5

#define INT_UART6               78          // UART6

#define INT_UART7               79          // UART7

#define INT_I2C2                84          // I2C2

#define INT_I2C3                85          // I2C3

#define INT_TIMER4A             86          // 16/32-Bit Timer 4A

#define INT_TIMER4B             87          // 16/32-Bit Timer 4B

#define INT_TIMER5A             108         // 16/32-Bit Timer 5A

#define INT_TIMER5B             109         // 16/32-Bit Timer 5B

#define INT_WTIMER0A            110         // 32/64-Bit Timer 0A

#define INT_WTIMER0B            111         // 32/64-Bit Timer 0B

#define INT_WTIMER1A            112         // 32/64-Bit Timer 1A

#define INT_WTIMER1B            113         // 32/64-Bit Timer 1B

#define INT_WTIMER2A            114         // 32/64-Bit Timer 2A

#define INT_WTIMER2B            115         // 32/64-Bit Timer 2B

#define INT_WTIMER3A            116         // 32/64-Bit Timer 3A

#define INT_WTIMER3B            117         // 32/64-Bit Timer 3B

#define INT_WTIMER4A            118         // 32/64-Bit Timer 4A

#define INT_WTIMER4B            119         // 32/64-Bit Timer 4B

#define INT_WTIMER5A            120         // 32/64-Bit Timer 5A

#define INT_WTIMER5B            121         // 32/64-Bit Timer 5B

#define INT_SYSEXC              122         // System Exception (imprecise)

#define INT_I2C4                125         // I2C4

#define INT_I2C5                126         // I2C5

#define INT_PWM1_0              150         // PWM1 Generator 0

#define INT_PWM1_1              151         // PWM1 Generator 1

#define INT_PWM1_2              152         // PWM1 Generator 2

#define INT_PWM1_3              153         // PWM1 Generator 3

#define INT_PWM1_FAULT          154         // PWM1 Fault


//*****************************************************************************

//

// Watchdog Timer registers (WATCHDOG0)

//

//*****************************************************************************

#define WATCHDOG0_LOAD_R        (*((volatile uint32_t *)0x40000000))

#define WATCHDOG0_VALUE_R       (*((volatile uint32_t *)0x40000004))

#define WATCHDOG0_CTL_R         (*((volatile uint32_t *)0x40000008))

#define WATCHDOG0_ICR_R         (*((volatile uint32_t *)0x4000000C))

#define WATCHDOG0_RIS_R         (*((volatile uint32_t *)0x40000010))

#define WATCHDOG0_MIS_R         (*((volatile uint32_t *)0x40000014))

#define WATCHDOG0_TEST_R        (*((volatile uint32_t *)0x40000418))

#define WATCHDOG0_LOCK_R        (*((volatile uint32_t *)0x40000C00))


//*****************************************************************************

//

// Watchdog Timer registers (WATCHDOG1)

//

//*****************************************************************************

#define WATCHDOG1_LOAD_R        (*((volatile uint32_t *)0x40001000))

#define WATCHDOG1_VALUE_R       (*((volatile uint32_t *)0x40001004))

#define WATCHDOG1_CTL_R         (*((volatile uint32_t *)0x40001008))

#define WATCHDOG1_ICR_R         (*((volatile uint32_t *)0x4000100C))

#define WATCHDOG1_RIS_R         (*((volatile uint32_t *)0x40001010))

#define WATCHDOG1_MIS_R         (*((volatile uint32_t *)0x40001014))

#define WATCHDOG1_TEST_R        (*((volatile uint32_t *)0x40001418))

#define WATCHDOG1_LOCK_R        (*((volatile uint32_t *)0x40001C00))


//*****************************************************************************

//

// GPIO registers (PORTA)

//

//*****************************************************************************

#define GPIO_PORTA_DATA_BITS_R  ((volatile uint32_t *)0x40004000)

#define GPIO_PORTA_DATA_R       (*((volatile uint32_t *)0x400043FC))

#define GPIO_PORTA_DIR_R        (*((volatile uint32_t *)0x40004400))

#define GPIO_PORTA_IS_R         (*((volatile uint32_t *)0x40004404))

#define GPIO_PORTA_IBE_R        (*((volatile uint32_t *)0x40004408))

#define GPIO_PORTA_IEV_R        (*((volatile uint32_t *)0x4000440C))

#define GPIO_PORTA_IM_R         (*((volatile uint32_t *)0x40004410))

#define GPIO_PORTA_RIS_R        (*((volatile uint32_t *)0x40004414))

#define GPIO_PORTA_MIS_R        (*((volatile uint32_t *)0x40004418))

#define GPIO_PORTA_ICR_R        (*((volatile uint32_t *)0x4000441C))

#define GPIO_PORTA_AFSEL_R      (*((volatile uint32_t *)0x40004420))

#define GPIO_PORTA_DR2R_R       (*((volatile uint32_t *)0x40004500))

#define GPIO_PORTA_DR4R_R       (*((volatile uint32_t *)0x40004504))

#define GPIO_PORTA_DR8R_R       (*((volatile uint32_t *)0x40004508))

#define GPIO_PORTA_ODR_R        (*((volatile uint32_t *)0x4000450C))

#define GPIO_PORTA_PUR_R        (*((volatile uint32_t *)0x40004510))

#define GPIO_PORTA_PDR_R        (*((volatile uint32_t *)0x40004514))

#define GPIO_PORTA_SLR_R        (*((volatile uint32_t *)0x40004518))

#define GPIO_PORTA_DEN_R        (*((volatile uint32_t *)0x4000451C))

#define GPIO_PORTA_LOCK_R       (*((volatile uint32_t *)0x40004520))

#define GPIO_PORTA_CR_R         (*((volatile uint32_t *)0x40004524))

#define GPIO_PORTA_AMSEL_R      (*((volatile uint32_t *)0x40004528))

#define GPIO_PORTA_PCTL_R       (*((volatile uint32_t *)0x4000452C))

#define GPIO_PORTA_ADCCTL_R     (*((volatile uint32_t *)0x40004530))

#define GPIO_PORTA_DMACTL_R     (*((volatile uint32_t *)0x40004534))


//*****************************************************************************

//

// GPIO registers (PORTB)

//

//*****************************************************************************

#define GPIO_PORTB_DATA_BITS_R  ((volatile uint32_t *)0x40005000)

#define GPIO_PORTB_DATA_R       (*((volatile uint32_t *)0x400053FC))

#define GPIO_PORTB_DIR_R        (*((volatile uint32_t *)0x40005400))

#define GPIO_PORTB_IS_R         (*((volatile uint32_t *)0x40005404))

#define GPIO_PORTB_IBE_R        (*((volatile uint32_t *)0x40005408))

#define GPIO_PORTB_IEV_R        (*((volatile uint32_t *)0x4000540C))

#define GPIO_PORTB_IM_R         (*((volatile uint32_t *)0x40005410))

#define GPIO_PORTB_RIS_R        (*((volatile uint32_t *)0x40005414))

#define GPIO_PORTB_MIS_R        (*((volatile uint32_t *)0x40005418))

#define GPIO_PORTB_ICR_R        (*((volatile uint32_t *)0x4000541C))

#define GPIO_PORTB_AFSEL_R      (*((volatile uint32_t *)0x40005420))

#define GPIO_PORTB_DR2R_R       (*((volatile uint32_t *)0x40005500))

#define GPIO_PORTB_DR4R_R       (*((volatile uint32_t *)0x40005504))

#define GPIO_PORTB_DR8R_R       (*((volatile uint32_t *)0x40005508))

#define GPIO_PORTB_ODR_R        (*((volatile uint32_t *)0x4000550C))

#define GPIO_PORTB_PUR_R        (*((volatile uint32_t *)0x40005510))

#define GPIO_PORTB_PDR_R        (*((volatile uint32_t *)0x40005514))

#define GPIO_PORTB_SLR_R        (*((volatile uint32_t *)0x40005518))

#define GPIO_PORTB_DEN_R        (*((volatile uint32_t *)0x4000551C))

#define GPIO_PORTB_LOCK_R       (*((volatile uint32_t *)0x40005520))

#define GPIO_PORTB_CR_R         (*((volatile uint32_t *)0x40005524))

#define GPIO_PORTB_AMSEL_R      (*((volatile uint32_t *)0x40005528))

#define GPIO_PORTB_PCTL_R       (*((volatile uint32_t *)0x4000552C))

#define GPIO_PORTB_ADCCTL_R     (*((volatile uint32_t *)0x40005530))

#define GPIO_PORTB_DMACTL_R     (*((volatile uint32_t *)0x40005534))


//*****************************************************************************

//

// GPIO registers (PORTC)

//

//*****************************************************************************

#define GPIO_PORTC_DATA_BITS_R  ((volatile uint32_t *)0x40006000)

#define GPIO_PORTC_DATA_R       (*((volatile uint32_t *)0x400063FC))

#define GPIO_PORTC_DIR_R        (*((volatile uint32_t *)0x40006400))

#define GPIO_PORTC_IS_R         (*((volatile uint32_t *)0x40006404))

#define GPIO_PORTC_IBE_R        (*((volatile uint32_t *)0x40006408))

#define GPIO_PORTC_IEV_R        (*((volatile uint32_t *)0x4000640C))

#define GPIO_PORTC_IM_R         (*((volatile uint32_t *)0x40006410))

#define GPIO_PORTC_RIS_R        (*((volatile uint32_t *)0x40006414))

#define GPIO_PORTC_MIS_R        (*((volatile uint32_t *)0x40006418))

#define GPIO_PORTC_ICR_R        (*((volatile uint32_t *)0x4000641C))

#define GPIO_PORTC_AFSEL_R      (*((volatile uint32_t *)0x40006420))

#define GPIO_PORTC_DR2R_R       (*((volatile uint32_t *)0x40006500))

#define GPIO_PORTC_DR4R_R       (*((volatile uint32_t *)0x40006504))

#define GPIO_PORTC_DR8R_R       (*((volatile uint32_t *)0x40006508))

#define GPIO_PORTC_ODR_R        (*((volatile uint32_t *)0x4000650C))

#define GPIO_PORTC_PUR_R        (*((volatile uint32_t *)0x40006510))

#define GPIO_PORTC_PDR_R        (*((volatile uint32_t *)0x40006514))

#define GPIO_PORTC_SLR_R        (*((volatile uint32_t *)0x40006518))

#define GPIO_PORTC_DEN_R        (*((volatile uint32_t *)0x4000651C))

#define GPIO_PORTC_LOCK_R       (*((volatile uint32_t *)0x40006520))

#define GPIO_PORTC_CR_R         (*((volatile uint32_t *)0x40006524))

#define GPIO_PORTC_AMSEL_R      (*((volatile uint32_t *)0x40006528))

#define GPIO_PORTC_PCTL_R       (*((volatile uint32_t *)0x4000652C))

#define GPIO_PORTC_ADCCTL_R     (*((volatile uint32_t *)0x40006530))

#define GPIO_PORTC_DMACTL_R     (*((volatile uint32_t *)0x40006534))


//*****************************************************************************

//

// GPIO registers (PORTD)

//

//*****************************************************************************

#define GPIO_PORTD_DATA_BITS_R  ((volatile uint32_t *)0x40007000)

#define GPIO_PORTD_DATA_R       (*((volatile uint32_t *)0x400073FC))

#define GPIO_PORTD_DIR_R        (*((volatile uint32_t *)0x40007400))

#define GPIO_PORTD_IS_R         (*((volatile uint32_t *)0x40007404))

#define GPIO_PORTD_IBE_R        (*((volatile uint32_t *)0x40007408))

#define GPIO_PORTD_IEV_R        (*((volatile uint32_t *)0x4000740C))

#define GPIO_PORTD_IM_R         (*((volatile uint32_t *)0x40007410))

#define GPIO_PORTD_RIS_R        (*((volatile uint32_t *)0x40007414))

#define GPIO_PORTD_MIS_R        (*((volatile uint32_t *)0x40007418))

#define GPIO_PORTD_ICR_R        (*((volatile uint32_t *)0x4000741C))

#define GPIO_PORTD_AFSEL_R      (*((volatile uint32_t *)0x40007420))

#define GPIO_PORTD_DR2R_R       (*((volatile uint32_t *)0x40007500))

#define GPIO_PORTD_DR4R_R       (*((volatile uint32_t *)0x40007504))

#define GPIO_PORTD_DR8R_R       (*((volatile uint32_t *)0x40007508))

#define GPIO_PORTD_ODR_R        (*((volatile uint32_t *)0x4000750C))

#define GPIO_PORTD_PUR_R        (*((volatile uint32_t *)0x40007510))

#define GPIO_PORTD_PDR_R        (*((volatile uint32_t *)0x40007514))

#define GPIO_PORTD_SLR_R        (*((volatile uint32_t *)0x40007518))

#define GPIO_PORTD_DEN_R        (*((volatile uint32_t *)0x4000751C))

#define GPIO_PORTD_LOCK_R       (*((volatile uint32_t *)0x40007520))

#define GPIO_PORTD_CR_R         (*((volatile uint32_t *)0x40007524))

#define GPIO_PORTD_AMSEL_R      (*((volatile uint32_t *)0x40007528))

#define GPIO_PORTD_PCTL_R       (*((volatile uint32_t *)0x4000752C))

#define GPIO_PORTD_ADCCTL_R     (*((volatile uint32_t *)0x40007530))

#define GPIO_PORTD_DMACTL_R     (*((volatile uint32_t *)0x40007534))


//*****************************************************************************

//

// SSI registers (SSI0)

//

//*****************************************************************************

#define SSI0_CR0_R              (*((volatile uint32_t *)0x40008000))

#define SSI0_CR1_R              (*((volatile uint32_t *)0x40008004))

#define SSI0_DR_R               (*((volatile uint32_t *)0x40008008))

#define SSI0_SR_R               (*((volatile uint32_t *)0x4000800C))

#define SSI0_CPSR_R             (*((volatile uint32_t *)0x40008010))

#define SSI0_IM_R               (*((volatile uint32_t *)0x40008014))

#define SSI0_RIS_R              (*((volatile uint32_t *)0x40008018))

#define SSI0_MIS_R              (*((volatile uint32_t *)0x4000801C))

#define SSI0_ICR_R              (*((volatile uint32_t *)0x40008020))

#define SSI0_DMACTL_R           (*((volatile uint32_t *)0x40008024))

#define SSI0_CC_R               (*((volatile uint32_t *)0x40008FC8))


//*****************************************************************************

//

// SSI registers (SSI1)

//

//*****************************************************************************

#define SSI1_CR0_R              (*((volatile uint32_t *)0x40009000))

#define SSI1_CR1_R              (*((volatile uint32_t *)0x40009004))

#define SSI1_DR_R               (*((volatile uint32_t *)0x40009008))

#define SSI1_SR_R               (*((volatile uint32_t *)0x4000900C))

#define SSI1_CPSR_R             (*((volatile uint32_t *)0x40009010))

#define SSI1_IM_R               (*((volatile uint32_t *)0x40009014))

#define SSI1_RIS_R              (*((volatile uint32_t *)0x40009018))

#define SSI1_MIS_R              (*((volatile uint32_t *)0x4000901C))

#define SSI1_ICR_R              (*((volatile uint32_t *)0x40009020))

#define SSI1_DMACTL_R           (*((volatile uint32_t *)0x40009024))

#define SSI1_CC_R               (*((volatile uint32_t *)0x40009FC8))


//*****************************************************************************

//

// SSI registers (SSI2)

//

//*****************************************************************************

#define SSI2_CR0_R              (*((volatile uint32_t *)0x4000A000))

#define SSI2_CR1_R              (*((volatile uint32_t *)0x4000A004))

#define SSI2_DR_R               (*((volatile uint32_t *)0x4000A008))

#define SSI2_SR_R               (*((volatile uint32_t *)0x4000A00C))

#define SSI2_CPSR_R             (*((volatile uint32_t *)0x4000A010))

#define SSI2_IM_R               (*((volatile uint32_t *)0x4000A014))

#define SSI2_RIS_R              (*((volatile uint32_t *)0x4000A018))

#define SSI2_MIS_R              (*((volatile uint32_t *)0x4000A01C))

#define SSI2_ICR_R              (*((volatile uint32_t *)0x4000A020))

#define SSI2_DMACTL_R           (*((volatile uint32_t *)0x4000A024))

#define SSI2_CC_R               (*((volatile uint32_t *)0x4000AFC8))


//*****************************************************************************

//

// SSI registers (SSI3)

//

//*****************************************************************************

#define SSI3_CR0_R              (*((volatile uint32_t *)0x4000B000))

#define SSI3_CR1_R              (*((volatile uint32_t *)0x4000B004))

#define SSI3_DR_R               (*((volatile uint32_t *)0x4000B008))

#define SSI3_SR_R               (*((volatile uint32_t *)0x4000B00C))

#define SSI3_CPSR_R             (*((volatile uint32_t *)0x4000B010))

#define SSI3_IM_R               (*((volatile uint32_t *)0x4000B014))

#define SSI3_RIS_R              (*((volatile uint32_t *)0x4000B018))

#define SSI3_MIS_R              (*((volatile uint32_t *)0x4000B01C))

#define SSI3_ICR_R              (*((volatile uint32_t *)0x4000B020))

#define SSI3_DMACTL_R           (*((volatile uint32_t *)0x4000B024))

#define SSI3_CC_R               (*((volatile uint32_t *)0x4000BFC8))


//*****************************************************************************

//

// UART registers (UART0)

//

//*****************************************************************************

#define UART0_DR_R              (*((volatile uint32_t *)0x4000C000))

#define UART0_RSR_R             (*((volatile uint32_t *)0x4000C004))

#define UART0_ECR_R             (*((volatile uint32_t *)0x4000C004))

#define UART0_FR_R              (*((volatile uint32_t *)0x4000C018))

#define UART0_ILPR_R            (*((volatile uint32_t *)0x4000C020))

#define UART0_IBRD_R            (*((volatile uint32_t *)0x4000C024))

#define UART0_FBRD_R            (*((volatile uint32_t *)0x4000C028))

#define UART0_LCRH_R            (*((volatile uint32_t *)0x4000C02C))

#define UART0_CTL_R             (*((volatile uint32_t *)0x4000C030))

#define UART0_IFLS_R            (*((volatile uint32_t *)0x4000C034))

#define UART0_IM_R              (*((volatile uint32_t *)0x4000C038))

#define UART0_RIS_R             (*((volatile uint32_t *)0x4000C03C))

#define UART0_MIS_R             (*((volatile uint32_t *)0x4000C040))

#define UART0_ICR_R             (*((volatile uint32_t *)0x4000C044))

#define UART0_DMACTL_R          (*((volatile uint32_t *)0x4000C048))

#define UART0_9BITADDR_R        (*((volatile uint32_t *)0x4000C0A4))

#define UART0_9BITAMASK_R       (*((volatile uint32_t *)0x4000C0A8))

#define UART0_PP_R              (*((volatile uint32_t *)0x4000CFC0))

#define UART0_CC_R              (*((volatile uint32_t *)0x4000CFC8))


//*****************************************************************************

//

// UART registers (UART1)

//

//*****************************************************************************

#define UART1_DR_R              (*((volatile uint32_t *)0x4000D000))

#define UART1_RSR_R             (*((volatile uint32_t *)0x4000D004))

#define UART1_ECR_R             (*((volatile uint32_t *)0x4000D004))

#define UART1_FR_R              (*((volatile uint32_t *)0x4000D018))

#define UART1_ILPR_R            (*((volatile uint32_t *)0x4000D020))

#define UART1_IBRD_R            (*((volatile uint32_t *)0x4000D024))

#define UART1_FBRD_R            (*((volatile uint32_t *)0x4000D028))

#define UART1_LCRH_R            (*((volatile uint32_t *)0x4000D02C))

#define UART1_CTL_R             (*((volatile uint32_t *)0x4000D030))

#define UART1_IFLS_R            (*((volatile uint32_t *)0x4000D034))

#define UART1_IM_R              (*((volatile uint32_t *)0x4000D038))

#define UART1_RIS_R             (*((volatile uint32_t *)0x4000D03C))

#define UART1_MIS_R             (*((volatile uint32_t *)0x4000D040))

#define UART1_ICR_R             (*((volatile uint32_t *)0x4000D044))

#define UART1_DMACTL_R          (*((volatile uint32_t *)0x4000D048))

#define UART1_9BITADDR_R        (*((volatile uint32_t *)0x4000D0A4))

#define UART1_9BITAMASK_R       (*((volatile uint32_t *)0x4000D0A8))

#define UART1_PP_R              (*((volatile uint32_t *)0x4000DFC0))

#define UART1_CC_R              (*((volatile uint32_t *)0x4000DFC8))


//*****************************************************************************

//

// UART registers (UART2)

//

//*****************************************************************************

#define UART2_DR_R              (*((volatile uint32_t *)0x4000E000))

#define UART2_RSR_R             (*((volatile uint32_t *)0x4000E004))

#define UART2_ECR_R             (*((volatile uint32_t *)0x4000E004))

#define UART2_FR_R              (*((volatile uint32_t *)0x4000E018))

#define UART2_ILPR_R            (*((volatile uint32_t *)0x4000E020))

#define UART2_IBRD_R            (*((volatile uint32_t *)0x4000E024))

#define UART2_FBRD_R            (*((volatile uint32_t *)0x4000E028))

#define UART2_LCRH_R            (*((volatile uint32_t *)0x4000E02C))

#define UART2_CTL_R             (*((volatile uint32_t *)0x4000E030))

#define UART2_IFLS_R            (*((volatile uint32_t *)0x4000E034))

#define UART2_IM_R              (*((volatile uint32_t *)0x4000E038))

#define UART2_RIS_R             (*((volatile uint32_t *)0x4000E03C))

#define UART2_MIS_R             (*((volatile uint32_t *)0x4000E040))

#define UART2_ICR_R             (*((volatile uint32_t *)0x4000E044))

#define UART2_DMACTL_R          (*((volatile uint32_t *)0x4000E048))

#define UART2_9BITADDR_R        (*((volatile uint32_t *)0x4000E0A4))

#define UART2_9BITAMASK_R       (*((volatile uint32_t *)0x4000E0A8))

#define UART2_PP_R              (*((volatile uint32_t *)0x4000EFC0))

#define UART2_CC_R              (*((volatile uint32_t *)0x4000EFC8))


//*****************************************************************************

//

// UART registers (UART3)

//

//*****************************************************************************

#define UART3_DR_R              (*((volatile uint32_t *)0x4000F000))

#define UART3_RSR_R             (*((volatile uint32_t *)0x4000F004))

#define UART3_ECR_R             (*((volatile uint32_t *)0x4000F004))

#define UART3_FR_R              (*((volatile uint32_t *)0x4000F018))

#define UART3_ILPR_R            (*((volatile uint32_t *)0x4000F020))

#define UART3_IBRD_R            (*((volatile uint32_t *)0x4000F024))

#define UART3_FBRD_R            (*((volatile uint32_t *)0x4000F028))

#define UART3_LCRH_R            (*((volatile uint32_t *)0x4000F02C))

#define UART3_CTL_R             (*((volatile uint32_t *)0x4000F030))

#define UART3_IFLS_R            (*((volatile uint32_t *)0x4000F034))

#define UART3_IM_R              (*((volatile uint32_t *)0x4000F038))

#define UART3_RIS_R             (*((volatile uint32_t *)0x4000F03C))

#define UART3_MIS_R             (*((volatile uint32_t *)0x4000F040))

#define UART3_ICR_R             (*((volatile uint32_t *)0x4000F044))

#define UART3_DMACTL_R          (*((volatile uint32_t *)0x4000F048))

#define UART3_9BITADDR_R        (*((volatile uint32_t *)0x4000F0A4))

#define UART3_9BITAMASK_R       (*((volatile uint32_t *)0x4000F0A8))

#define UART3_PP_R              (*((volatile uint32_t *)0x4000FFC0))

#define UART3_CC_R              (*((volatile uint32_t *)0x4000FFC8))


//*****************************************************************************

//

// UART registers (UART4)

//

//*****************************************************************************

#define UART4_DR_R              (*((volatile uint32_t *)0x40010000))

#define UART4_RSR_R             (*((volatile uint32_t *)0x40010004))

#define UART4_ECR_R             (*((volatile uint32_t *)0x40010004))

#define UART4_FR_R              (*((volatile uint32_t *)0x40010018))

#define UART4_ILPR_R            (*((volatile uint32_t *)0x40010020))

#define UART4_IBRD_R            (*((volatile uint32_t *)0x40010024))

#define UART4_FBRD_R            (*((volatile uint32_t *)0x40010028))

#define UART4_LCRH_R            (*((volatile uint32_t *)0x4001002C))

#define UART4_CTL_R             (*((volatile uint32_t *)0x40010030))

#define UART4_IFLS_R            (*((volatile uint32_t *)0x40010034))

#define UART4_IM_R              (*((volatile uint32_t *)0x40010038))

#define UART4_RIS_R             (*((volatile uint32_t *)0x4001003C))

#define UART4_MIS_R             (*((volatile uint32_t *)0x40010040))

#define UART4_ICR_R             (*((volatile uint32_t *)0x40010044))

#define UART4_DMACTL_R          (*((volatile uint32_t *)0x40010048))

#define UART4_9BITADDR_R        (*((volatile uint32_t *)0x400100A4))

#define UART4_9BITAMASK_R       (*((volatile uint32_t *)0x400100A8))

#define UART4_PP_R              (*((volatile uint32_t *)0x40010FC0))

#define UART4_CC_R              (*((volatile uint32_t *)0x40010FC8))


//*****************************************************************************

//

// UART registers (UART5)

//

//*****************************************************************************

#define UART5_DR_R              (*((volatile uint32_t *)0x40011000))

#define UART5_RSR_R             (*((volatile uint32_t *)0x40011004))

#define UART5_ECR_R             (*((volatile uint32_t *)0x40011004))

#define UART5_FR_R              (*((volatile uint32_t *)0x40011018))

#define UART5_ILPR_R            (*((volatile uint32_t *)0x40011020))

#define UART5_IBRD_R            (*((volatile uint32_t *)0x40011024))

#define UART5_FBRD_R            (*((volatile uint32_t *)0x40011028))

#define UART5_LCRH_R            (*((volatile uint32_t *)0x4001102C))

#define UART5_CTL_R             (*((volatile uint32_t *)0x40011030))

#define UART5_IFLS_R            (*((volatile uint32_t *)0x40011034))

#define UART5_IM_R              (*((volatile uint32_t *)0x40011038))

#define UART5_RIS_R             (*((volatile uint32_t *)0x4001103C))

#define UART5_MIS_R             (*((volatile uint32_t *)0x40011040))

#define UART5_ICR_R             (*((volatile uint32_t *)0x40011044))

#define UART5_DMACTL_R          (*((volatile uint32_t *)0x40011048))

#define UART5_9BITADDR_R        (*((volatile uint32_t *)0x400110A4))

#define UART5_9BITAMASK_R       (*((volatile uint32_t *)0x400110A8))

#define UART5_PP_R              (*((volatile uint32_t *)0x40011FC0))

#define UART5_CC_R              (*((volatile uint32_t *)0x40011FC8))


//*****************************************************************************

//

// UART registers (UART6)

//

//*****************************************************************************

#define UART6_DR_R              (*((volatile uint32_t *)0x40012000))

#define UART6_RSR_R             (*((volatile uint32_t *)0x40012004))

#define UART6_ECR_R             (*((volatile uint32_t *)0x40012004))

#define UART6_FR_R              (*((volatile uint32_t *)0x40012018))

#define UART6_ILPR_R            (*((volatile uint32_t *)0x40012020))

#define UART6_IBRD_R            (*((volatile uint32_t *)0x40012024))

#define UART6_FBRD_R            (*((volatile uint32_t *)0x40012028))

#define UART6_LCRH_R            (*((volatile uint32_t *)0x4001202C))

#define UART6_CTL_R             (*((volatile uint32_t *)0x40012030))

#define UART6_IFLS_R            (*((volatile uint32_t *)0x40012034))

#define UART6_IM_R              (*((volatile uint32_t *)0x40012038))

#define UART6_RIS_R             (*((volatile uint32_t *)0x4001203C))

#define UART6_MIS_R             (*((volatile uint32_t *)0x40012040))

#define UART6_ICR_R             (*((volatile uint32_t *)0x40012044))

#define UART6_DMACTL_R          (*((volatile uint32_t *)0x40012048))

#define UART6_9BITADDR_R        (*((volatile uint32_t *)0x400120A4))

#define UART6_9BITAMASK_R       (*((volatile uint32_t *)0x400120A8))

#define UART6_PP_R              (*((volatile uint32_t *)0x40012FC0))

#define UART6_CC_R              (*((volatile uint32_t *)0x40012FC8))


//*****************************************************************************

//

// UART registers (UART7)

//

//*****************************************************************************

#define UART7_DR_R              (*((volatile uint32_t *)0x40013000))

#define UART7_RSR_R             (*((volatile uint32_t *)0x40013004))

#define UART7_ECR_R             (*((volatile uint32_t *)0x40013004))

#define UART7_FR_R              (*((volatile uint32_t *)0x40013018))

#define UART7_ILPR_R            (*((volatile uint32_t *)0x40013020))

#define UART7_IBRD_R            (*((volatile uint32_t *)0x40013024))

#define UART7_FBRD_R            (*((volatile uint32_t *)0x40013028))

#define UART7_LCRH_R            (*((volatile uint32_t *)0x4001302C))

#define UART7_CTL_R             (*((volatile uint32_t *)0x40013030))

#define UART7_IFLS_R            (*((volatile uint32_t *)0x40013034))

#define UART7_IM_R              (*((volatile uint32_t *)0x40013038))

#define UART7_RIS_R             (*((volatile uint32_t *)0x4001303C))

#define UART7_MIS_R             (*((volatile uint32_t *)0x40013040))

#define UART7_ICR_R             (*((volatile uint32_t *)0x40013044))

#define UART7_DMACTL_R          (*((volatile uint32_t *)0x40013048))

#define UART7_9BITADDR_R        (*((volatile uint32_t *)0x400130A4))

#define UART7_9BITAMASK_R       (*((volatile uint32_t *)0x400130A8))

#define UART7_PP_R              (*((volatile uint32_t *)0x40013FC0))

#define UART7_CC_R              (*((volatile uint32_t *)0x40013FC8))


//*****************************************************************************

//

// I2C registers (I2C0)

//

//*****************************************************************************

#define I2C0_MSA_R              (*((volatile uint32_t *)0x40020000))

#define I2C0_MCS_R              (*((volatile uint32_t *)0x40020004))

#define I2C0_MDR_R              (*((volatile uint32_t *)0x40020008))

#define I2C0_MTPR_R             (*((volatile uint32_t *)0x4002000C))

#define I2C0_MIMR_R             (*((volatile uint32_t *)0x40020010))

#define I2C0_MRIS_R             (*((volatile uint32_t *)0x40020014))

#define I2C0_MMIS_R             (*((volatile uint32_t *)0x40020018))

#define I2C0_MICR_R             (*((volatile uint32_t *)0x4002001C))

#define I2C0_MCR_R              (*((volatile uint32_t *)0x40020020))

#define I2C0_MCLKOCNT_R         (*((volatile uint32_t *)0x40020024))

#define I2C0_MBMON_R            (*((volatile uint32_t *)0x4002002C))

#define I2C0_MCR2_R             (*((volatile uint32_t *)0x40020038))

#define I2C0_SOAR_R             (*((volatile uint32_t *)0x40020800))

#define I2C0_SCSR_R             (*((volatile uint32_t *)0x40020804))

#define I2C0_SDR_R              (*((volatile uint32_t *)0x40020808))

#define I2C0_SIMR_R             (*((volatile uint32_t *)0x4002080C))

#define I2C0_SRIS_R             (*((volatile uint32_t *)0x40020810))

#define I2C0_SMIS_R             (*((volatile uint32_t *)0x40020814))

#define I2C0_SICR_R             (*((volatile uint32_t *)0x40020818))

#define I2C0_SOAR2_R            (*((volatile uint32_t *)0x4002081C))

#define I2C0_SACKCTL_R          (*((volatile uint32_t *)0x40020820))

#define I2C0_PP_R               (*((volatile uint32_t *)0x40020FC0))

#define I2C0_PC_R               (*((volatile uint32_t *)0x40020FC4))


//*****************************************************************************

//

// I2C registers (I2C1)

//

//*****************************************************************************

#define I2C1_MSA_R              (*((volatile uint32_t *)0x40021000))

#define I2C1_MCS_R              (*((volatile uint32_t *)0x40021004))

#define I2C1_MDR_R              (*((volatile uint32_t *)0x40021008))

#define I2C1_MTPR_R             (*((volatile uint32_t *)0x4002100C))

#define I2C1_MIMR_R             (*((volatile uint32_t *)0x40021010))

#define I2C1_MRIS_R             (*((volatile uint32_t *)0x40021014))

#define I2C1_MMIS_R             (*((volatile uint32_t *)0x40021018))

#define I2C1_MICR_R             (*((volatile uint32_t *)0x4002101C))

#define I2C1_MCR_R              (*((volatile uint32_t *)0x40021020))

#define I2C1_MCLKOCNT_R         (*((volatile uint32_t *)0x40021024))

#define I2C1_MBMON_R            (*((volatile uint32_t *)0x4002102C))

#define I2C1_MCR2_R             (*((volatile uint32_t *)0x40021038))

#define I2C1_SOAR_R             (*((volatile uint32_t *)0x40021800))

#define I2C1_SCSR_R             (*((volatile uint32_t *)0x40021804))

#define I2C1_SDR_R              (*((volatile uint32_t *)0x40021808))

#define I2C1_SIMR_R             (*((volatile uint32_t *)0x4002180C))

#define I2C1_SRIS_R             (*((volatile uint32_t *)0x40021810))

#define I2C1_SMIS_R             (*((volatile uint32_t *)0x40021814))

#define I2C1_SICR_R             (*((volatile uint32_t *)0x40021818))

#define I2C1_SOAR2_R            (*((volatile uint32_t *)0x4002181C))

#define I2C1_SACKCTL_R          (*((volatile uint32_t *)0x40021820))

#define I2C1_PP_R               (*((volatile uint32_t *)0x40021FC0))

#define I2C1_PC_R               (*((volatile uint32_t *)0x40021FC4))


//*****************************************************************************

//

// I2C registers (I2C2)

//

//*****************************************************************************

#define I2C2_MSA_R              (*((volatile uint32_t *)0x40022000))

#define I2C2_MCS_R              (*((volatile uint32_t *)0x40022004))

#define I2C2_MDR_R              (*((volatile uint32_t *)0x40022008))

#define I2C2_MTPR_R             (*((volatile uint32_t *)0x4002200C))

#define I2C2_MIMR_R             (*((volatile uint32_t *)0x40022010))

#define I2C2_MRIS_R             (*((volatile uint32_t *)0x40022014))

#define I2C2_MMIS_R             (*((volatile uint32_t *)0x40022018))

#define I2C2_MICR_R             (*((volatile uint32_t *)0x4002201C))

#define I2C2_MCR_R              (*((volatile uint32_t *)0x40022020))

#define I2C2_MCLKOCNT_R         (*((volatile uint32_t *)0x40022024))

#define I2C2_MBMON_R            (*((volatile uint32_t *)0x4002202C))

#define I2C2_MCR2_R             (*((volatile uint32_t *)0x40022038))

#define I2C2_SOAR_R             (*((volatile uint32_t *)0x40022800))

#define I2C2_SCSR_R             (*((volatile uint32_t *)0x40022804))

#define I2C2_SDR_R              (*((volatile uint32_t *)0x40022808))

#define I2C2_SIMR_R             (*((volatile uint32_t *)0x4002280C))

#define I2C2_SRIS_R             (*((volatile uint32_t *)0x40022810))

#define I2C2_SMIS_R             (*((volatile uint32_t *)0x40022814))

#define I2C2_SICR_R             (*((volatile uint32_t *)0x40022818))

#define I2C2_SOAR2_R            (*((volatile uint32_t *)0x4002281C))

#define I2C2_SACKCTL_R          (*((volatile uint32_t *)0x40022820))

#define I2C2_PP_R               (*((volatile uint32_t *)0x40022FC0))

#define I2C2_PC_R               (*((volatile uint32_t *)0x40022FC4))


//*****************************************************************************

//

// I2C registers (I2C3)

//

//*****************************************************************************

#define I2C3_MSA_R              (*((volatile uint32_t *)0x40023000))

#define I2C3_MCS_R              (*((volatile uint32_t *)0x40023004))

#define I2C3_MDR_R              (*((volatile uint32_t *)0x40023008))

#define I2C3_MTPR_R             (*((volatile uint32_t *)0x4002300C))

#define I2C3_MIMR_R             (*((volatile uint32_t *)0x40023010))

#define I2C3_MRIS_R             (*((volatile uint32_t *)0x40023014))

#define I2C3_MMIS_R             (*((volatile uint32_t *)0x40023018))

#define I2C3_MICR_R             (*((volatile uint32_t *)0x4002301C))

#define I2C3_MCR_R              (*((volatile uint32_t *)0x40023020))

#define I2C3_MCLKOCNT_R         (*((volatile uint32_t *)0x40023024))

#define I2C3_MBMON_R            (*((volatile uint32_t *)0x4002302C))

#define I2C3_MCR2_R             (*((volatile uint32_t *)0x40023038))

#define I2C3_SOAR_R             (*((volatile uint32_t *)0x40023800))

#define I2C3_SCSR_R             (*((volatile uint32_t *)0x40023804))

#define I2C3_SDR_R              (*((volatile uint32_t *)0x40023808))

#define I2C3_SIMR_R             (*((volatile uint32_t *)0x4002380C))

#define I2C3_SRIS_R             (*((volatile uint32_t *)0x40023810))

#define I2C3_SMIS_R             (*((volatile uint32_t *)0x40023814))

#define I2C3_SICR_R             (*((volatile uint32_t *)0x40023818))

#define I2C3_SOAR2_R            (*((volatile uint32_t *)0x4002381C))

#define I2C3_SACKCTL_R          (*((volatile uint32_t *)0x40023820))

#define I2C3_PP_R               (*((volatile uint32_t *)0x40023FC0))

#define I2C3_PC_R               (*((volatile uint32_t *)0x40023FC4))


//*****************************************************************************

//

// GPIO registers (PORTE)

//

//*****************************************************************************

#define GPIO_PORTE_DATA_BITS_R  ((volatile uint32_t *)0x40024000)

#define GPIO_PORTE_DATA_R       (*((volatile uint32_t *)0x400243FC))

#define GPIO_PORTE_DIR_R        (*((volatile uint32_t *)0x40024400))

#define GPIO_PORTE_IS_R         (*((volatile uint32_t *)0x40024404))

#define GPIO_PORTE_IBE_R        (*((volatile uint32_t *)0x40024408))

#define GPIO_PORTE_IEV_R        (*((volatile uint32_t *)0x4002440C))

#define GPIO_PORTE_IM_R         (*((volatile uint32_t *)0x40024410))

#define GPIO_PORTE_RIS_R        (*((volatile uint32_t *)0x40024414))

#define GPIO_PORTE_MIS_R        (*((volatile uint32_t *)0x40024418))

#define GPIO_PORTE_ICR_R        (*((volatile uint32_t *)0x4002441C))

#define GPIO_PORTE_AFSEL_R      (*((volatile uint32_t *)0x40024420))

#define GPIO_PORTE_DR2R_R       (*((volatile uint32_t *)0x40024500))

#define GPIO_PORTE_DR4R_R       (*((volatile uint32_t *)0x40024504))

#define GPIO_PORTE_DR8R_R       (*((volatile uint32_t *)0x40024508))

#define GPIO_PORTE_ODR_R        (*((volatile uint32_t *)0x4002450C))

#define GPIO_PORTE_PUR_R        (*((volatile uint32_t *)0x40024510))

#define GPIO_PORTE_PDR_R        (*((volatile uint32_t *)0x40024514))

#define GPIO_PORTE_SLR_R        (*((volatile uint32_t *)0x40024518))

#define GPIO_PORTE_DEN_R        (*((volatile uint32_t *)0x4002451C))

#define GPIO_PORTE_LOCK_R       (*((volatile uint32_t *)0x40024520))

#define GPIO_PORTE_CR_R         (*((volatile uint32_t *)0x40024524))

#define GPIO_PORTE_AMSEL_R      (*((volatile uint32_t *)0x40024528))

#define GPIO_PORTE_PCTL_R       (*((volatile uint32_t *)0x4002452C))

#define GPIO_PORTE_ADCCTL_R     (*((volatile uint32_t *)0x40024530))

#define GPIO_PORTE_DMACTL_R     (*((volatile uint32_t *)0x40024534))


//*****************************************************************************

//

// GPIO registers (PORTF)

//

//*****************************************************************************

#define GPIO_PORTF_DATA_BITS_R  ((volatile uint32_t *)0x40025000)

#define GPIO_PORTF_DATA_R       (*((volatile uint32_t *)0x400253FC))

#define GPIO_PORTF_DIR_R        (*((volatile uint32_t *)0x40025400))

#define GPIO_PORTF_IS_R         (*((volatile uint32_t *)0x40025404))

#define GPIO_PORTF_IBE_R        (*((volatile uint32_t *)0x40025408))

#define GPIO_PORTF_IEV_R        (*((volatile uint32_t *)0x4002540C))

#define GPIO_PORTF_IM_R         (*((volatile uint32_t *)0x40025410))

#define GPIO_PORTF_RIS_R        (*((volatile uint32_t *)0x40025414))

#define GPIO_PORTF_MIS_R        (*((volatile uint32_t *)0x40025418))

#define GPIO_PORTF_ICR_R        (*((volatile uint32_t *)0x4002541C))

#define GPIO_PORTF_AFSEL_R      (*((volatile uint32_t *)0x40025420))

#define GPIO_PORTF_DR2R_R       (*((volatile uint32_t *)0x40025500))

#define GPIO_PORTF_DR4R_R       (*((volatile uint32_t *)0x40025504))

#define GPIO_PORTF_DR8R_R       (*((volatile uint32_t *)0x40025508))

#define GPIO_PORTF_ODR_R        (*((volatile uint32_t *)0x4002550C))

#define GPIO_PORTF_PUR_R        (*((volatile uint32_t *)0x40025510))

#define GPIO_PORTF_PDR_R        (*((volatile uint32_t *)0x40025514))

#define GPIO_PORTF_SLR_R        (*((volatile uint32_t *)0x40025518))

#define GPIO_PORTF_DEN_R        (*((volatile uint32_t *)0x4002551C))

#define GPIO_PORTF_LOCK_R       (*((volatile uint32_t *)0x40025520))

#define GPIO_PORTF_CR_R         (*((volatile uint32_t *)0x40025524))

#define GPIO_PORTF_AMSEL_R      (*((volatile uint32_t *)0x40025528))

#define GPIO_PORTF_PCTL_R       (*((volatile uint32_t *)0x4002552C))

#define GPIO_PORTF_ADCCTL_R     (*((volatile uint32_t *)0x40025530))

#define GPIO_PORTF_DMACTL_R     (*((volatile uint32_t *)0x40025534))


//*****************************************************************************

//

// GPIO registers (PORTG)

//

//*****************************************************************************

#define GPIO_PORTG_DATA_BITS_R  ((volatile uint32_t *)0x40026000)

#define GPIO_PORTG_DATA_R       (*((volatile uint32_t *)0x400263FC))

#define GPIO_PORTG_DIR_R        (*((volatile uint32_t *)0x40026400))

#define GPIO_PORTG_IS_R         (*((volatile uint32_t *)0x40026404))

#define GPIO_PORTG_IBE_R        (*((volatile uint32_t *)0x40026408))

#define GPIO_PORTG_IEV_R        (*((volatile uint32_t *)0x4002640C))

#define GPIO_PORTG_IM_R         (*((volatile uint32_t *)0x40026410))

#define GPIO_PORTG_RIS_R        (*((volatile uint32_t *)0x40026414))

#define GPIO_PORTG_MIS_R        (*((volatile uint32_t *)0x40026418))

#define GPIO_PORTG_ICR_R        (*((volatile uint32_t *)0x4002641C))

#define GPIO_PORTG_AFSEL_R      (*((volatile uint32_t *)0x40026420))

#define GPIO_PORTG_DR2R_R       (*((volatile uint32_t *)0x40026500))

#define GPIO_PORTG_DR4R_R       (*((volatile uint32_t *)0x40026504))

#define GPIO_PORTG_DR8R_R       (*((volatile uint32_t *)0x40026508))

#define GPIO_PORTG_ODR_R        (*((volatile uint32_t *)0x4002650C))

#define GPIO_PORTG_PUR_R        (*((volatile uint32_t *)0x40026510))

#define GPIO_PORTG_PDR_R        (*((volatile uint32_t *)0x40026514))

#define GPIO_PORTG_SLR_R        (*((volatile uint32_t *)0x40026518))

#define GPIO_PORTG_DEN_R        (*((volatile uint32_t *)0x4002651C))

#define GPIO_PORTG_LOCK_R       (*((volatile uint32_t *)0x40026520))

#define GPIO_PORTG_CR_R         (*((volatile uint32_t *)0x40026524))

#define GPIO_PORTG_AMSEL_R      (*((volatile uint32_t *)0x40026528))

#define GPIO_PORTG_PCTL_R       (*((volatile uint32_t *)0x4002652C))

#define GPIO_PORTG_ADCCTL_R     (*((volatile uint32_t *)0x40026530))

#define GPIO_PORTG_DMACTL_R     (*((volatile uint32_t *)0x40026534))


//*****************************************************************************

//

// PWM registers (PWM0)

//

//*****************************************************************************

#define PWM0_CTL_R              (*((volatile uint32_t *)0x40028000))

#define PWM0_SYNC_R             (*((volatile uint32_t *)0x40028004))

#define PWM0_ENABLE_R           (*((volatile uint32_t *)0x40028008))

#define PWM0_INVERT_R           (*((volatile uint32_t *)0x4002800C))

#define PWM0_FAULT_R            (*((volatile uint32_t *)0x40028010))

#define PWM0_INTEN_R            (*((volatile uint32_t *)0x40028014))

#define PWM0_RIS_R              (*((volatile uint32_t *)0x40028018))

#define PWM0_ISC_R              (*((volatile uint32_t *)0x4002801C))

#define PWM0_STATUS_R           (*((volatile uint32_t *)0x40028020))

#define PWM0_FAULTVAL_R         (*((volatile uint32_t *)0x40028024))

#define PWM0_ENUPD_R            (*((volatile uint32_t *)0x40028028))

#define PWM0_0_CTL_R            (*((volatile uint32_t *)0x40028040))

#define PWM0_0_INTEN_R          (*((volatile uint32_t *)0x40028044))

#define PWM0_0_RIS_R            (*((volatile uint32_t *)0x40028048))

#define PWM0_0_ISC_R            (*((volatile uint32_t *)0x4002804C))

#define PWM0_0_LOAD_R           (*((volatile uint32_t *)0x40028050))

#define PWM0_0_COUNT_R          (*((volatile uint32_t *)0x40028054))

#define PWM0_0_CMPA_R           (*((volatile uint32_t *)0x40028058))

#define PWM0_0_CMPB_R           (*((volatile uint32_t *)0x4002805C))

#define PWM0_0_GENA_R           (*((volatile uint32_t *)0x40028060))

#define PWM0_0_GENB_R           (*((volatile uint32_t *)0x40028064))

#define PWM0_0_DBCTL_R          (*((volatile uint32_t *)0x40028068))

#define PWM0_0_DBRISE_R         (*((volatile uint32_t *)0x4002806C))

#define PWM0_0_DBFALL_R         (*((volatile uint32_t *)0x40028070))

#define PWM0_0_FLTSRC0_R        (*((volatile uint32_t *)0x40028074))

#define PWM0_0_FLTSRC1_R        (*((volatile uint32_t *)0x40028078))

#define PWM0_0_MINFLTPER_R      (*((volatile uint32_t *)0x4002807C))

#define PWM0_1_CTL_R            (*((volatile uint32_t *)0x40028080))

#define PWM0_1_INTEN_R          (*((volatile uint32_t *)0x40028084))

#define PWM0_1_RIS_R            (*((volatile uint32_t *)0x40028088))

#define PWM0_1_ISC_R            (*((volatile uint32_t *)0x4002808C))

#define PWM0_1_LOAD_R           (*((volatile uint32_t *)0x40028090))

#define PWM0_1_COUNT_R          (*((volatile uint32_t *)0x40028094))

#define PWM0_1_CMPA_R           (*((volatile uint32_t *)0x40028098))

#define PWM0_1_CMPB_R           (*((volatile uint32_t *)0x4002809C))

#define PWM0_1_GENA_R           (*((volatile uint32_t *)0x400280A0))

#define PWM0_1_GENB_R           (*((volatile uint32_t *)0x400280A4))

#define PWM0_1_DBCTL_R          (*((volatile uint32_t *)0x400280A8))

#define PWM0_1_DBRISE_R         (*((volatile uint32_t *)0x400280AC))

#define PWM0_1_DBFALL_R         (*((volatile uint32_t *)0x400280B0))

#define PWM0_1_FLTSRC0_R        (*((volatile uint32_t *)0x400280B4))

#define PWM0_1_FLTSRC1_R        (*((volatile uint32_t *)0x400280B8))

#define PWM0_1_MINFLTPER_R      (*((volatile uint32_t *)0x400280BC))

#define PWM0_2_CTL_R            (*((volatile uint32_t *)0x400280C0))

#define PWM0_2_INTEN_R          (*((volatile uint32_t *)0x400280C4))

#define PWM0_2_RIS_R            (*((volatile uint32_t *)0x400280C8))

#define PWM0_2_ISC_R            (*((volatile uint32_t *)0x400280CC))

#define PWM0_2_LOAD_R           (*((volatile uint32_t *)0x400280D0))

#define PWM0_2_COUNT_R          (*((volatile uint32_t *)0x400280D4))

#define PWM0_2_CMPA_R           (*((volatile uint32_t *)0x400280D8))

#define PWM0_2_CMPB_R           (*((volatile uint32_t *)0x400280DC))

#define PWM0_2_GENA_R           (*((volatile uint32_t *)0x400280E0))

#define PWM0_2_GENB_R           (*((volatile uint32_t *)0x400280E4))

#define PWM0_2_DBCTL_R          (*((volatile uint32_t *)0x400280E8))

#define PWM0_2_DBRISE_R         (*((volatile uint32_t *)0x400280EC))

#define PWM0_2_DBFALL_R         (*((volatile uint32_t *)0x400280F0))

#define PWM0_2_FLTSRC0_R        (*((volatile uint32_t *)0x400280F4))

#define PWM0_2_FLTSRC1_R        (*((volatile uint32_t *)0x400280F8))

#define PWM0_2_MINFLTPER_R      (*((volatile uint32_t *)0x400280FC))

#define PWM0_3_CTL_R            (*((volatile uint32_t *)0x40028100))

#define PWM0_3_INTEN_R          (*((volatile uint32_t *)0x40028104))

#define PWM0_3_RIS_R            (*((volatile uint32_t *)0x40028108))

#define PWM0_3_ISC_R            (*((volatile uint32_t *)0x4002810C))

#define PWM0_3_LOAD_R           (*((volatile uint32_t *)0x40028110))

#define PWM0_3_COUNT_R          (*((volatile uint32_t *)0x40028114))

#define PWM0_3_CMPA_R           (*((volatile uint32_t *)0x40028118))

#define PWM0_3_CMPB_R           (*((volatile uint32_t *)0x4002811C))

#define PWM0_3_GENA_R           (*((volatile uint32_t *)0x40028120))

#define PWM0_3_GENB_R           (*((volatile uint32_t *)0x40028124))

#define PWM0_3_DBCTL_R          (*((volatile uint32_t *)0x40028128))

#define PWM0_3_DBRISE_R         (*((volatile uint32_t *)0x4002812C))

#define PWM0_3_DBFALL_R         (*((volatile uint32_t *)0x40028130))

#define PWM0_3_FLTSRC0_R        (*((volatile uint32_t *)0x40028134))

#define PWM0_3_FLTSRC1_R        (*((volatile uint32_t *)0x40028138))

#define PWM0_3_MINFLTPER_R      (*((volatile uint32_t *)0x4002813C))

#define PWM0_0_FLTSEN_R         (*((volatile uint32_t *)0x40028800))

#define PWM0_0_FLTSTAT0_R       (*((volatile uint32_t *)0x40028804))

#define PWM0_0_FLTSTAT1_R       (*((volatile uint32_t *)0x40028808))

#define PWM0_1_FLTSEN_R         (*((volatile uint32_t *)0x40028880))

#define PWM0_1_FLTSTAT0_R       (*((volatile uint32_t *)0x40028884))

#define PWM0_1_FLTSTAT1_R       (*((volatile uint32_t *)0x40028888))

#define PWM0_2_FLTSEN_R         (*((volatile uint32_t *)0x40028900))

#define PWM0_2_FLTSTAT0_R       (*((volatile uint32_t *)0x40028904))

#define PWM0_2_FLTSTAT1_R       (*((volatile uint32_t *)0x40028908))

#define PWM0_3_FLTSEN_R         (*((volatile uint32_t *)0x40028980))

#define PWM0_3_FLTSTAT0_R       (*((volatile uint32_t *)0x40028984))

#define PWM0_3_FLTSTAT1_R       (*((volatile uint32_t *)0x40028988))

#define PWM0_PP_R               (*((volatile uint32_t *)0x40028FC0))


//*****************************************************************************

//

// PWM registers (PWM1)

//

//*****************************************************************************

#define PWM1_CTL_R              (*((volatile uint32_t *)0x40029000))

#define PWM1_SYNC_R             (*((volatile uint32_t *)0x40029004))

#define PWM1_ENABLE_R           (*((volatile uint32_t *)0x40029008))

#define PWM1_INVERT_R           (*((volatile uint32_t *)0x4002900C))

#define PWM1_FAULT_R            (*((volatile uint32_t *)0x40029010))

#define PWM1_INTEN_R            (*((volatile uint32_t *)0x40029014))

#define PWM1_RIS_R              (*((volatile uint32_t *)0x40029018))

#define PWM1_ISC_R              (*((volatile uint32_t *)0x4002901C))

#define PWM1_STATUS_R           (*((volatile uint32_t *)0x40029020))

#define PWM1_FAULTVAL_R         (*((volatile uint32_t *)0x40029024))

#define PWM1_ENUPD_R            (*((volatile uint32_t *)0x40029028))

#define PWM1_0_CTL_R            (*((volatile uint32_t *)0x40029040))

#define PWM1_0_INTEN_R          (*((volatile uint32_t *)0x40029044))

#define PWM1_0_RIS_R            (*((volatile uint32_t *)0x40029048))

#define PWM1_0_ISC_R            (*((volatile uint32_t *)0x4002904C))

#define PWM1_0_LOAD_R           (*((volatile uint32_t *)0x40029050))

#define PWM1_0_COUNT_R          (*((volatile uint32_t *)0x40029054))

#define PWM1_0_CMPA_R           (*((volatile uint32_t *)0x40029058))

#define PWM1_0_CMPB_R           (*((volatile uint32_t *)0x4002905C))

#define PWM1_0_GENA_R           (*((volatile uint32_t *)0x40029060))

#define PWM1_0_GENB_R           (*((volatile uint32_t *)0x40029064))

#define PWM1_0_DBCTL_R          (*((volatile uint32_t *)0x40029068))

#define PWM1_0_DBRISE_R         (*((volatile uint32_t *)0x4002906C))

#define PWM1_0_DBFALL_R         (*((volatile uint32_t *)0x40029070))

#define PWM1_0_FLTSRC0_R        (*((volatile uint32_t *)0x40029074))

#define PWM1_0_FLTSRC1_R        (*((volatile uint32_t *)0x40029078))

#define PWM1_0_MINFLTPER_R      (*((volatile uint32_t *)0x4002907C))

#define PWM1_1_CTL_R            (*((volatile uint32_t *)0x40029080))

#define PWM1_1_INTEN_R          (*((volatile uint32_t *)0x40029084))

#define PWM1_1_RIS_R            (*((volatile uint32_t *)0x40029088))

#define PWM1_1_ISC_R            (*((volatile uint32_t *)0x4002908C))

#define PWM1_1_LOAD_R           (*((volatile uint32_t *)0x40029090))

#define PWM1_1_COUNT_R          (*((volatile uint32_t *)0x40029094))

#define PWM1_1_CMPA_R           (*((volatile uint32_t *)0x40029098))

#define PWM1_1_CMPB_R           (*((volatile uint32_t *)0x4002909C))

#define PWM1_1_GENA_R           (*((volatile uint32_t *)0x400290A0))

#define PWM1_1_GENB_R           (*((volatile uint32_t *)0x400290A4))

#define PWM1_1_DBCTL_R          (*((volatile uint32_t *)0x400290A8))

#define PWM1_1_DBRISE_R         (*((volatile uint32_t *)0x400290AC))

#define PWM1_1_DBFALL_R         (*((volatile uint32_t *)0x400290B0))

#define PWM1_1_FLTSRC0_R        (*((volatile uint32_t *)0x400290B4))

#define PWM1_1_FLTSRC1_R        (*((volatile uint32_t *)0x400290B8))

#define PWM1_1_MINFLTPER_R      (*((volatile uint32_t *)0x400290BC))

#define PWM1_2_CTL_R            (*((volatile uint32_t *)0x400290C0))

#define PWM1_2_INTEN_R          (*((volatile uint32_t *)0x400290C4))

#define PWM1_2_RIS_R            (*((volatile uint32_t *)0x400290C8))

#define PWM1_2_ISC_R            (*((volatile uint32_t *)0x400290CC))

#define PWM1_2_LOAD_R           (*((volatile uint32_t *)0x400290D0))

#define PWM1_2_COUNT_R          (*((volatile uint32_t *)0x400290D4))

#define PWM1_2_CMPA_R           (*((volatile uint32_t *)0x400290D8))

#define PWM1_2_CMPB_R           (*((volatile uint32_t *)0x400290DC))

#define PWM1_2_GENA_R           (*((volatile uint32_t *)0x400290E0))

#define PWM1_2_GENB_R           (*((volatile uint32_t *)0x400290E4))

#define PWM1_2_DBCTL_R          (*((volatile uint32_t *)0x400290E8))

#define PWM1_2_DBRISE_R         (*((volatile uint32_t *)0x400290EC))

#define PWM1_2_DBFALL_R         (*((volatile uint32_t *)0x400290F0))

#define PWM1_2_FLTSRC0_R        (*((volatile uint32_t *)0x400290F4))

#define PWM1_2_FLTSRC1_R        (*((volatile uint32_t *)0x400290F8))

#define PWM1_2_MINFLTPER_R      (*((volatile uint32_t *)0x400290FC))

#define PWM1_3_CTL_R            (*((volatile uint32_t *)0x40029100))

#define PWM1_3_INTEN_R          (*((volatile uint32_t *)0x40029104))

#define PWM1_3_RIS_R            (*((volatile uint32_t *)0x40029108))

#define PWM1_3_ISC_R            (*((volatile uint32_t *)0x4002910C))

#define PWM1_3_LOAD_R           (*((volatile uint32_t *)0x40029110))

#define PWM1_3_COUNT_R          (*((volatile uint32_t *)0x40029114))

#define PWM1_3_CMPA_R           (*((volatile uint32_t *)0x40029118))

#define PWM1_3_CMPB_R           (*((volatile uint32_t *)0x4002911C))

#define PWM1_3_GENA_R           (*((volatile uint32_t *)0x40029120))

#define PWM1_3_GENB_R           (*((volatile uint32_t *)0x40029124))

#define PWM1_3_DBCTL_R          (*((volatile uint32_t *)0x40029128))

#define PWM1_3_DBRISE_R         (*((volatile uint32_t *)0x4002912C))

#define PWM1_3_DBFALL_R         (*((volatile uint32_t *)0x40029130))

#define PWM1_3_FLTSRC0_R        (*((volatile uint32_t *)0x40029134))

#define PWM1_3_FLTSRC1_R        (*((volatile uint32_t *)0x40029138))

#define PWM1_3_MINFLTPER_R      (*((volatile uint32_t *)0x4002913C))

#define PWM1_0_FLTSEN_R         (*((volatile uint32_t *)0x40029800))

#define PWM1_0_FLTSTAT0_R       (*((volatile uint32_t *)0x40029804))

#define PWM1_0_FLTSTAT1_R       (*((volatile uint32_t *)0x40029808))

#define PWM1_1_FLTSEN_R         (*((volatile uint32_t *)0x40029880))

#define PWM1_1_FLTSTAT0_R       (*((volatile uint32_t *)0x40029884))

#define PWM1_1_FLTSTAT1_R       (*((volatile uint32_t *)0x40029888))

#define PWM1_2_FLTSEN_R         (*((volatile uint32_t *)0x40029900))

#define PWM1_2_FLTSTAT0_R       (*((volatile uint32_t *)0x40029904))

#define PWM1_2_FLTSTAT1_R       (*((volatile uint32_t *)0x40029908))

#define PWM1_3_FLTSEN_R         (*((volatile uint32_t *)0x40029980))

#define PWM1_3_FLTSTAT0_R       (*((volatile uint32_t *)0x40029984))

#define PWM1_3_FLTSTAT1_R       (*((volatile uint32_t *)0x40029988))

#define PWM1_PP_R               (*((volatile uint32_t *)0x40029FC0))


//*****************************************************************************

//

// QEI registers (QEI0)

//

//*****************************************************************************

#define QEI0_CTL_R              (*((volatile uint32_t *)0x4002C000))

#define QEI0_STAT_R             (*((volatile uint32_t *)0x4002C004))

#define QEI0_POS_R              (*((volatile uint32_t *)0x4002C008))

#define QEI0_MAXPOS_R           (*((volatile uint32_t *)0x4002C00C))

#define QEI0_LOAD_R             (*((volatile uint32_t *)0x4002C010))

#define QEI0_TIME_R             (*((volatile uint32_t *)0x4002C014))

#define QEI0_COUNT_R            (*((volatile uint32_t *)0x4002C018))

#define QEI0_SPEED_R            (*((volatile uint32_t *)0x4002C01C))

#define QEI0_INTEN_R            (*((volatile uint32_t *)0x4002C020))

#define QEI0_RIS_R              (*((volatile uint32_t *)0x4002C024))

#define QEI0_ISC_R              (*((volatile uint32_t *)0x4002C028))


//*****************************************************************************

//

// QEI registers (QEI1)

//

//*****************************************************************************

#define QEI1_CTL_R              (*((volatile uint32_t *)0x4002D000))

#define QEI1_STAT_R             (*((volatile uint32_t *)0x4002D004))

#define QEI1_POS_R              (*((volatile uint32_t *)0x4002D008))

#define QEI1_MAXPOS_R           (*((volatile uint32_t *)0x4002D00C))

#define QEI1_LOAD_R             (*((volatile uint32_t *)0x4002D010))

#define QEI1_TIME_R             (*((volatile uint32_t *)0x4002D014))

#define QEI1_COUNT_R            (*((volatile uint32_t *)0x4002D018))

#define QEI1_SPEED_R            (*((volatile uint32_t *)0x4002D01C))

#define QEI1_INTEN_R            (*((volatile uint32_t *)0x4002D020))

#define QEI1_RIS_R              (*((volatile uint32_t *)0x4002D024))

#define QEI1_ISC_R              (*((volatile uint32_t *)0x4002D028))


//*****************************************************************************

//

// Timer registers (TIMER0)

//

//*****************************************************************************

#define TIMER0_CFG_R            (*((volatile uint32_t *)0x40030000))

#define TIMER0_TAMR_R           (*((volatile uint32_t *)0x40030004))

#define TIMER0_TBMR_R           (*((volatile uint32_t *)0x40030008))

#define TIMER0_CTL_R            (*((volatile uint32_t *)0x4003000C))

#define TIMER0_SYNC_R           (*((volatile uint32_t *)0x40030010))

#define TIMER0_IMR_R            (*((volatile uint32_t *)0x40030018))

#define TIMER0_RIS_R            (*((volatile uint32_t *)0x4003001C))

#define TIMER0_MIS_R            (*((volatile uint32_t *)0x40030020))

#define TIMER0_ICR_R            (*((volatile uint32_t *)0x40030024))

#define TIMER0_TAILR_R          (*((volatile uint32_t *)0x40030028))

#define TIMER0_TBILR_R          (*((volatile uint32_t *)0x4003002C))

#define TIMER0_TAMATCHR_R       (*((volatile uint32_t *)0x40030030))

#define TIMER0_TBMATCHR_R       (*((volatile uint32_t *)0x40030034))

#define TIMER0_TAPR_R           (*((volatile uint32_t *)0x40030038))

#define TIMER0_TBPR_R           (*((volatile uint32_t *)0x4003003C))

#define TIMER0_TAPMR_R          (*((volatile uint32_t *)0x40030040))

#define TIMER0_TBPMR_R          (*((volatile uint32_t *)0x40030044))

#define TIMER0_TAR_R            (*((volatile uint32_t *)0x40030048))

#define TIMER0_TBR_R            (*((volatile uint32_t *)0x4003004C))

#define TIMER0_TAV_R            (*((volatile uint32_t *)0x40030050))

#define TIMER0_TBV_R            (*((volatile uint32_t *)0x40030054))

#define TIMER0_RTCPD_R          (*((volatile uint32_t *)0x40030058))

#define TIMER0_TAPS_R           (*((volatile uint32_t *)0x4003005C))

#define TIMER0_TBPS_R           (*((volatile uint32_t *)0x40030060))

#define TIMER0_TAPV_R           (*((volatile uint32_t *)0x40030064))

#define TIMER0_TBPV_R           (*((volatile uint32_t *)0x40030068))

#define TIMER0_PP_R             (*((volatile uint32_t *)0x40030FC0))


//*****************************************************************************

//

// Timer registers (TIMER1)

//

//*****************************************************************************

#define TIMER1_CFG_R            (*((volatile uint32_t *)0x40031000))

#define TIMER1_TAMR_R           (*((volatile uint32_t *)0x40031004))

#define TIMER1_TBMR_R           (*((volatile uint32_t *)0x40031008))

#define TIMER1_CTL_R            (*((volatile uint32_t *)0x4003100C))

#define TIMER1_SYNC_R           (*((volatile uint32_t *)0x40031010))

#define TIMER1_IMR_R            (*((volatile uint32_t *)0x40031018))

#define TIMER1_RIS_R            (*((volatile uint32_t *)0x4003101C))

#define TIMER1_MIS_R            (*((volatile uint32_t *)0x40031020))

#define TIMER1_ICR_R            (*((volatile uint32_t *)0x40031024))

#define TIMER1_TAILR_R          (*((volatile uint32_t *)0x40031028))

#define TIMER1_TBILR_R          (*((volatile uint32_t *)0x4003102C))

#define TIMER1_TAMATCHR_R       (*((volatile uint32_t *)0x40031030))

#define TIMER1_TBMATCHR_R       (*((volatile uint32_t *)0x40031034))

#define TIMER1_TAPR_R           (*((volatile uint32_t *)0x40031038))

#define TIMER1_TBPR_R           (*((volatile uint32_t *)0x4003103C))

#define TIMER1_TAPMR_R          (*((volatile uint32_t *)0x40031040))

#define TIMER1_TBPMR_R          (*((volatile uint32_t *)0x40031044))

#define TIMER1_TAR_R            (*((volatile uint32_t *)0x40031048))

#define TIMER1_TBR_R            (*((volatile uint32_t *)0x4003104C))

#define TIMER1_TAV_R            (*((volatile uint32_t *)0x40031050))

#define TIMER1_TBV_R            (*((volatile uint32_t *)0x40031054))

#define TIMER1_RTCPD_R          (*((volatile uint32_t *)0x40031058))

#define TIMER1_TAPS_R           (*((volatile uint32_t *)0x4003105C))

#define TIMER1_TBPS_R           (*((volatile uint32_t *)0x40031060))

#define TIMER1_TAPV_R           (*((volatile uint32_t *)0x40031064))

#define TIMER1_TBPV_R           (*((volatile uint32_t *)0x40031068))

#define TIMER1_PP_R             (*((volatile uint32_t *)0x40031FC0))


//*****************************************************************************

//

// Timer registers (TIMER2)

//

//*****************************************************************************

#define TIMER2_CFG_R            (*((volatile uint32_t *)0x40032000))

#define TIMER2_TAMR_R           (*((volatile uint32_t *)0x40032004))

#define TIMER2_TBMR_R           (*((volatile uint32_t *)0x40032008))

#define TIMER2_CTL_R            (*((volatile uint32_t *)0x4003200C))

#define TIMER2_SYNC_R           (*((volatile uint32_t *)0x40032010))

#define TIMER2_IMR_R            (*((volatile uint32_t *)0x40032018))

#define TIMER2_RIS_R            (*((volatile uint32_t *)0x4003201C))

#define TIMER2_MIS_R            (*((volatile uint32_t *)0x40032020))

#define TIMER2_ICR_R            (*((volatile uint32_t *)0x40032024))

#define TIMER2_TAILR_R          (*((volatile uint32_t *)0x40032028))

#define TIMER2_TBILR_R          (*((volatile uint32_t *)0x4003202C))

#define TIMER2_TAMATCHR_R       (*((volatile uint32_t *)0x40032030))

#define TIMER2_TBMATCHR_R       (*((volatile uint32_t *)0x40032034))

#define TIMER2_TAPR_R           (*((volatile uint32_t *)0x40032038))

#define TIMER2_TBPR_R           (*((volatile uint32_t *)0x4003203C))

#define TIMER2_TAPMR_R          (*((volatile uint32_t *)0x40032040))

#define TIMER2_TBPMR_R          (*((volatile uint32_t *)0x40032044))

#define TIMER2_TAR_R            (*((volatile uint32_t *)0x40032048))

#define TIMER2_TBR_R            (*((volatile uint32_t *)0x4003204C))

#define TIMER2_TAV_R            (*((volatile uint32_t *)0x40032050))

#define TIMER2_TBV_R            (*((volatile uint32_t *)0x40032054))

#define TIMER2_RTCPD_R          (*((volatile uint32_t *)0x40032058))

#define TIMER2_TAPS_R           (*((volatile uint32_t *)0x4003205C))

#define TIMER2_TBPS_R           (*((volatile uint32_t *)0x40032060))

#define TIMER2_TAPV_R           (*((volatile uint32_t *)0x40032064))

#define TIMER2_TBPV_R           (*((volatile uint32_t *)0x40032068))

#define TIMER2_PP_R             (*((volatile uint32_t *)0x40032FC0))


//*****************************************************************************

//

// Timer registers (TIMER3)

//

//*****************************************************************************

#define TIMER3_CFG_R            (*((volatile uint32_t *)0x40033000))

#define TIMER3_TAMR_R           (*((volatile uint32_t *)0x40033004))

#define TIMER3_TBMR_R           (*((volatile uint32_t *)0x40033008))

#define TIMER3_CTL_R            (*((volatile uint32_t *)0x4003300C))

#define TIMER3_SYNC_R           (*((volatile uint32_t *)0x40033010))

#define TIMER3_IMR_R            (*((volatile uint32_t *)0x40033018))

#define TIMER3_RIS_R            (*((volatile uint32_t *)0x4003301C))

#define TIMER3_MIS_R            (*((volatile uint32_t *)0x40033020))

#define TIMER3_ICR_R            (*((volatile uint32_t *)0x40033024))

#define TIMER3_TAILR_R          (*((volatile uint32_t *)0x40033028))

#define TIMER3_TBILR_R          (*((volatile uint32_t *)0x4003302C))

#define TIMER3_TAMATCHR_R       (*((volatile uint32_t *)0x40033030))

#define TIMER3_TBMATCHR_R       (*((volatile uint32_t *)0x40033034))

#define TIMER3_TAPR_R           (*((volatile uint32_t *)0x40033038))

#define TIMER3_TBPR_R           (*((volatile uint32_t *)0x4003303C))

#define TIMER3_TAPMR_R          (*((volatile uint32_t *)0x40033040))

#define TIMER3_TBPMR_R          (*((volatile uint32_t *)0x40033044))

#define TIMER3_TAR_R            (*((volatile uint32_t *)0x40033048))

#define TIMER3_TBR_R            (*((volatile uint32_t *)0x4003304C))

#define TIMER3_TAV_R            (*((volatile uint32_t *)0x40033050))

#define TIMER3_TBV_R            (*((volatile uint32_t *)0x40033054))

#define TIMER3_RTCPD_R          (*((volatile uint32_t *)0x40033058))

#define TIMER3_TAPS_R           (*((volatile uint32_t *)0x4003305C))

#define TIMER3_TBPS_R           (*((volatile uint32_t *)0x40033060))

#define TIMER3_TAPV_R           (*((volatile uint32_t *)0x40033064))

#define TIMER3_TBPV_R           (*((volatile uint32_t *)0x40033068))

#define TIMER3_PP_R             (*((volatile uint32_t *)0x40033FC0))


//*****************************************************************************

//

// Timer registers (TIMER4)

//

//*****************************************************************************

#define TIMER4_CFG_R            (*((volatile uint32_t *)0x40034000))

#define TIMER4_TAMR_R           (*((volatile uint32_t *)0x40034004))

#define TIMER4_TBMR_R           (*((volatile uint32_t *)0x40034008))

#define TIMER4_CTL_R            (*((volatile uint32_t *)0x4003400C))

#define TIMER4_SYNC_R           (*((volatile uint32_t *)0x40034010))

#define TIMER4_IMR_R            (*((volatile uint32_t *)0x40034018))

#define TIMER4_RIS_R            (*((volatile uint32_t *)0x4003401C))

#define TIMER4_MIS_R            (*((volatile uint32_t *)0x40034020))

#define TIMER4_ICR_R            (*((volatile uint32_t *)0x40034024))

#define TIMER4_TAILR_R          (*((volatile uint32_t *)0x40034028))

#define TIMER4_TBILR_R          (*((volatile uint32_t *)0x4003402C))

#define TIMER4_TAMATCHR_R       (*((volatile uint32_t *)0x40034030))

#define TIMER4_TBMATCHR_R       (*((volatile uint32_t *)0x40034034))

#define TIMER4_TAPR_R           (*((volatile uint32_t *)0x40034038))

#define TIMER4_TBPR_R           (*((volatile uint32_t *)0x4003403C))

#define TIMER4_TAPMR_R          (*((volatile uint32_t *)0x40034040))

#define TIMER4_TBPMR_R          (*((volatile uint32_t *)0x40034044))

#define TIMER4_TAR_R            (*((volatile uint32_t *)0x40034048))

#define TIMER4_TBR_R            (*((volatile uint32_t *)0x4003404C))

#define TIMER4_TAV_R            (*((volatile uint32_t *)0x40034050))

#define TIMER4_TBV_R            (*((volatile uint32_t *)0x40034054))

#define TIMER4_RTCPD_R          (*((volatile uint32_t *)0x40034058))

#define TIMER4_TAPS_R           (*((volatile uint32_t *)0x4003405C))

#define TIMER4_TBPS_R           (*((volatile uint32_t *)0x40034060))

#define TIMER4_TAPV_R           (*((volatile uint32_t *)0x40034064))

#define TIMER4_TBPV_R           (*((volatile uint32_t *)0x40034068))

#define TIMER4_PP_R             (*((volatile uint32_t *)0x40034FC0))


//*****************************************************************************

//

// Timer registers (TIMER5)

//

//*****************************************************************************

#define TIMER5_CFG_R            (*((volatile uint32_t *)0x40035000))

#define TIMER5_TAMR_R           (*((volatile uint32_t *)0x40035004))

#define TIMER5_TBMR_R           (*((volatile uint32_t *)0x40035008))

#define TIMER5_CTL_R            (*((volatile uint32_t *)0x4003500C))

#define TIMER5_SYNC_R           (*((volatile uint32_t *)0x40035010))

#define TIMER5_IMR_R            (*((volatile uint32_t *)0x40035018))

#define TIMER5_RIS_R            (*((volatile uint32_t *)0x4003501C))

#define TIMER5_MIS_R            (*((volatile uint32_t *)0x40035020))

#define TIMER5_ICR_R            (*((volatile uint32_t *)0x40035024))

#define TIMER5_TAILR_R          (*((volatile uint32_t *)0x40035028))

#define TIMER5_TBILR_R          (*((volatile uint32_t *)0x4003502C))

#define TIMER5_TAMATCHR_R       (*((volatile uint32_t *)0x40035030))

#define TIMER5_TBMATCHR_R       (*((volatile uint32_t *)0x40035034))

#define TIMER5_TAPR_R           (*((volatile uint32_t *)0x40035038))

#define TIMER5_TBPR_R           (*((volatile uint32_t *)0x4003503C))

#define TIMER5_TAPMR_R          (*((volatile uint32_t *)0x40035040))

#define TIMER5_TBPMR_R          (*((volatile uint32_t *)0x40035044))

#define TIMER5_TAR_R            (*((volatile uint32_t *)0x40035048))

#define TIMER5_TBR_R            (*((volatile uint32_t *)0x4003504C))

#define TIMER5_TAV_R            (*((volatile uint32_t *)0x40035050))

#define TIMER5_TBV_R            (*((volatile uint32_t *)0x40035054))

#define TIMER5_RTCPD_R          (*((volatile uint32_t *)0x40035058))

#define TIMER5_TAPS_R           (*((volatile uint32_t *)0x4003505C))

#define TIMER5_TBPS_R           (*((volatile uint32_t *)0x40035060))

#define TIMER5_TAPV_R           (*((volatile uint32_t *)0x40035064))

#define TIMER5_TBPV_R           (*((volatile uint32_t *)0x40035068))

#define TIMER5_PP_R             (*((volatile uint32_t *)0x40035FC0))


//*****************************************************************************

//

// Timer registers (WTIMER0)

//

//*****************************************************************************

#define WTIMER0_CFG_R           (*((volatile uint32_t *)0x40036000))

#define WTIMER0_TAMR_R          (*((volatile uint32_t *)0x40036004))

#define WTIMER0_TBMR_R          (*((volatile uint32_t *)0x40036008))

#define WTIMER0_CTL_R           (*((volatile uint32_t *)0x4003600C))

#define WTIMER0_SYNC_R          (*((volatile uint32_t *)0x40036010))

#define WTIMER0_IMR_R           (*((volatile uint32_t *)0x40036018))

#define WTIMER0_RIS_R           (*((volatile uint32_t *)0x4003601C))

#define WTIMER0_MIS_R           (*((volatile uint32_t *)0x40036020))

#define WTIMER0_ICR_R           (*((volatile uint32_t *)0x40036024))

#define WTIMER0_TAILR_R         (*((volatile uint32_t *)0x40036028))

#define WTIMER0_TBILR_R         (*((volatile uint32_t *)0x4003602C))

#define WTIMER0_TAMATCHR_R      (*((volatile uint32_t *)0x40036030))

#define WTIMER0_TBMATCHR_R      (*((volatile uint32_t *)0x40036034))

#define WTIMER0_TAPR_R          (*((volatile uint32_t *)0x40036038))

#define WTIMER0_TBPR_R          (*((volatile uint32_t *)0x4003603C))

#define WTIMER0_TAPMR_R         (*((volatile uint32_t *)0x40036040))

#define WTIMER0_TBPMR_R         (*((volatile uint32_t *)0x40036044))

#define WTIMER0_TAR_R           (*((volatile uint32_t *)0x40036048))

#define WTIMER0_TBR_R           (*((volatile uint32_t *)0x4003604C))

#define WTIMER0_TAV_R           (*((volatile uint32_t *)0x40036050))

#define WTIMER0_TBV_R           (*((volatile uint32_t *)0x40036054))

#define WTIMER0_RTCPD_R         (*((volatile uint32_t *)0x40036058))

#define WTIMER0_TAPS_R          (*((volatile uint32_t *)0x4003605C))

#define WTIMER0_TBPS_R          (*((volatile uint32_t *)0x40036060))

#define WTIMER0_TAPV_R          (*((volatile uint32_t *)0x40036064))

#define WTIMER0_TBPV_R          (*((volatile uint32_t *)0x40036068))

#define WTIMER0_PP_R            (*((volatile uint32_t *)0x40036FC0))


//*****************************************************************************

//

// Timer registers (WTIMER1)

//

//*****************************************************************************

#define WTIMER1_CFG_R           (*((volatile uint32_t *)0x40037000))

#define WTIMER1_TAMR_R          (*((volatile uint32_t *)0x40037004))

#define WTIMER1_TBMR_R          (*((volatile uint32_t *)0x40037008))

#define WTIMER1_CTL_R           (*((volatile uint32_t *)0x4003700C))

#define WTIMER1_SYNC_R          (*((volatile uint32_t *)0x40037010))

#define WTIMER1_IMR_R           (*((volatile uint32_t *)0x40037018))

#define WTIMER1_RIS_R           (*((volatile uint32_t *)0x4003701C))

#define WTIMER1_MIS_R           (*((volatile uint32_t *)0x40037020))

#define WTIMER1_ICR_R           (*((volatile uint32_t *)0x40037024))

#define WTIMER1_TAILR_R         (*((volatile uint32_t *)0x40037028))

#define WTIMER1_TBILR_R         (*((volatile uint32_t *)0x4003702C))

#define WTIMER1_TAMATCHR_R      (*((volatile uint32_t *)0x40037030))

#define WTIMER1_TBMATCHR_R      (*((volatile uint32_t *)0x40037034))

#define WTIMER1_TAPR_R          (*((volatile uint32_t *)0x40037038))

#define WTIMER1_TBPR_R          (*((volatile uint32_t *)0x4003703C))

#define WTIMER1_TAPMR_R         (*((volatile uint32_t *)0x40037040))

#define WTIMER1_TBPMR_R         (*((volatile uint32_t *)0x40037044))

#define WTIMER1_TAR_R           (*((volatile uint32_t *)0x40037048))

#define WTIMER1_TBR_R           (*((volatile uint32_t *)0x4003704C))

#define WTIMER1_TAV_R           (*((volatile uint32_t *)0x40037050))

#define WTIMER1_TBV_R           (*((volatile uint32_t *)0x40037054))

#define WTIMER1_RTCPD_R         (*((volatile uint32_t *)0x40037058))

#define WTIMER1_TAPS_R          (*((volatile uint32_t *)0x4003705C))

#define WTIMER1_TBPS_R          (*((volatile uint32_t *)0x40037060))

#define WTIMER1_TAPV_R          (*((volatile uint32_t *)0x40037064))

#define WTIMER1_TBPV_R          (*((volatile uint32_t *)0x40037068))

#define WTIMER1_PP_R            (*((volatile uint32_t *)0x40037FC0))


//*****************************************************************************

//

// ADC registers (ADC0)

//

//*****************************************************************************

#define ADC0_ACTSS_R            (*((volatile uint32_t *)0x40038000))

#define ADC0_RIS_R              (*((volatile uint32_t *)0x40038004))

#define ADC0_IM_R               (*((volatile uint32_t *)0x40038008))

#define ADC0_ISC_R              (*((volatile uint32_t *)0x4003800C))

#define ADC0_OSTAT_R            (*((volatile uint32_t *)0x40038010))

#define ADC0_EMUX_R             (*((volatile uint32_t *)0x40038014))

#define ADC0_USTAT_R            (*((volatile uint32_t *)0x40038018))

#define ADC0_TSSEL_R            (*((volatile uint32_t *)0x4003801C))

#define ADC0_SSPRI_R            (*((volatile uint32_t *)0x40038020))

#define ADC0_SPC_R              (*((volatile uint32_t *)0x40038024))

#define ADC0_PSSI_R             (*((volatile uint32_t *)0x40038028))

#define ADC0_SAC_R              (*((volatile uint32_t *)0x40038030))

#define ADC0_DCISC_R            (*((volatile uint32_t *)0x40038034))

#define ADC0_CTL_R              (*((volatile uint32_t *)0x40038038))

#define ADC0_SSMUX0_R           (*((volatile uint32_t *)0x40038040))

#define ADC0_SSCTL0_R           (*((volatile uint32_t *)0x40038044))

#define ADC0_SSFIFO0_R          (*((volatile uint32_t *)0x40038048))

#define ADC0_SSFSTAT0_R         (*((volatile uint32_t *)0x4003804C))

#define ADC0_SSOP0_R            (*((volatile uint32_t *)0x40038050))

#define ADC0_SSDC0_R            (*((volatile uint32_t *)0x40038054))

#define ADC0_SSMUX1_R           (*((volatile uint32_t *)0x40038060))

#define ADC0_SSCTL1_R           (*((volatile uint32_t *)0x40038064))

#define ADC0_SSFIFO1_R          (*((volatile uint32_t *)0x40038068))

#define ADC0_SSFSTAT1_R         (*((volatile uint32_t *)0x4003806C))

#define ADC0_SSOP1_R            (*((volatile uint32_t *)0x40038070))

#define ADC0_SSDC1_R            (*((volatile uint32_t *)0x40038074))

#define ADC0_SSMUX2_R           (*((volatile uint32_t *)0x40038080))

#define ADC0_SSCTL2_R           (*((volatile uint32_t *)0x40038084))

#define ADC0_SSFIFO2_R          (*((volatile uint32_t *)0x40038088))

#define ADC0_SSFSTAT2_R         (*((volatile uint32_t *)0x4003808C))

#define ADC0_SSOP2_R            (*((volatile uint32_t *)0x40038090))

#define ADC0_SSDC2_R            (*((volatile uint32_t *)0x40038094))

#define ADC0_SSMUX3_R           (*((volatile uint32_t *)0x400380A0))

#define ADC0_SSCTL3_R           (*((volatile uint32_t *)0x400380A4))

#define ADC0_SSFIFO3_R          (*((volatile uint32_t *)0x400380A8))

#define ADC0_SSFSTAT3_R         (*((volatile uint32_t *)0x400380AC))

#define ADC0_SSOP3_R            (*((volatile uint32_t *)0x400380B0))

#define ADC0_SSDC3_R            (*((volatile uint32_t *)0x400380B4))

#define ADC0_DCRIC_R            (*((volatile uint32_t *)0x40038D00))

#define ADC0_DCCTL0_R           (*((volatile uint32_t *)0x40038E00))

#define ADC0_DCCTL1_R           (*((volatile uint32_t *)0x40038E04))

#define ADC0_DCCTL2_R           (*((volatile uint32_t *)0x40038E08))

#define ADC0_DCCTL3_R           (*((volatile uint32_t *)0x40038E0C))

#define ADC0_DCCTL4_R           (*((volatile uint32_t *)0x40038E10))

#define ADC0_DCCTL5_R           (*((volatile uint32_t *)0x40038E14))

#define ADC0_DCCTL6_R           (*((volatile uint32_t *)0x40038E18))

#define ADC0_DCCTL7_R           (*((volatile uint32_t *)0x40038E1C))

#define ADC0_DCCMP0_R           (*((volatile uint32_t *)0x40038E40))

#define ADC0_DCCMP1_R           (*((volatile uint32_t *)0x40038E44))

#define ADC0_DCCMP2_R           (*((volatile uint32_t *)0x40038E48))

#define ADC0_DCCMP3_R           (*((volatile uint32_t *)0x40038E4C))

#define ADC0_DCCMP4_R           (*((volatile uint32_t *)0x40038E50))

#define ADC0_DCCMP5_R           (*((volatile uint32_t *)0x40038E54))

#define ADC0_DCCMP6_R           (*((volatile uint32_t *)0x40038E58))

#define ADC0_DCCMP7_R           (*((volatile uint32_t *)0x40038E5C))

#define ADC0_PP_R               (*((volatile uint32_t *)0x40038FC0))

#define ADC0_PC_R               (*((volatile uint32_t *)0x40038FC4))

#define ADC0_CC_R               (*((volatile uint32_t *)0x40038FC8))


//*****************************************************************************

//

// ADC registers (ADC1)

//

//*****************************************************************************

#define ADC1_ACTSS_R            (*((volatile uint32_t *)0x40039000))

#define ADC1_RIS_R              (*((volatile uint32_t *)0x40039004))

#define ADC1_IM_R               (*((volatile uint32_t *)0x40039008))

#define ADC1_ISC_R              (*((volatile uint32_t *)0x4003900C))

#define ADC1_OSTAT_R            (*((volatile uint32_t *)0x40039010))

#define ADC1_EMUX_R             (*((volatile uint32_t *)0x40039014))

#define ADC1_USTAT_R            (*((volatile uint32_t *)0x40039018))

#define ADC1_TSSEL_R            (*((volatile uint32_t *)0x4003901C))

#define ADC1_SSPRI_R            (*((volatile uint32_t *)0x40039020))

#define ADC1_SPC_R              (*((volatile uint32_t *)0x40039024))

#define ADC1_PSSI_R             (*((volatile uint32_t *)0x40039028))

#define ADC1_SAC_R              (*((volatile uint32_t *)0x40039030))

#define ADC1_DCISC_R            (*((volatile uint32_t *)0x40039034))

#define ADC1_CTL_R              (*((volatile uint32_t *)0x40039038))

#define ADC1_SSMUX0_R           (*((volatile uint32_t *)0x40039040))

#define ADC1_SSCTL0_R           (*((volatile uint32_t *)0x40039044))

#define ADC1_SSFIFO0_R          (*((volatile uint32_t *)0x40039048))

#define ADC1_SSFSTAT0_R         (*((volatile uint32_t *)0x4003904C))

#define ADC1_SSOP0_R            (*((volatile uint32_t *)0x40039050))

#define ADC1_SSDC0_R            (*((volatile uint32_t *)0x40039054))

#define ADC1_SSMUX1_R           (*((volatile uint32_t *)0x40039060))

#define ADC1_SSCTL1_R           (*((volatile uint32_t *)0x40039064))

#define ADC1_SSFIFO1_R          (*((volatile uint32_t *)0x40039068))

#define ADC1_SSFSTAT1_R         (*((volatile uint32_t *)0x4003906C))

#define ADC1_SSOP1_R            (*((volatile uint32_t *)0x40039070))

#define ADC1_SSDC1_R            (*((volatile uint32_t *)0x40039074))

#define ADC1_SSMUX2_R           (*((volatile uint32_t *)0x40039080))

#define ADC1_SSCTL2_R           (*((volatile uint32_t *)0x40039084))

#define ADC1_SSFIFO2_R          (*((volatile uint32_t *)0x40039088))

#define ADC1_SSFSTAT2_R         (*((volatile uint32_t *)0x4003908C))

#define ADC1_SSOP2_R            (*((volatile uint32_t *)0x40039090))

#define ADC1_SSDC2_R            (*((volatile uint32_t *)0x40039094))

#define ADC1_SSMUX3_R           (*((volatile uint32_t *)0x400390A0))

#define ADC1_SSCTL3_R           (*((volatile uint32_t *)0x400390A4))

#define ADC1_SSFIFO3_R          (*((volatile uint32_t *)0x400390A8))

#define ADC1_SSFSTAT3_R         (*((volatile uint32_t *)0x400390AC))

#define ADC1_SSOP3_R            (*((volatile uint32_t *)0x400390B0))

#define ADC1_SSDC3_R            (*((volatile uint32_t *)0x400390B4))

#define ADC1_DCRIC_R            (*((volatile uint32_t *)0x40039D00))

#define ADC1_DCCTL0_R           (*((volatile uint32_t *)0x40039E00))

#define ADC1_DCCTL1_R           (*((volatile uint32_t *)0x40039E04))

#define ADC1_DCCTL2_R           (*((volatile uint32_t *)0x40039E08))

#define ADC1_DCCTL3_R           (*((volatile uint32_t *)0x40039E0C))

#define ADC1_DCCTL4_R           (*((volatile uint32_t *)0x40039E10))

#define ADC1_DCCTL5_R           (*((volatile uint32_t *)0x40039E14))

#define ADC1_DCCTL6_R           (*((volatile uint32_t *)0x40039E18))

#define ADC1_DCCTL7_R           (*((volatile uint32_t *)0x40039E1C))

#define ADC1_DCCMP0_R           (*((volatile uint32_t *)0x40039E40))

#define ADC1_DCCMP1_R           (*((volatile uint32_t *)0x40039E44))

#define ADC1_DCCMP2_R           (*((volatile uint32_t *)0x40039E48))

#define ADC1_DCCMP3_R           (*((volatile uint32_t *)0x40039E4C))

#define ADC1_DCCMP4_R           (*((volatile uint32_t *)0x40039E50))

#define ADC1_DCCMP5_R           (*((volatile uint32_t *)0x40039E54))

#define ADC1_DCCMP6_R           (*((volatile uint32_t *)0x40039E58))

#define ADC1_DCCMP7_R           (*((volatile uint32_t *)0x40039E5C))

#define ADC1_PP_R               (*((volatile uint32_t *)0x40039FC0))

#define ADC1_PC_R               (*((volatile uint32_t *)0x40039FC4))

#define ADC1_CC_R               (*((volatile uint32_t *)0x40039FC8))


//*****************************************************************************

//

// Comparator registers (COMP)

//

//*****************************************************************************

#define COMP_ACMIS_R            (*((volatile uint32_t *)0x4003C000))

#define COMP_ACRIS_R            (*((volatile uint32_t *)0x4003C004))

#define COMP_ACINTEN_R          (*((volatile uint32_t *)0x4003C008))

#define COMP_ACREFCTL_R         (*((volatile uint32_t *)0x4003C010))

#define COMP_ACSTAT0_R          (*((volatile uint32_t *)0x4003C020))

#define COMP_ACCTL0_R           (*((volatile uint32_t *)0x4003C024))

#define COMP_ACSTAT1_R          (*((volatile uint32_t *)0x4003C040))

#define COMP_ACCTL1_R           (*((volatile uint32_t *)0x4003C044))

#define COMP_PP_R               (*((volatile uint32_t *)0x4003CFC0))


//*****************************************************************************

//

// CAN registers (CAN0)

//

//*****************************************************************************

#define CAN0_CTL_R              (*((volatile uint32_t *)0x40040000))

#define CAN0_STS_R              (*((volatile uint32_t *)0x40040004))

#define CAN0_ERR_R              (*((volatile uint32_t *)0x40040008))

#define CAN0_BIT_R              (*((volatile uint32_t *)0x4004000C))

#define CAN0_INT_R              (*((volatile uint32_t *)0x40040010))

#define CAN0_TST_R              (*((volatile uint32_t *)0x40040014))

#define CAN0_BRPE_R             (*((volatile uint32_t *)0x40040018))

#define CAN0_IF1CRQ_R           (*((volatile uint32_t *)0x40040020))

#define CAN0_IF1CMSK_R          (*((volatile uint32_t *)0x40040024))

#define CAN0_IF1MSK1_R          (*((volatile uint32_t *)0x40040028))

#define CAN0_IF1MSK2_R          (*((volatile uint32_t *)0x4004002C))

#define CAN0_IF1ARB1_R          (*((volatile uint32_t *)0x40040030))

#define CAN0_IF1ARB2_R          (*((volatile uint32_t *)0x40040034))

#define CAN0_IF1MCTL_R          (*((volatile uint32_t *)0x40040038))

#define CAN0_IF1DA1_R           (*((volatile uint32_t *)0x4004003C))

#define CAN0_IF1DA2_R           (*((volatile uint32_t *)0x40040040))

#define CAN0_IF1DB1_R           (*((volatile uint32_t *)0x40040044))

#define CAN0_IF1DB2_R           (*((volatile uint32_t *)0x40040048))

#define CAN0_IF2CRQ_R           (*((volatile uint32_t *)0x40040080))

#define CAN0_IF2CMSK_R          (*((volatile uint32_t *)0x40040084))

#define CAN0_IF2MSK1_R          (*((volatile uint32_t *)0x40040088))

#define CAN0_IF2MSK2_R          (*((volatile uint32_t *)0x4004008C))

#define CAN0_IF2ARB1_R          (*((volatile uint32_t *)0x40040090))

#define CAN0_IF2ARB2_R          (*((volatile uint32_t *)0x40040094))

#define CAN0_IF2MCTL_R          (*((volatile uint32_t *)0x40040098))

#define CAN0_IF2DA1_R           (*((volatile uint32_t *)0x4004009C))

#define CAN0_IF2DA2_R           (*((volatile uint32_t *)0x400400A0))

#define CAN0_IF2DB1_R           (*((volatile uint32_t *)0x400400A4))

#define CAN0_IF2DB2_R           (*((volatile uint32_t *)0x400400A8))

#define CAN0_TXRQ1_R            (*((volatile uint32_t *)0x40040100))

#define CAN0_TXRQ2_R            (*((volatile uint32_t *)0x40040104))

#define CAN0_NWDA1_R            (*((volatile uint32_t *)0x40040120))

#define CAN0_NWDA2_R            (*((volatile uint32_t *)0x40040124))

#define CAN0_MSG1INT_R          (*((volatile uint32_t *)0x40040140))

#define CAN0_MSG2INT_R          (*((volatile uint32_t *)0x40040144))

#define CAN0_MSG1VAL_R          (*((volatile uint32_t *)0x40040160))

#define CAN0_MSG2VAL_R          (*((volatile uint32_t *)0x40040164))


//*****************************************************************************

//

// CAN registers (CAN1)

//

//*****************************************************************************

#define CAN1_CTL_R              (*((volatile uint32_t *)0x40041000))

#define CAN1_STS_R              (*((volatile uint32_t *)0x40041004))

#define CAN1_ERR_R              (*((volatile uint32_t *)0x40041008))

#define CAN1_BIT_R              (*((volatile uint32_t *)0x4004100C))

#define CAN1_INT_R              (*((volatile uint32_t *)0x40041010))

#define CAN1_TST_R              (*((volatile uint32_t *)0x40041014))

#define CAN1_BRPE_R             (*((volatile uint32_t *)0x40041018))

#define CAN1_IF1CRQ_R           (*((volatile uint32_t *)0x40041020))

#define CAN1_IF1CMSK_R          (*((volatile uint32_t *)0x40041024))

#define CAN1_IF1MSK1_R          (*((volatile uint32_t *)0x40041028))

#define CAN1_IF1MSK2_R          (*((volatile uint32_t *)0x4004102C))

#define CAN1_IF1ARB1_R          (*((volatile uint32_t *)0x40041030))

#define CAN1_IF1ARB2_R          (*((volatile uint32_t *)0x40041034))

#define CAN1_IF1MCTL_R          (*((volatile uint32_t *)0x40041038))

#define CAN1_IF1DA1_R           (*((volatile uint32_t *)0x4004103C))

#define CAN1_IF1DA2_R           (*((volatile uint32_t *)0x40041040))

#define CAN1_IF1DB1_R           (*((volatile uint32_t *)0x40041044))

#define CAN1_IF1DB2_R           (*((volatile uint32_t *)0x40041048))

#define CAN1_IF2CRQ_R           (*((volatile uint32_t *)0x40041080))

#define CAN1_IF2CMSK_R          (*((volatile uint32_t *)0x40041084))

#define CAN1_IF2MSK1_R          (*((volatile uint32_t *)0x40041088))

#define CAN1_IF2MSK2_R          (*((volatile uint32_t *)0x4004108C))

#define CAN1_IF2ARB1_R          (*((volatile uint32_t *)0x40041090))

#define CAN1_IF2ARB2_R          (*((volatile uint32_t *)0x40041094))

#define CAN1_IF2MCTL_R          (*((volatile uint32_t *)0x40041098))

#define CAN1_IF2DA1_R           (*((volatile uint32_t *)0x4004109C))

#define CAN1_IF2DA2_R           (*((volatile uint32_t *)0x400410A0))

#define CAN1_IF2DB1_R           (*((volatile uint32_t *)0x400410A4))

#define CAN1_IF2DB2_R           (*((volatile uint32_t *)0x400410A8))

#define CAN1_TXRQ1_R            (*((volatile uint32_t *)0x40041100))

#define CAN1_TXRQ2_R            (*((volatile uint32_t *)0x40041104))

#define CAN1_NWDA1_R            (*((volatile uint32_t *)0x40041120))

#define CAN1_NWDA2_R            (*((volatile uint32_t *)0x40041124))

#define CAN1_MSG1INT_R          (*((volatile uint32_t *)0x40041140))

#define CAN1_MSG2INT_R          (*((volatile uint32_t *)0x40041144))

#define CAN1_MSG1VAL_R          (*((volatile uint32_t *)0x40041160))

#define CAN1_MSG2VAL_R          (*((volatile uint32_t *)0x40041164))


//*****************************************************************************

//

// Timer registers (WTIMER2)

//

//*****************************************************************************

#define WTIMER2_CFG_R           (*((volatile uint32_t *)0x4004C000))

#define WTIMER2_TAMR_R          (*((volatile uint32_t *)0x4004C004))

#define WTIMER2_TBMR_R          (*((volatile uint32_t *)0x4004C008))

#define WTIMER2_CTL_R           (*((volatile uint32_t *)0x4004C00C))

#define WTIMER2_SYNC_R          (*((volatile uint32_t *)0x4004C010))

#define WTIMER2_IMR_R           (*((volatile uint32_t *)0x4004C018))

#define WTIMER2_RIS_R           (*((volatile uint32_t *)0x4004C01C))

#define WTIMER2_MIS_R           (*((volatile uint32_t *)0x4004C020))

#define WTIMER2_ICR_R           (*((volatile uint32_t *)0x4004C024))

#define WTIMER2_TAILR_R         (*((volatile uint32_t *)0x4004C028))

#define WTIMER2_TBILR_R         (*((volatile uint32_t *)0x4004C02C))

#define WTIMER2_TAMATCHR_R      (*((volatile uint32_t *)0x4004C030))

#define WTIMER2_TBMATCHR_R      (*((volatile uint32_t *)0x4004C034))

#define WTIMER2_TAPR_R          (*((volatile uint32_t *)0x4004C038))

#define WTIMER2_TBPR_R          (*((volatile uint32_t *)0x4004C03C))

#define WTIMER2_TAPMR_R         (*((volatile uint32_t *)0x4004C040))

#define WTIMER2_TBPMR_R         (*((volatile uint32_t *)0x4004C044))

#define WTIMER2_TAR_R           (*((volatile uint32_t *)0x4004C048))

#define WTIMER2_TBR_R           (*((volatile uint32_t *)0x4004C04C))

#define WTIMER2_TAV_R           (*((volatile uint32_t *)0x4004C050))

#define WTIMER2_TBV_R           (*((volatile uint32_t *)0x4004C054))

#define WTIMER2_RTCPD_R         (*((volatile uint32_t *)0x4004C058))

#define WTIMER2_TAPS_R          (*((volatile uint32_t *)0x4004C05C))

#define WTIMER2_TBPS_R          (*((volatile uint32_t *)0x4004C060))

#define WTIMER2_TAPV_R          (*((volatile uint32_t *)0x4004C064))

#define WTIMER2_TBPV_R          (*((volatile uint32_t *)0x4004C068))

#define WTIMER2_PP_R            (*((volatile uint32_t *)0x4004CFC0))


//*****************************************************************************

//

// Timer registers (WTIMER3)

//

//*****************************************************************************

#define WTIMER3_CFG_R           (*((volatile uint32_t *)0x4004D000))

#define WTIMER3_TAMR_R          (*((volatile uint32_t *)0x4004D004))

#define WTIMER3_TBMR_R          (*((volatile uint32_t *)0x4004D008))

#define WTIMER3_CTL_R           (*((volatile uint32_t *)0x4004D00C))

#define WTIMER3_SYNC_R          (*((volatile uint32_t *)0x4004D010))

#define WTIMER3_IMR_R           (*((volatile uint32_t *)0x4004D018))

#define WTIMER3_RIS_R           (*((volatile uint32_t *)0x4004D01C))

#define WTIMER3_MIS_R           (*((volatile uint32_t *)0x4004D020))

#define WTIMER3_ICR_R           (*((volatile uint32_t *)0x4004D024))

#define WTIMER3_TAILR_R         (*((volatile uint32_t *)0x4004D028))

#define WTIMER3_TBILR_R         (*((volatile uint32_t *)0x4004D02C))

#define WTIMER3_TAMATCHR_R      (*((volatile uint32_t *)0x4004D030))

#define WTIMER3_TBMATCHR_R      (*((volatile uint32_t *)0x4004D034))

#define WTIMER3_TAPR_R          (*((volatile uint32_t *)0x4004D038))

#define WTIMER3_TBPR_R          (*((volatile uint32_t *)0x4004D03C))

#define WTIMER3_TAPMR_R         (*((volatile uint32_t *)0x4004D040))

#define WTIMER3_TBPMR_R         (*((volatile uint32_t *)0x4004D044))

#define WTIMER3_TAR_R           (*((volatile uint32_t *)0x4004D048))

#define WTIMER3_TBR_R           (*((volatile uint32_t *)0x4004D04C))

#define WTIMER3_TAV_R           (*((volatile uint32_t *)0x4004D050))

#define WTIMER3_TBV_R           (*((volatile uint32_t *)0x4004D054))

#define WTIMER3_RTCPD_R         (*((volatile uint32_t *)0x4004D058))

#define WTIMER3_TAPS_R          (*((volatile uint32_t *)0x4004D05C))

#define WTIMER3_TBPS_R          (*((volatile uint32_t *)0x4004D060))

#define WTIMER3_TAPV_R          (*((volatile uint32_t *)0x4004D064))

#define WTIMER3_TBPV_R          (*((volatile uint32_t *)0x4004D068))

#define WTIMER3_PP_R            (*((volatile uint32_t *)0x4004DFC0))


//*****************************************************************************

//

// Timer registers (WTIMER4)

//

//*****************************************************************************

#define WTIMER4_CFG_R           (*((volatile uint32_t *)0x4004E000))

#define WTIMER4_TAMR_R          (*((volatile uint32_t *)0x4004E004))

#define WTIMER4_TBMR_R          (*((volatile uint32_t *)0x4004E008))

#define WTIMER4_CTL_R           (*((volatile uint32_t *)0x4004E00C))

#define WTIMER4_SYNC_R          (*((volatile uint32_t *)0x4004E010))

#define WTIMER4_IMR_R           (*((volatile uint32_t *)0x4004E018))

#define WTIMER4_RIS_R           (*((volatile uint32_t *)0x4004E01C))

#define WTIMER4_MIS_R           (*((volatile uint32_t *)0x4004E020))

#define WTIMER4_ICR_R           (*((volatile uint32_t *)0x4004E024))

#define WTIMER4_TAILR_R         (*((volatile uint32_t *)0x4004E028))

#define WTIMER4_TBILR_R         (*((volatile uint32_t *)0x4004E02C))

#define WTIMER4_TAMATCHR_R      (*((volatile uint32_t *)0x4004E030))

#define WTIMER4_TBMATCHR_R      (*((volatile uint32_t *)0x4004E034))

#define WTIMER4_TAPR_R          (*((volatile uint32_t *)0x4004E038))

#define WTIMER4_TBPR_R          (*((volatile uint32_t *)0x4004E03C))

#define WTIMER4_TAPMR_R         (*((volatile uint32_t *)0x4004E040))

#define WTIMER4_TBPMR_R         (*((volatile uint32_t *)0x4004E044))

#define WTIMER4_TAR_R           (*((volatile uint32_t *)0x4004E048))

#define WTIMER4_TBR_R           (*((volatile uint32_t *)0x4004E04C))

#define WTIMER4_TAV_R           (*((volatile uint32_t *)0x4004E050))

#define WTIMER4_TBV_R           (*((volatile uint32_t *)0x4004E054))

#define WTIMER4_RTCPD_R         (*((volatile uint32_t *)0x4004E058))

#define WTIMER4_TAPS_R          (*((volatile uint32_t *)0x4004E05C))

#define WTIMER4_TBPS_R          (*((volatile uint32_t *)0x4004E060))

#define WTIMER4_TAPV_R          (*((volatile uint32_t *)0x4004E064))

#define WTIMER4_TBPV_R          (*((volatile uint32_t *)0x4004E068))

#define WTIMER4_PP_R            (*((volatile uint32_t *)0x4004EFC0))


//*****************************************************************************

//

// Timer registers (WTIMER5)

//

//*****************************************************************************

#define WTIMER5_CFG_R           (*((volatile uint32_t *)0x4004F000))

#define WTIMER5_TAMR_R          (*((volatile uint32_t *)0x4004F004))

#define WTIMER5_TBMR_R          (*((volatile uint32_t *)0x4004F008))

#define WTIMER5_CTL_R           (*((volatile uint32_t *)0x4004F00C))

#define WTIMER5_SYNC_R          (*((volatile uint32_t *)0x4004F010))

#define WTIMER5_IMR_R           (*((volatile uint32_t *)0x4004F018))

#define WTIMER5_RIS_R           (*((volatile uint32_t *)0x4004F01C))

#define WTIMER5_MIS_R           (*((volatile uint32_t *)0x4004F020))

#define WTIMER5_ICR_R           (*((volatile uint32_t *)0x4004F024))

#define WTIMER5_TAILR_R         (*((volatile uint32_t *)0x4004F028))

#define WTIMER5_TBILR_R         (*((volatile uint32_t *)0x4004F02C))

#define WTIMER5_TAMATCHR_R      (*((volatile uint32_t *)0x4004F030))

#define WTIMER5_TBMATCHR_R      (*((volatile uint32_t *)0x4004F034))

#define WTIMER5_TAPR_R          (*((volatile uint32_t *)0x4004F038))

#define WTIMER5_TBPR_R          (*((volatile uint32_t *)0x4004F03C))

#define WTIMER5_TAPMR_R         (*((volatile uint32_t *)0x4004F040))

#define WTIMER5_TBPMR_R         (*((volatile uint32_t *)0x4004F044))

#define WTIMER5_TAR_R           (*((volatile uint32_t *)0x4004F048))

#define WTIMER5_TBR_R           (*((volatile uint32_t *)0x4004F04C))

#define WTIMER5_TAV_R           (*((volatile uint32_t *)0x4004F050))

#define WTIMER5_TBV_R           (*((volatile uint32_t *)0x4004F054))

#define WTIMER5_RTCPD_R         (*((volatile uint32_t *)0x4004F058))

#define WTIMER5_TAPS_R          (*((volatile uint32_t *)0x4004F05C))

#define WTIMER5_TBPS_R          (*((volatile uint32_t *)0x4004F060))

#define WTIMER5_TAPV_R          (*((volatile uint32_t *)0x4004F064))

#define WTIMER5_TBPV_R          (*((volatile uint32_t *)0x4004F068))

#define WTIMER5_PP_R            (*((volatile uint32_t *)0x4004FFC0))


//*****************************************************************************

//

// Univeral Serial Bus registers (USB0)

//

//*****************************************************************************

#define USB0_FADDR_R            (*((volatile uint8_t *)0x40050000))

#define USB0_POWER_R            (*((volatile uint8_t *)0x40050001))

#define USB0_TXIS_R             (*((volatile uint16_t *)0x40050002))

#define USB0_RXIS_R             (*((volatile uint16_t *)0x40050004))

#define USB0_TXIE_R             (*((volatile uint16_t *)0x40050006))

#define USB0_RXIE_R             (*((volatile uint16_t *)0x40050008))

#define USB0_IS_R               (*((volatile uint8_t *)0x4005000A))

#define USB0_IE_R               (*((volatile uint8_t *)0x4005000B))

#define USB0_FRAME_R            (*((volatile uint16_t *)0x4005000C))

#define USB0_EPIDX_R            (*((volatile uint8_t *)0x4005000E))

#define USB0_TEST_R             (*((volatile uint8_t *)0x4005000F))

#define USB0_FIFO0_R            (*((volatile uint32_t *)0x40050020))

#define USB0_FIFO1_R            (*((volatile uint32_t *)0x40050024))

#define USB0_FIFO2_R            (*((volatile uint32_t *)0x40050028))

#define USB0_FIFO3_R            (*((volatile uint32_t *)0x4005002C))

#define USB0_FIFO4_R            (*((volatile uint32_t *)0x40050030))

#define USB0_FIFO5_R            (*((volatile uint32_t *)0x40050034))

#define USB0_FIFO6_R            (*((volatile uint32_t *)0x40050038))

#define USB0_FIFO7_R            (*((volatile uint32_t *)0x4005003C))

#define USB0_DEVCTL_R           (*((volatile uint8_t *)0x40050060))

#define USB0_TXFIFOSZ_R         (*((volatile uint8_t *)0x40050062))

#define USB0_RXFIFOSZ_R         (*((volatile uint8_t *)0x40050063))

#define USB0_TXFIFOADD_R        (*((volatile uint16_t *)0x40050064))

#define USB0_RXFIFOADD_R        (*((volatile uint16_t *)0x40050066))

#define USB0_CONTIM_R           (*((volatile uint8_t *)0x4005007A))

#define USB0_VPLEN_R            (*((volatile uint8_t *)0x4005007B))

#define USB0_FSEOF_R            (*((volatile uint8_t *)0x4005007D))

#define USB0_LSEOF_R            (*((volatile uint8_t *)0x4005007E))

#define USB0_TXFUNCADDR0_R      (*((volatile uint8_t *)0x40050080))

#define USB0_TXHUBADDR0_R       (*((volatile uint8_t *)0x40050082))

#define USB0_TXHUBPORT0_R       (*((volatile uint8_t *)0x40050083))

#define USB0_TXFUNCADDR1_R      (*((volatile uint8_t *)0x40050088))

#define USB0_TXHUBADDR1_R       (*((volatile uint8_t *)0x4005008A))

#define USB0_TXHUBPORT1_R       (*((volatile uint8_t *)0x4005008B))

#define USB0_RXFUNCADDR1_R      (*((volatile uint8_t *)0x4005008C))

#define USB0_RXHUBADDR1_R       (*((volatile uint8_t *)0x4005008E))

#define USB0_RXHUBPORT1_R       (*((volatile uint8_t *)0x4005008F))

#define USB0_TXFUNCADDR2_R      (*((volatile uint8_t *)0x40050090))

#define USB0_TXHUBADDR2_R       (*((volatile uint8_t *)0x40050092))

#define USB0_TXHUBPORT2_R       (*((volatile uint8_t *)0x40050093))

#define USB0_RXFUNCADDR2_R      (*((volatile uint8_t *)0x40050094))

#define USB0_RXHUBADDR2_R       (*((volatile uint8_t *)0x40050096))

#define USB0_RXHUBPORT2_R       (*((volatile uint8_t *)0x40050097))

#define USB0_TXFUNCADDR3_R      (*((volatile uint8_t *)0x40050098))

#define USB0_TXHUBADDR3_R       (*((volatile uint8_t *)0x4005009A))

#define USB0_TXHUBPORT3_R       (*((volatile uint8_t *)0x4005009B))

#define USB0_RXFUNCADDR3_R      (*((volatile uint8_t *)0x4005009C))

#define USB0_RXHUBADDR3_R       (*((volatile uint8_t *)0x4005009E))

#define USB0_RXHUBPORT3_R       (*((volatile uint8_t *)0x4005009F))

#define USB0_TXFUNCADDR4_R      (*((volatile uint8_t *)0x400500A0))

#define USB0_TXHUBADDR4_R       (*((volatile uint8_t *)0x400500A2))

#define USB0_TXHUBPORT4_R       (*((volatile uint8_t *)0x400500A3))

#define USB0_RXFUNCADDR4_R      (*((volatile uint8_t *)0x400500A4))

#define USB0_RXHUBADDR4_R       (*((volatile uint8_t *)0x400500A6))

#define USB0_RXHUBPORT4_R       (*((volatile uint8_t *)0x400500A7))

#define USB0_TXFUNCADDR5_R      (*((volatile uint8_t *)0x400500A8))

#define USB0_TXHUBADDR5_R       (*((volatile uint8_t *)0x400500AA))

#define USB0_TXHUBPORT5_R       (*((volatile uint8_t *)0x400500AB))

#define USB0_RXFUNCADDR5_R      (*((volatile uint8_t *)0x400500AC))

#define USB0_RXHUBADDR5_R       (*((volatile uint8_t *)0x400500AE))

#define USB0_RXHUBPORT5_R       (*((volatile uint8_t *)0x400500AF))

#define USB0_TXFUNCADDR6_R      (*((volatile uint8_t *)0x400500B0))

#define USB0_TXHUBADDR6_R       (*((volatile uint8_t *)0x400500B2))

#define USB0_TXHUBPORT6_R       (*((volatile uint8_t *)0x400500B3))

#define USB0_RXFUNCADDR6_R      (*((volatile uint8_t *)0x400500B4))

#define USB0_RXHUBADDR6_R       (*((volatile uint8_t *)0x400500B6))

#define USB0_RXHUBPORT6_R       (*((volatile uint8_t *)0x400500B7))

#define USB0_TXFUNCADDR7_R      (*((volatile uint8_t *)0x400500B8))

#define USB0_TXHUBADDR7_R       (*((volatile uint8_t *)0x400500BA))

#define USB0_TXHUBPORT7_R       (*((volatile uint8_t *)0x400500BB))

#define USB0_RXFUNCADDR7_R      (*((volatile uint8_t *)0x400500BC))

#define USB0_RXHUBADDR7_R       (*((volatile uint8_t *)0x400500BE))

#define USB0_RXHUBPORT7_R       (*((volatile uint8_t *)0x400500BF))

#define USB0_CSRL0_R            (*((volatile uint8_t *)0x40050102))

#define USB0_CSRH0_R            (*((volatile uint8_t *)0x40050103))

#define USB0_COUNT0_R           (*((volatile uint8_t *)0x40050108))

#define USB0_TYPE0_R            (*((volatile uint8_t *)0x4005010A))

#define USB0_NAKLMT_R           (*((volatile uint8_t *)0x4005010B))

#define USB0_TXMAXP1_R          (*((volatile uint16_t *)0x40050110))

#define USB0_TXCSRL1_R          (*((volatile uint8_t *)0x40050112))

#define USB0_TXCSRH1_R          (*((volatile uint8_t *)0x40050113))

#define USB0_RXMAXP1_R          (*((volatile uint16_t *)0x40050114))

#define USB0_RXCSRL1_R          (*((volatile uint8_t *)0x40050116))

#define USB0_RXCSRH1_R          (*((volatile uint8_t *)0x40050117))

#define USB0_RXCOUNT1_R         (*((volatile uint16_t *)0x40050118))

#define USB0_TXTYPE1_R          (*((volatile uint8_t *)0x4005011A))

#define USB0_TXINTERVAL1_R      (*((volatile uint8_t *)0x4005011B))

#define USB0_RXTYPE1_R          (*((volatile uint8_t *)0x4005011C))

#define USB0_RXINTERVAL1_R      (*((volatile uint8_t *)0x4005011D))

#define USB0_TXMAXP2_R          (*((volatile uint16_t *)0x40050120))

#define USB0_TXCSRL2_R          (*((volatile uint8_t *)0x40050122))

#define USB0_TXCSRH2_R          (*((volatile uint8_t *)0x40050123))

#define USB0_RXMAXP2_R          (*((volatile uint16_t *)0x40050124))

#define USB0_RXCSRL2_R          (*((volatile uint8_t *)0x40050126))

#define USB0_RXCSRH2_R          (*((volatile uint8_t *)0x40050127))

#define USB0_RXCOUNT2_R         (*((volatile uint16_t *)0x40050128))

#define USB0_TXTYPE2_R          (*((volatile uint8_t *)0x4005012A))

#define USB0_TXINTERVAL2_R      (*((volatile uint8_t *)0x4005012B))

#define USB0_RXTYPE2_R          (*((volatile uint8_t *)0x4005012C))

#define USB0_RXINTERVAL2_R      (*((volatile uint8_t *)0x4005012D))

#define USB0_TXMAXP3_R          (*((volatile uint16_t *)0x40050130))

#define USB0_TXCSRL3_R          (*((volatile uint8_t *)0x40050132))

#define USB0_TXCSRH3_R          (*((volatile uint8_t *)0x40050133))

#define USB0_RXMAXP3_R          (*((volatile uint16_t *)0x40050134))

#define USB0_RXCSRL3_R          (*((volatile uint8_t *)0x40050136))

#define USB0_RXCSRH3_R          (*((volatile uint8_t *)0x40050137))

#define USB0_RXCOUNT3_R         (*((volatile uint16_t *)0x40050138))

#define USB0_TXTYPE3_R          (*((volatile uint8_t *)0x4005013A))

#define USB0_TXINTERVAL3_R      (*((volatile uint8_t *)0x4005013B))

#define USB0_RXTYPE3_R          (*((volatile uint8_t *)0x4005013C))

#define USB0_RXINTERVAL3_R      (*((volatile uint8_t *)0x4005013D))

#define USB0_TXMAXP4_R          (*((volatile uint16_t *)0x40050140))

#define USB0_TXCSRL4_R          (*((volatile uint8_t *)0x40050142))

#define USB0_TXCSRH4_R          (*((volatile uint8_t *)0x40050143))

#define USB0_RXMAXP4_R          (*((volatile uint16_t *)0x40050144))

#define USB0_RXCSRL4_R          (*((volatile uint8_t *)0x40050146))

#define USB0_RXCSRH4_R          (*((volatile uint8_t *)0x40050147))

#define USB0_RXCOUNT4_R         (*((volatile uint16_t *)0x40050148))

#define USB0_TXTYPE4_R          (*((volatile uint8_t *)0x4005014A))

#define USB0_TXINTERVAL4_R      (*((volatile uint8_t *)0x4005014B))

#define USB0_RXTYPE4_R          (*((volatile uint8_t *)0x4005014C))

#define USB0_RXINTERVAL4_R      (*((volatile uint8_t *)0x4005014D))

#define USB0_TXMAXP5_R          (*((volatile uint16_t *)0x40050150))

#define USB0_TXCSRL5_R          (*((volatile uint8_t *)0x40050152))

#define USB0_TXCSRH5_R          (*((volatile uint8_t *)0x40050153))

#define USB0_RXMAXP5_R          (*((volatile uint16_t *)0x40050154))

#define USB0_RXCSRL5_R          (*((volatile uint8_t *)0x40050156))

#define USB0_RXCSRH5_R          (*((volatile uint8_t *)0x40050157))

#define USB0_RXCOUNT5_R         (*((volatile uint16_t *)0x40050158))

#define USB0_TXTYPE5_R          (*((volatile uint8_t *)0x4005015A))

#define USB0_TXINTERVAL5_R      (*((volatile uint8_t *)0x4005015B))

#define USB0_RXTYPE5_R          (*((volatile uint8_t *)0x4005015C))

#define USB0_RXINTERVAL5_R      (*((volatile uint8_t *)0x4005015D))

#define USB0_TXMAXP6_R          (*((volatile uint16_t *)0x40050160))

#define USB0_TXCSRL6_R          (*((volatile uint8_t *)0x40050162))

#define USB0_TXCSRH6_R          (*((volatile uint8_t *)0x40050163))

#define USB0_RXMAXP6_R          (*((volatile uint16_t *)0x40050164))

#define USB0_RXCSRL6_R          (*((volatile uint8_t *)0x40050166))

#define USB0_RXCSRH6_R          (*((volatile uint8_t *)0x40050167))

#define USB0_RXCOUNT6_R         (*((volatile uint16_t *)0x40050168))

#define USB0_TXTYPE6_R          (*((volatile uint8_t *)0x4005016A))

#define USB0_TXINTERVAL6_R      (*((volatile uint8_t *)0x4005016B))

#define USB0_RXTYPE6_R          (*((volatile uint8_t *)0x4005016C))

#define USB0_RXINTERVAL6_R      (*((volatile uint8_t *)0x4005016D))

#define USB0_TXMAXP7_R          (*((volatile uint16_t *)0x40050170))

#define USB0_TXCSRL7_R          (*((volatile uint8_t *)0x40050172))

#define USB0_TXCSRH7_R          (*((volatile uint8_t *)0x40050173))

#define USB0_RXMAXP7_R          (*((volatile uint16_t *)0x40050174))

#define USB0_RXCSRL7_R          (*((volatile uint8_t *)0x40050176))

#define USB0_RXCSRH7_R          (*((volatile uint8_t *)0x40050177))

#define USB0_RXCOUNT7_R         (*((volatile uint16_t *)0x40050178))

#define USB0_TXTYPE7_R          (*((volatile uint8_t *)0x4005017A))

#define USB0_TXINTERVAL7_R      (*((volatile uint8_t *)0x4005017B))

#define USB0_RXTYPE7_R          (*((volatile uint8_t *)0x4005017C))

#define USB0_RXINTERVAL7_R      (*((volatile uint8_t *)0x4005017D))

#define USB0_RQPKTCOUNT1_R      (*((volatile uint16_t *)0x40050304))

#define USB0_RQPKTCOUNT2_R      (*((volatile uint16_t *)0x40050308))

#define USB0_RQPKTCOUNT3_R      (*((volatile uint16_t *)0x4005030C))

#define USB0_RQPKTCOUNT4_R      (*((volatile uint16_t *)0x40050310))

#define USB0_RQPKTCOUNT5_R      (*((volatile uint16_t *)0x40050314))

#define USB0_RQPKTCOUNT6_R      (*((volatile uint16_t *)0x40050318))

#define USB0_RQPKTCOUNT7_R      (*((volatile uint16_t *)0x4005031C))

#define USB0_RXDPKTBUFDIS_R     (*((volatile uint16_t *)0x40050340))

#define USB0_TXDPKTBUFDIS_R     (*((volatile uint16_t *)0x40050342))

#define USB0_EPC_R              (*((volatile uint32_t *)0x40050400))

#define USB0_EPCRIS_R           (*((volatile uint32_t *)0x40050404))

#define USB0_EPCIM_R            (*((volatile uint32_t *)0x40050408))

#define USB0_EPCISC_R           (*((volatile uint32_t *)0x4005040C))

#define USB0_DRRIS_R            (*((volatile uint32_t *)0x40050410))

#define USB0_DRIM_R             (*((volatile uint32_t *)0x40050414))

#define USB0_DRISC_R            (*((volatile uint32_t *)0x40050418))

#define USB0_GPCS_R             (*((volatile uint32_t *)0x4005041C))

#define USB0_VDC_R              (*((volatile uint32_t *)0x40050430))

#define USB0_VDCRIS_R           (*((volatile uint32_t *)0x40050434))

#define USB0_VDCIM_R            (*((volatile uint32_t *)0x40050438))

#define USB0_VDCISC_R           (*((volatile uint32_t *)0x4005043C))

#define USB0_IDVRIS_R           (*((volatile uint32_t *)0x40050444))

#define USB0_IDVIM_R            (*((volatile uint32_t *)0x40050448))

#define USB0_IDVISC_R           (*((volatile uint32_t *)0x4005044C))

#define USB0_DMASEL_R           (*((volatile uint32_t *)0x40050450))

#define USB0_PP_R               (*((volatile uint32_t *)0x40050FC0))


//*****************************************************************************

//

// GPIO registers (PORTA AHB)

//

//*****************************************************************************

#define GPIO_PORTA_AHB_DATA_BITS_R                                            \

                                ((volatile uint32_t *)0x40058000)

#define GPIO_PORTA_AHB_DATA_R   (*((volatile uint32_t *)0x400583FC))

#define GPIO_PORTA_AHB_DIR_R    (*((volatile uint32_t *)0x40058400))

#define GPIO_PORTA_AHB_IS_R     (*((volatile uint32_t *)0x40058404))

#define GPIO_PORTA_AHB_IBE_R    (*((volatile uint32_t *)0x40058408))

#define GPIO_PORTA_AHB_IEV_R    (*((volatile uint32_t *)0x4005840C))

#define GPIO_PORTA_AHB_IM_R     (*((volatile uint32_t *)0x40058410))

#define GPIO_PORTA_AHB_RIS_R    (*((volatile uint32_t *)0x40058414))

#define GPIO_PORTA_AHB_MIS_R    (*((volatile uint32_t *)0x40058418))

#define GPIO_PORTA_AHB_ICR_R    (*((volatile uint32_t *)0x4005841C))

#define GPIO_PORTA_AHB_AFSEL_R  (*((volatile uint32_t *)0x40058420))

#define GPIO_PORTA_AHB_DR2R_R   (*((volatile uint32_t *)0x40058500))

#define GPIO_PORTA_AHB_DR4R_R   (*((volatile uint32_t *)0x40058504))

#define GPIO_PORTA_AHB_DR8R_R   (*((volatile uint32_t *)0x40058508))

#define GPIO_PORTA_AHB_ODR_R    (*((volatile uint32_t *)0x4005850C))

#define GPIO_PORTA_AHB_PUR_R    (*((volatile uint32_t *)0x40058510))

#define GPIO_PORTA_AHB_PDR_R    (*((volatile uint32_t *)0x40058514))

#define GPIO_PORTA_AHB_SLR_R    (*((volatile uint32_t *)0x40058518))

#define GPIO_PORTA_AHB_DEN_R    (*((volatile uint32_t *)0x4005851C))

#define GPIO_PORTA_AHB_LOCK_R   (*((volatile uint32_t *)0x40058520))

#define GPIO_PORTA_AHB_CR_R     (*((volatile uint32_t *)0x40058524))

#define GPIO_PORTA_AHB_AMSEL_R  (*((volatile uint32_t *)0x40058528))

#define GPIO_PORTA_AHB_PCTL_R   (*((volatile uint32_t *)0x4005852C))

#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530))

#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534))


//*****************************************************************************

//

// GPIO registers (PORTB AHB)

//

//*****************************************************************************

#define GPIO_PORTB_AHB_DATA_BITS_R                                            \

                                ((volatile uint32_t *)0x40059000)

#define GPIO_PORTB_AHB_DATA_R   (*((volatile uint32_t *)0x400593FC))

#define GPIO_PORTB_AHB_DIR_R    (*((volatile uint32_t *)0x40059400))

#define GPIO_PORTB_AHB_IS_R     (*((volatile uint32_t *)0x40059404))

#define GPIO_PORTB_AHB_IBE_R    (*((volatile uint32_t *)0x40059408))

#define GPIO_PORTB_AHB_IEV_R    (*((volatile uint32_t *)0x4005940C))

#define GPIO_PORTB_AHB_IM_R     (*((volatile uint32_t *)0x40059410))

#define GPIO_PORTB_AHB_RIS_R    (*((volatile uint32_t *)0x40059414))

#define GPIO_PORTB_AHB_MIS_R    (*((volatile uint32_t *)0x40059418))

#define GPIO_PORTB_AHB_ICR_R    (*((volatile uint32_t *)0x4005941C))

#define GPIO_PORTB_AHB_AFSEL_R  (*((volatile uint32_t *)0x40059420))

#define GPIO_PORTB_AHB_DR2R_R   (*((volatile uint32_t *)0x40059500))

#define GPIO_PORTB_AHB_DR4R_R   (*((volatile uint32_t *)0x40059504))

#define GPIO_PORTB_AHB_DR8R_R   (*((volatile uint32_t *)0x40059508))

#define GPIO_PORTB_AHB_ODR_R    (*((volatile uint32_t *)0x4005950C))

#define GPIO_PORTB_AHB_PUR_R    (*((volatile uint32_t *)0x40059510))

#define GPIO_PORTB_AHB_PDR_R    (*((volatile uint32_t *)0x40059514))

#define GPIO_PORTB_AHB_SLR_R    (*((volatile uint32_t *)0x40059518))

#define GPIO_PORTB_AHB_DEN_R    (*((volatile uint32_t *)0x4005951C))

#define GPIO_PORTB_AHB_LOCK_R   (*((volatile uint32_t *)0x40059520))

#define GPIO_PORTB_AHB_CR_R     (*((volatile uint32_t *)0x40059524))

#define GPIO_PORTB_AHB_AMSEL_R  (*((volatile uint32_t *)0x40059528))

#define GPIO_PORTB_AHB_PCTL_R   (*((volatile uint32_t *)0x4005952C))

#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530))

#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534))


//*****************************************************************************

//

// GPIO registers (PORTC AHB)

//

//*****************************************************************************

#define GPIO_PORTC_AHB_DATA_BITS_R                                            \

                                ((volatile uint32_t *)0x4005A000)

#define GPIO_PORTC_AHB_DATA_R   (*((volatile uint32_t *)0x4005A3FC))

#define GPIO_PORTC_AHB_DIR_R    (*((volatile uint32_t *)0x4005A400))

#define GPIO_PORTC_AHB_IS_R     (*((volatile uint32_t *)0x4005A404))

#define GPIO_PORTC_AHB_IBE_R    (*((volatile uint32_t *)0x4005A408))

#define GPIO_PORTC_AHB_IEV_R    (*((volatile uint32_t *)0x4005A40C))

#define GPIO_PORTC_AHB_IM_R     (*((volatile uint32_t *)0x4005A410))

#define GPIO_PORTC_AHB_RIS_R    (*((volatile uint32_t *)0x4005A414))

#define GPIO_PORTC_AHB_MIS_R    (*((volatile uint32_t *)0x4005A418))

#define GPIO_PORTC_AHB_ICR_R    (*((volatile uint32_t *)0x4005A41C))

#define GPIO_PORTC_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005A420))

#define GPIO_PORTC_AHB_DR2R_R   (*((volatile uint32_t *)0x4005A500))

#define GPIO_PORTC_AHB_DR4R_R   (*((volatile uint32_t *)0x4005A504))

#define GPIO_PORTC_AHB_DR8R_R   (*((volatile uint32_t *)0x4005A508))

#define GPIO_PORTC_AHB_ODR_R    (*((volatile uint32_t *)0x4005A50C))

#define GPIO_PORTC_AHB_PUR_R    (*((volatile uint32_t *)0x4005A510))

#define GPIO_PORTC_AHB_PDR_R    (*((volatile uint32_t *)0x4005A514))

#define GPIO_PORTC_AHB_SLR_R    (*((volatile uint32_t *)0x4005A518))

#define GPIO_PORTC_AHB_DEN_R    (*((volatile uint32_t *)0x4005A51C))

#define GPIO_PORTC_AHB_LOCK_R   (*((volatile uint32_t *)0x4005A520))

#define GPIO_PORTC_AHB_CR_R     (*((volatile uint32_t *)0x4005A524))

#define GPIO_PORTC_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005A528))

#define GPIO_PORTC_AHB_PCTL_R   (*((volatile uint32_t *)0x4005A52C))

#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530))

#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534))


//*****************************************************************************

//

// GPIO registers (PORTD AHB)

//

//*****************************************************************************

#define GPIO_PORTD_AHB_DATA_BITS_R                                            \

                                ((volatile uint32_t *)0x4005B000)

#define GPIO_PORTD_AHB_DATA_R   (*((volatile uint32_t *)0x4005B3FC))

#define GPIO_PORTD_AHB_DIR_R    (*((volatile uint32_t *)0x4005B400))

#define GPIO_PORTD_AHB_IS_R     (*((volatile uint32_t *)0x4005B404))

#define GPIO_PORTD_AHB_IBE_R    (*((volatile uint32_t *)0x4005B408))

#define GPIO_PORTD_AHB_IEV_R    (*((volatile uint32_t *)0x4005B40C))

#define GPIO_PORTD_AHB_IM_R     (*((volatile uint32_t *)0x4005B410))

#define GPIO_PORTD_AHB_RIS_R    (*((volatile uint32_t *)0x4005B414))

#define GPIO_PORTD_AHB_MIS_R    (*((volatile uint32_t *)0x4005B418))

#define GPIO_PORTD_AHB_ICR_R    (*((volatile uint32_t *)0x4005B41C))

#define GPIO_PORTD_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005B420))

#define GPIO_PORTD_AHB_DR2R_R   (*((volatile uint32_t *)0x4005B500))

#define GPIO_PORTD_AHB_DR4R_R   (*((volatile uint32_t *)0x4005B504))

#define GPIO_PORTD_AHB_DR8R_R   (*((volatile uint32_t *)0x4005B508))

#define GPIO_PORTD_AHB_ODR_R    (*((volatile uint32_t *)0x4005B50C))

#define GPIO_PORTD_AHB_PUR_R    (*((volatile uint32_t *)0x4005B510))

#define GPIO_PORTD_AHB_PDR_R    (*((volatile uint32_t *)0x4005B514))

#define GPIO_PORTD_AHB_SLR_R    (*((volatile uint32_t *)0x4005B518))

#define GPIO_PORTD_AHB_DEN_R    (*((volatile uint32_t *)0x4005B51C))

#define GPIO_PORTD_AHB_LOCK_R   (*((volatile uint32_t *)0x4005B520))

#define GPIO_PORTD_AHB_CR_R     (*((volatile uint32_t *)0x4005B524))

#define GPIO_PORTD_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005B528))

#define GPIO_PORTD_AHB_PCTL_R   (*((volatile uint32_t *)0x4005B52C))

#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530))

#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534))


//*****************************************************************************

//

// GPIO registers (PORTE AHB)

//

//*****************************************************************************

#define GPIO_PORTE_AHB_DATA_BITS_R                                            \

                                ((volatile uint32_t *)0x4005C000)

#define GPIO_PORTE_AHB_DATA_R   (*((volatile uint32_t *)0x4005C3FC))

#define GPIO_PORTE_AHB_DIR_R    (*((volatile uint32_t *)0x4005C400))

#define GPIO_PORTE_AHB_IS_R     (*((volatile uint32_t *)0x4005C404))

#define GPIO_PORTE_AHB_IBE_R    (*((volatile uint32_t *)0x4005C408))

#define GPIO_PORTE_AHB_IEV_R    (*((volatile uint32_t *)0x4005C40C))

#define GPIO_PORTE_AHB_IM_R     (*((volatile uint32_t *)0x4005C410))

#define GPIO_PORTE_AHB_RIS_R    (*((volatile uint32_t *)0x4005C414))

#define GPIO_PORTE_AHB_MIS_R    (*((volatile uint32_t *)0x4005C418))

#define GPIO_PORTE_AHB_ICR_R    (*((volatile uint32_t *)0x4005C41C))

#define GPIO_PORTE_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005C420))

#define GPIO_PORTE_AHB_DR2R_R   (*((volatile uint32_t *)0x4005C500))

#define GPIO_PORTE_AHB_DR4R_R   (*((volatile uint32_t *)0x4005C504))

#define GPIO_PORTE_AHB_DR8R_R   (*((volatile uint32_t *)0x4005C508))

#define GPIO_PORTE_AHB_ODR_R    (*((volatile uint32_t *)0x4005C50C))

#define GPIO_PORTE_AHB_PUR_R    (*((volatile uint32_t *)0x4005C510))

#define GPIO_PORTE_AHB_PDR_R    (*((volatile uint32_t *)0x4005C514))

#define GPIO_PORTE_AHB_SLR_R    (*((volatile uint32_t *)0x4005C518))

#define GPIO_PORTE_AHB_DEN_R    (*((volatile uint32_t *)0x4005C51C))

#define GPIO_PORTE_AHB_LOCK_R   (*((volatile uint32_t *)0x4005C520))

#define GPIO_PORTE_AHB_CR_R     (*((volatile uint32_t *)0x4005C524))

#define GPIO_PORTE_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005C528))

#define GPIO_PORTE_AHB_PCTL_R   (*((volatile uint32_t *)0x4005C52C))

#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530))

#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534))


//*****************************************************************************

//

// GPIO registers (PORTF AHB)

//

//*****************************************************************************

#define GPIO_PORTF_AHB_DATA_BITS_R                                            \

                                ((volatile uint32_t *)0x4005D000)

#define GPIO_PORTF_AHB_DATA_R   (*((volatile uint32_t *)0x4005D3FC))

#define GPIO_PORTF_AHB_DIR_R    (*((volatile uint32_t *)0x4005D400))

#define GPIO_PORTF_AHB_IS_R     (*((volatile uint32_t *)0x4005D404))

#define GPIO_PORTF_AHB_IBE_R    (*((volatile uint32_t *)0x4005D408))

#define GPIO_PORTF_AHB_IEV_R    (*((volatile uint32_t *)0x4005D40C))

#define GPIO_PORTF_AHB_IM_R     (*((volatile uint32_t *)0x4005D410))

#define GPIO_PORTF_AHB_RIS_R    (*((volatile uint32_t *)0x4005D414))

#define GPIO_PORTF_AHB_MIS_R    (*((volatile uint32_t *)0x4005D418))

#define GPIO_PORTF_AHB_ICR_R    (*((volatile uint32_t *)0x4005D41C))

#define GPIO_PORTF_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005D420))

#define GPIO_PORTF_AHB_DR2R_R   (*((volatile uint32_t *)0x4005D500))

#define GPIO_PORTF_AHB_DR4R_R   (*((volatile uint32_t *)0x4005D504))

#define GPIO_PORTF_AHB_DR8R_R   (*((volatile uint32_t *)0x4005D508))

#define GPIO_PORTF_AHB_ODR_R    (*((volatile uint32_t *)0x4005D50C))

#define GPIO_PORTF_AHB_PUR_R    (*((volatile uint32_t *)0x4005D510))

#define GPIO_PORTF_AHB_PDR_R    (*((volatile uint32_t *)0x4005D514))

#define GPIO_PORTF_AHB_SLR_R    (*((volatile uint32_t *)0x4005D518))

#define GPIO_PORTF_AHB_DEN_R    (*((volatile uint32_t *)0x4005D51C))

#define GPIO_PORTF_AHB_LOCK_R   (*((volatile uint32_t *)0x4005D520))

#define GPIO_PORTF_AHB_CR_R     (*((volatile uint32_t *)0x4005D524))

#define GPIO_PORTF_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005D528))

#define GPIO_PORTF_AHB_PCTL_R   (*((volatile uint32_t *)0x4005D52C))

#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530))

#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534))


//*****************************************************************************

//

// GPIO registers (PORTG AHB)

//

//*****************************************************************************

#define GPIO_PORTG_AHB_DATA_BITS_R                                            \

                                ((volatile uint32_t *)0x4005E000)

#define GPIO_PORTG_AHB_DATA_R   (*((volatile uint32_t *)0x4005E3FC))

#define GPIO_PORTG_AHB_DIR_R    (*((volatile uint32_t *)0x4005E400))

#define GPIO_PORTG_AHB_IS_R     (*((volatile uint32_t *)0x4005E404))

#define GPIO_PORTG_AHB_IBE_R    (*((volatile uint32_t *)0x4005E408))

#define GPIO_PORTG_AHB_IEV_R    (*((volatile uint32_t *)0x4005E40C))

#define GPIO_PORTG_AHB_IM_R     (*((volatile uint32_t *)0x4005E410))

#define GPIO_PORTG_AHB_RIS_R    (*((volatile uint32_t *)0x4005E414))

#define GPIO_PORTG_AHB_MIS_R    (*((volatile uint32_t *)0x4005E418))

#define GPIO_PORTG_AHB_ICR_R    (*((volatile uint32_t *)0x4005E41C))

#define GPIO_PORTG_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005E420))

#define GPIO_PORTG_AHB_DR2R_R   (*((volatile uint32_t *)0x4005E500))

#define GPIO_PORTG_AHB_DR4R_R   (*((volatile uint32_t *)0x4005E504))

#define GPIO_PORTG_AHB_DR8R_R   (*((volatile uint32_t *)0x4005E508))

#define GPIO_PORTG_AHB_ODR_R    (*((volatile uint32_t *)0x4005E50C))

#define GPIO_PORTG_AHB_PUR_R    (*((volatile uint32_t *)0x4005E510))

#define GPIO_PORTG_AHB_PDR_R    (*((volatile uint32_t *)0x4005E514))

#define GPIO_PORTG_AHB_SLR_R    (*((volatile uint32_t *)0x4005E518))

#define GPIO_PORTG_AHB_DEN_R    (*((volatile uint32_t *)0x4005E51C))

#define GPIO_PORTG_AHB_LOCK_R   (*((volatile uint32_t *)0x4005E520))

#define GPIO_PORTG_AHB_CR_R     (*((volatile uint32_t *)0x4005E524))

#define GPIO_PORTG_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005E528))

#define GPIO_PORTG_AHB_PCTL_R   (*((volatile uint32_t *)0x4005E52C))

#define GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530))

#define GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534))


//*****************************************************************************

//

// EEPROM registers (EEPROM)

//

//*****************************************************************************

#define EEPROM_EESIZE_R         (*((volatile uint32_t *)0x400AF000))

#define EEPROM_EEBLOCK_R        (*((volatile uint32_t *)0x400AF004))

#define EEPROM_EEOFFSET_R       (*((volatile uint32_t *)0x400AF008))

#define EEPROM_EERDWR_R         (*((volatile uint32_t *)0x400AF010))

#define EEPROM_EERDWRINC_R      (*((volatile uint32_t *)0x400AF014))

#define EEPROM_EEDONE_R         (*((volatile uint32_t *)0x400AF018))

#define EEPROM_EESUPP_R         (*((volatile uint32_t *)0x400AF01C))

#define EEPROM_EEUNLOCK_R       (*((volatile uint32_t *)0x400AF020))

#define EEPROM_EEPROT_R         (*((volatile uint32_t *)0x400AF030))

#define EEPROM_EEPASS0_R        (*((volatile uint32_t *)0x400AF034))

#define EEPROM_EEPASS1_R        (*((volatile uint32_t *)0x400AF038))

#define EEPROM_EEPASS2_R        (*((volatile uint32_t *)0x400AF03C))

#define EEPROM_EEINT_R          (*((volatile uint32_t *)0x400AF040))

#define EEPROM_EEHIDE_R         (*((volatile uint32_t *)0x400AF050))

#define EEPROM_EEDBGME_R        (*((volatile uint32_t *)0x400AF080))

#define EEPROM_PP_R             (*((volatile uint32_t *)0x400AFFC0))


//*****************************************************************************

//

// I2C registers (I2C4)

//

//*****************************************************************************

#define I2C4_MSA_R              (*((volatile uint32_t *)0x400C0000))

#define I2C4_MCS_R              (*((volatile uint32_t *)0x400C0004))

#define I2C4_MDR_R              (*((volatile uint32_t *)0x400C0008))

#define I2C4_MTPR_R             (*((volatile uint32_t *)0x400C000C))

#define I2C4_MIMR_R             (*((volatile uint32_t *)0x400C0010))

#define I2C4_MRIS_R             (*((volatile uint32_t *)0x400C0014))

#define I2C4_MMIS_R             (*((volatile uint32_t *)0x400C0018))

#define I2C4_MICR_R             (*((volatile uint32_t *)0x400C001C))

#define I2C4_MCR_R              (*((volatile uint32_t *)0x400C0020))

#define I2C4_MCLKOCNT_R         (*((volatile uint32_t *)0x400C0024))

#define I2C4_MBMON_R            (*((volatile uint32_t *)0x400C002C))

#define I2C4_MCR2_R             (*((volatile uint32_t *)0x400C0038))

#define I2C4_SOAR_R             (*((volatile uint32_t *)0x400C0800))

#define I2C4_SCSR_R             (*((volatile uint32_t *)0x400C0804))

#define I2C4_SDR_R              (*((volatile uint32_t *)0x400C0808))

#define I2C4_SIMR_R             (*((volatile uint32_t *)0x400C080C))

#define I2C4_SRIS_R             (*((volatile uint32_t *)0x400C0810))

#define I2C4_SMIS_R             (*((volatile uint32_t *)0x400C0814))

#define I2C4_SICR_R             (*((volatile uint32_t *)0x400C0818))

#define I2C4_SOAR2_R            (*((volatile uint32_t *)0x400C081C))

#define I2C4_SACKCTL_R          (*((volatile uint32_t *)0x400C0820))

#define I2C4_PP_R               (*((volatile uint32_t *)0x400C0FC0))

#define I2C4_PC_R               (*((volatile uint32_t *)0x400C0FC4))


//*****************************************************************************

//

// I2C registers (I2C5)

//

//*****************************************************************************

#define I2C5_MSA_R              (*((volatile uint32_t *)0x400C1000))

#define I2C5_MCS_R              (*((volatile uint32_t *)0x400C1004))

#define I2C5_MDR_R              (*((volatile uint32_t *)0x400C1008))

#define I2C5_MTPR_R             (*((volatile uint32_t *)0x400C100C))

#define I2C5_MIMR_R             (*((volatile uint32_t *)0x400C1010))

#define I2C5_MRIS_R             (*((volatile uint32_t *)0x400C1014))

#define I2C5_MMIS_R             (*((volatile uint32_t *)0x400C1018))

#define I2C5_MICR_R             (*((volatile uint32_t *)0x400C101C))

#define I2C5_MCR_R              (*((volatile uint32_t *)0x400C1020))

#define I2C5_MCLKOCNT_R         (*((volatile uint32_t *)0x400C1024))

#define I2C5_MBMON_R            (*((volatile uint32_t *)0x400C102C))

#define I2C5_MCR2_R             (*((volatile uint32_t *)0x400C1038))

#define I2C5_SOAR_R             (*((volatile uint32_t *)0x400C1800))

#define I2C5_SCSR_R             (*((volatile uint32_t *)0x400C1804))

#define I2C5_SDR_R              (*((volatile uint32_t *)0x400C1808))

#define I2C5_SIMR_R             (*((volatile uint32_t *)0x400C180C))

#define I2C5_SRIS_R             (*((volatile uint32_t *)0x400C1810))

#define I2C5_SMIS_R             (*((volatile uint32_t *)0x400C1814))

#define I2C5_SICR_R             (*((volatile uint32_t *)0x400C1818))

#define I2C5_SOAR2_R            (*((volatile uint32_t *)0x400C181C))

#define I2C5_SACKCTL_R          (*((volatile uint32_t *)0x400C1820))

#define I2C5_PP_R               (*((volatile uint32_t *)0x400C1FC0))

#define I2C5_PC_R               (*((volatile uint32_t *)0x400C1FC4))


//*****************************************************************************

//

// System Exception Module registers (SYSEXC)

//

//*****************************************************************************

#define SYSEXC_RIS_R            (*((volatile uint32_t *)0x400F9000))

#define SYSEXC_IM_R             (*((volatile uint32_t *)0x400F9004))

#define SYSEXC_MIS_R            (*((volatile uint32_t *)0x400F9008))

#define SYSEXC_IC_R             (*((volatile uint32_t *)0x400F900C))


//*****************************************************************************

//

// FLASH registers (FLASH CTRL)

//

//*****************************************************************************

#define FLASH_FMA_R             (*((volatile uint32_t *)0x400FD000))

#define FLASH_FMD_R             (*((volatile uint32_t *)0x400FD004))

#define FLASH_FMC_R             (*((volatile uint32_t *)0x400FD008))

#define FLASH_FCRIS_R           (*((volatile uint32_t *)0x400FD00C))

#define FLASH_FCIM_R            (*((volatile uint32_t *)0x400FD010))

#define FLASH_FCMISC_R          (*((volatile uint32_t *)0x400FD014))

#define FLASH_FMC2_R            (*((volatile uint32_t *)0x400FD020))

#define FLASH_FWBVAL_R          (*((volatile uint32_t *)0x400FD030))

#define FLASH_FWBN_R            (*((volatile uint32_t *)0x400FD100))

#define FLASH_FSIZE_R           (*((volatile uint32_t *)0x400FDFC0))

#define FLASH_SSIZE_R           (*((volatile uint32_t *)0x400FDFC4))

#define FLASH_ROMSWMAP_R        (*((volatile uint32_t *)0x400FDFCC))

#define FLASH_RMCTL_R           (*((volatile uint32_t *)0x400FE0F0))

#define FLASH_BOOTCFG_R         (*((volatile uint32_t *)0x400FE1D0))

#define FLASH_USERREG0_R        (*((volatile uint32_t *)0x400FE1E0))

#define FLASH_USERREG1_R        (*((volatile uint32_t *)0x400FE1E4))

#define FLASH_USERREG2_R        (*((volatile uint32_t *)0x400FE1E8))

#define FLASH_USERREG3_R        (*((volatile uint32_t *)0x400FE1EC))

#define FLASH_FMPRE0_R          (*((volatile uint32_t *)0x400FE200))

#define FLASH_FMPRE1_R          (*((volatile uint32_t *)0x400FE204))

#define FLASH_FMPPE0_R          (*((volatile uint32_t *)0x400FE400))

#define FLASH_FMPPE1_R          (*((volatile uint32_t *)0x400FE404))


//*****************************************************************************

//

// System Control registers (SYSCTL)

//

//*****************************************************************************

#define SYSCTL_DID0_R           (*((volatile uint32_t *)0x400FE000))

#define SYSCTL_DID1_R           (*((volatile uint32_t *)0x400FE004))

#define SYSCTL_DC0_R            (*((volatile uint32_t *)0x400FE008))

#define SYSCTL_DC1_R            (*((volatile uint32_t *)0x400FE010))

#define SYSCTL_DC2_R            (*((volatile uint32_t *)0x400FE014))

#define SYSCTL_DC3_R            (*((volatile uint32_t *)0x400FE018))

#define SYSCTL_DC4_R            (*((volatile uint32_t *)0x400FE01C))

#define SYSCTL_DC5_R            (*((volatile uint32_t *)0x400FE020))

#define SYSCTL_DC6_R            (*((volatile uint32_t *)0x400FE024))

#define SYSCTL_DC7_R            (*((volatile uint32_t *)0x400FE028))

#define SYSCTL_DC8_R            (*((volatile uint32_t *)0x400FE02C))

#define SYSCTL_PBORCTL_R        (*((volatile uint32_t *)0x400FE030))

#define SYSCTL_SRCR0_R          (*((volatile uint32_t *)0x400FE040))

#define SYSCTL_SRCR1_R          (*((volatile uint32_t *)0x400FE044))

#define SYSCTL_SRCR2_R          (*((volatile uint32_t *)0x400FE048))

#define SYSCTL_RIS_R            (*((volatile uint32_t *)0x400FE050))

#define SYSCTL_IMC_R            (*((volatile uint32_t *)0x400FE054))

#define SYSCTL_MISC_R           (*((volatile uint32_t *)0x400FE058))

#define SYSCTL_RESC_R           (*((volatile uint32_t *)0x400FE05C))

#define SYSCTL_RCC_R            (*((volatile uint32_t *)0x400FE060))

#define SYSCTL_GPIOHBCTL_R      (*((volatile uint32_t *)0x400FE06C))

#define SYSCTL_RCC2_R           (*((volatile uint32_t *)0x400FE070))

#define SYSCTL_MOSCCTL_R        (*((volatile uint32_t *)0x400FE07C))

#define SYSCTL_RCGC0_R          (*((volatile uint32_t *)0x400FE100))

#define SYSCTL_RCGC1_R          (*((volatile uint32_t *)0x400FE104))

#define SYSCTL_RCGC2_R          (*((volatile uint32_t *)0x400FE108))

#define SYSCTL_SCGC0_R          (*((volatile uint32_t *)0x400FE110))

#define SYSCTL_SCGC1_R          (*((volatile uint32_t *)0x400FE114))

#define SYSCTL_SCGC2_R          (*((volatile uint32_t *)0x400FE118))

#define SYSCTL_DCGC0_R          (*((volatile uint32_t *)0x400FE120))

#define SYSCTL_DCGC1_R          (*((volatile uint32_t *)0x400FE124))

#define SYSCTL_DCGC2_R          (*((volatile uint32_t *)0x400FE128))

#define SYSCTL_DSLPCLKCFG_R     (*((volatile uint32_t *)0x400FE144))

#define SYSCTL_SYSPROP_R        (*((volatile uint32_t *)0x400FE14C))

#define SYSCTL_PIOSCCAL_R       (*((volatile uint32_t *)0x400FE150))

#define SYSCTL_PLLFREQ0_R       (*((volatile uint32_t *)0x400FE160))

#define SYSCTL_PLLFREQ1_R       (*((volatile uint32_t *)0x400FE164))

#define SYSCTL_PLLSTAT_R        (*((volatile uint32_t *)0x400FE168))

#define SYSCTL_SLPPWRCFG_R      (*((volatile uint32_t *)0x400FE188))

#define SYSCTL_DSLPPWRCFG_R     (*((volatile uint32_t *)0x400FE18C))

#define SYSCTL_DC9_R            (*((volatile uint32_t *)0x400FE190))

#define SYSCTL_NVMSTAT_R        (*((volatile uint32_t *)0x400FE1A0))

#define SYSCTL_LDOSPCTL_R       (*((volatile uint32_t *)0x400FE1B4))

#define SYSCTL_LDODPCTL_R       (*((volatile uint32_t *)0x400FE1BC))

#define SYSCTL_PPWD_R           (*((volatile uint32_t *)0x400FE300))

#define SYSCTL_PPTIMER_R        (*((volatile uint32_t *)0x400FE304))

#define SYSCTL_PPGPIO_R         (*((volatile uint32_t *)0x400FE308))

#define SYSCTL_PPDMA_R          (*((volatile uint32_t *)0x400FE30C))

#define SYSCTL_PPHIB_R          (*((volatile uint32_t *)0x400FE314))

#define SYSCTL_PPUART_R         (*((volatile uint32_t *)0x400FE318))

#define SYSCTL_PPSSI_R          (*((volatile uint32_t *)0x400FE31C))

#define SYSCTL_PPI2C_R          (*((volatile uint32_t *)0x400FE320))

#define SYSCTL_PPUSB_R          (*((volatile uint32_t *)0x400FE328))

#define SYSCTL_PPCAN_R          (*((volatile uint32_t *)0x400FE334))

#define SYSCTL_PPADC_R          (*((volatile uint32_t *)0x400FE338))

#define SYSCTL_PPACMP_R         (*((volatile uint32_t *)0x400FE33C))

#define SYSCTL_PPPWM_R          (*((volatile uint32_t *)0x400FE340))

#define SYSCTL_PPQEI_R          (*((volatile uint32_t *)0x400FE344))

#define SYSCTL_PPEEPROM_R       (*((volatile uint32_t *)0x400FE358))

#define SYSCTL_PPWTIMER_R       (*((volatile uint32_t *)0x400FE35C))

#define SYSCTL_SRWD_R           (*((volatile uint32_t *)0x400FE500))

#define SYSCTL_SRTIMER_R        (*((volatile uint32_t *)0x400FE504))

#define SYSCTL_SRGPIO_R         (*((volatile uint32_t *)0x400FE508))

#define SYSCTL_SRDMA_R          (*((volatile uint32_t *)0x400FE50C))

#define SYSCTL_SRUART_R         (*((volatile uint32_t *)0x400FE518))

#define SYSCTL_SRSSI_R          (*((volatile uint32_t *)0x400FE51C))

#define SYSCTL_SRI2C_R          (*((volatile uint32_t *)0x400FE520))

#define SYSCTL_SRUSB_R          (*((volatile uint32_t *)0x400FE528))

#define SYSCTL_SRCAN_R          (*((volatile uint32_t *)0x400FE534))

#define SYSCTL_SRADC_R          (*((volatile uint32_t *)0x400FE538))

#define SYSCTL_SRACMP_R         (*((volatile uint32_t *)0x400FE53C))

#define SYSCTL_SRPWM_R          (*((volatile uint32_t *)0x400FE540))

#define SYSCTL_SRQEI_R          (*((volatile uint32_t *)0x400FE544))

#define SYSCTL_SREEPROM_R       (*((volatile uint32_t *)0x400FE558))

#define SYSCTL_SRWTIMER_R       (*((volatile uint32_t *)0x400FE55C))

#define SYSCTL_RCGCWD_R         (*((volatile uint32_t *)0x400FE600))

#define SYSCTL_RCGCTIMER_R      (*((volatile uint32_t *)0x400FE604))

#define SYSCTL_RCGCGPIO_R       (*((volatile uint32_t *)0x400FE608))

#define SYSCTL_RCGCDMA_R        (*((volatile uint32_t *)0x400FE60C))

#define SYSCTL_RCGCUART_R       (*((volatile uint32_t *)0x400FE618))

#define SYSCTL_RCGCSSI_R        (*((volatile uint32_t *)0x400FE61C))

#define SYSCTL_RCGCI2C_R        (*((volatile uint32_t *)0x400FE620))

#define SYSCTL_RCGCUSB_R        (*((volatile uint32_t *)0x400FE628))

#define SYSCTL_RCGCCAN_R        (*((volatile uint32_t *)0x400FE634))

#define SYSCTL_RCGCADC_R        (*((volatile uint32_t *)0x400FE638))

#define SYSCTL_RCGCACMP_R       (*((volatile uint32_t *)0x400FE63C))

#define SYSCTL_RCGCPWM_R        (*((volatile uint32_t *)0x400FE640))

#define SYSCTL_RCGCQEI_R        (*((volatile uint32_t *)0x400FE644))

#define SYSCTL_RCGCEEPROM_R     (*((volatile uint32_t *)0x400FE658))

#define SYSCTL_RCGCWTIMER_R     (*((volatile uint32_t *)0x400FE65C))

#define SYSCTL_SCGCWD_R         (*((volatile uint32_t *)0x400FE700))

#define SYSCTL_SCGCTIMER_R      (*((volatile uint32_t *)0x400FE704))

#define SYSCTL_SCGCGPIO_R       (*((volatile uint32_t *)0x400FE708))

#define SYSCTL_SCGCDMA_R        (*((volatile uint32_t *)0x400FE70C))

#define SYSCTL_SCGCUART_R       (*((volatile uint32_t *)0x400FE718))

#define SYSCTL_SCGCSSI_R        (*((volatile uint32_t *)0x400FE71C))

#define SYSCTL_SCGCI2C_R        (*((volatile uint32_t *)0x400FE720))

#define SYSCTL_SCGCUSB_R        (*((volatile uint32_t *)0x400FE728))

#define SYSCTL_SCGCCAN_R        (*((volatile uint32_t *)0x400FE734))

#define SYSCTL_SCGCADC_R        (*((volatile uint32_t *)0x400FE738))

#define SYSCTL_SCGCACMP_R       (*((volatile uint32_t *)0x400FE73C))

#define SYSCTL_SCGCPWM_R        (*((volatile uint32_t *)0x400FE740))

#define SYSCTL_SCGCQEI_R        (*((volatile uint32_t *)0x400FE744))

#define SYSCTL_SCGCEEPROM_R     (*((volatile uint32_t *)0x400FE758))

#define SYSCTL_SCGCWTIMER_R     (*((volatile uint32_t *)0x400FE75C))

#define SYSCTL_DCGCWD_R         (*((volatile uint32_t *)0x400FE800))

#define SYSCTL_DCGCTIMER_R      (*((volatile uint32_t *)0x400FE804))

#define SYSCTL_DCGCGPIO_R       (*((volatile uint32_t *)0x400FE808))

#define SYSCTL_DCGCDMA_R        (*((volatile uint32_t *)0x400FE80C))

#define SYSCTL_DCGCUART_R       (*((volatile uint32_t *)0x400FE818))

#define SYSCTL_DCGCSSI_R        (*((volatile uint32_t *)0x400FE81C))

#define SYSCTL_DCGCI2C_R        (*((volatile uint32_t *)0x400FE820))

#define SYSCTL_DCGCUSB_R        (*((volatile uint32_t *)0x400FE828))

#define SYSCTL_DCGCCAN_R        (*((volatile uint32_t *)0x400FE834))

#define SYSCTL_DCGCADC_R        (*((volatile uint32_t *)0x400FE838))

#define SYSCTL_DCGCACMP_R       (*((volatile uint32_t *)0x400FE83C))

#define SYSCTL_DCGCPWM_R        (*((volatile uint32_t *)0x400FE840))

#define SYSCTL_DCGCQEI_R        (*((volatile uint32_t *)0x400FE844))

#define SYSCTL_DCGCEEPROM_R     (*((volatile uint32_t *)0x400FE858))

#define SYSCTL_DCGCWTIMER_R     (*((volatile uint32_t *)0x400FE85C))

#define SYSCTL_PRWD_R           (*((volatile uint32_t *)0x400FEA00))

#define SYSCTL_PRTIMER_R        (*((volatile uint32_t *)0x400FEA04))

#define SYSCTL_PRGPIO_R         (*((volatile uint32_t *)0x400FEA08))

#define SYSCTL_PRDMA_R          (*((volatile uint32_t *)0x400FEA0C))

#define SYSCTL_PRUART_R         (*((volatile uint32_t *)0x400FEA18))

#define SYSCTL_PRSSI_R          (*((volatile uint32_t *)0x400FEA1C))

#define SYSCTL_PRI2C_R          (*((volatile uint32_t *)0x400FEA20))

#define SYSCTL_PRUSB_R          (*((volatile uint32_t *)0x400FEA28))

#define SYSCTL_PRCAN_R          (*((volatile uint32_t *)0x400FEA34))

#define SYSCTL_PRADC_R          (*((volatile uint32_t *)0x400FEA38))

#define SYSCTL_PRACMP_R         (*((volatile uint32_t *)0x400FEA3C))

#define SYSCTL_PRPWM_R          (*((volatile uint32_t *)0x400FEA40))

#define SYSCTL_PRQEI_R          (*((volatile uint32_t *)0x400FEA44))

#define SYSCTL_PREEPROM_R       (*((volatile uint32_t *)0x400FEA58))

#define SYSCTL_PRWTIMER_R       (*((volatile uint32_t *)0x400FEA5C))


//*****************************************************************************

//

// Micro Direct Memory Access registers (UDMA)

//

//*****************************************************************************

#define UDMA_STAT_R             (*((volatile uint32_t *)0x400FF000))

#define UDMA_CFG_R              (*((volatile uint32_t *)0x400FF004))

#define UDMA_CTLBASE_R          (*((volatile uint32_t *)0x400FF008))

#define UDMA_ALTBASE_R          (*((volatile uint32_t *)0x400FF00C))

#define UDMA_WAITSTAT_R         (*((volatile uint32_t *)0x400FF010))

#define UDMA_SWREQ_R            (*((volatile uint32_t *)0x400FF014))

#define UDMA_USEBURSTSET_R      (*((volatile uint32_t *)0x400FF018))

#define UDMA_USEBURSTCLR_R      (*((volatile uint32_t *)0x400FF01C))

#define UDMA_REQMASKSET_R       (*((volatile uint32_t *)0x400FF020))

#define UDMA_REQMASKCLR_R       (*((volatile uint32_t *)0x400FF024))

#define UDMA_ENASET_R           (*((volatile uint32_t *)0x400FF028))

#define UDMA_ENACLR_R           (*((volatile uint32_t *)0x400FF02C))

#define UDMA_ALTSET_R           (*((volatile uint32_t *)0x400FF030))

#define UDMA_ALTCLR_R           (*((volatile uint32_t *)0x400FF034))

#define UDMA_PRIOSET_R          (*((volatile uint32_t *)0x400FF038))

#define UDMA_PRIOCLR_R          (*((volatile uint32_t *)0x400FF03C))

#define UDMA_ERRCLR_R           (*((volatile uint32_t *)0x400FF04C))

#define UDMA_CHASGN_R           (*((volatile uint32_t *)0x400FF500))

#define UDMA_CHIS_R             (*((volatile uint32_t *)0x400FF504))

#define UDMA_CHMAP0_R           (*((volatile uint32_t *)0x400FF510))

#define UDMA_CHMAP1_R           (*((volatile uint32_t *)0x400FF514))

#define UDMA_CHMAP2_R           (*((volatile uint32_t *)0x400FF518))

#define UDMA_CHMAP3_R           (*((volatile uint32_t *)0x400FF51C))


//*****************************************************************************

//

// Micro Direct Memory Access (uDMA) offsets (UDMA)

//

//*****************************************************************************

#define UDMA_SRCENDP            0x00000000  // DMA Channel Source Address End

                                            // Pointer

#define UDMA_DSTENDP            0x00000004  // DMA Channel Destination Address

                                            // End Pointer

#define UDMA_CHCTL              0x00000008  // DMA Channel Control Word


//*****************************************************************************

//

// NVIC registers (NVIC)

//

//*****************************************************************************

#define NVIC_ACTLR_R            (*((volatile uint32_t *)0xE000E008))

#define NVIC_ST_CTRL_R          (*((volatile uint32_t *)0xE000E010))

#define NVIC_ST_RELOAD_R        (*((volatile uint32_t *)0xE000E014))

#define NVIC_ST_CURRENT_R       (*((volatile uint32_t *)0xE000E018))

#define NVIC_EN0_R              (*((volatile uint32_t *)0xE000E100))

#define NVIC_EN1_R              (*((volatile uint32_t *)0xE000E104))

#define NVIC_EN2_R              (*((volatile uint32_t *)0xE000E108))

#define NVIC_EN3_R              (*((volatile uint32_t *)0xE000E10C))

#define NVIC_EN4_R              (*((volatile uint32_t *)0xE000E110))

#define NVIC_DIS0_R             (*((volatile uint32_t *)0xE000E180))

#define NVIC_DIS1_R             (*((volatile uint32_t *)0xE000E184))

#define NVIC_DIS2_R             (*((volatile uint32_t *)0xE000E188))

#define NVIC_DIS3_R             (*((volatile uint32_t *)0xE000E18C))

#define NVIC_DIS4_R             (*((volatile uint32_t *)0xE000E190))

#define NVIC_PEND0_R            (*((volatile uint32_t *)0xE000E200))

#define NVIC_PEND1_R            (*((volatile uint32_t *)0xE000E204))

#define NVIC_PEND2_R            (*((volatile uint32_t *)0xE000E208))

#define NVIC_PEND3_R            (*((volatile uint32_t *)0xE000E20C))

#define NVIC_PEND4_R            (*((volatile uint32_t *)0xE000E210))

#define NVIC_UNPEND0_R          (*((volatile uint32_t *)0xE000E280))

#define NVIC_UNPEND1_R          (*((volatile uint32_t *)0xE000E284))

#define NVIC_UNPEND2_R          (*((volatile uint32_t *)0xE000E288))

#define NVIC_UNPEND3_R          (*((volatile uint32_t *)0xE000E28C))

#define NVIC_UNPEND4_R          (*((volatile uint32_t *)0xE000E290))

#define NVIC_ACTIVE0_R          (*((volatile uint32_t *)0xE000E300))

#define NVIC_ACTIVE1_R          (*((volatile uint32_t *)0xE000E304))

#define NVIC_ACTIVE2_R          (*((volatile uint32_t *)0xE000E308))

#define NVIC_ACTIVE3_R          (*((volatile uint32_t *)0xE000E30C))

#define NVIC_ACTIVE4_R          (*((volatile uint32_t *)0xE000E310))

#define NVIC_PRI0_R             (*((volatile uint32_t *)0xE000E400))

#define NVIC_PRI1_R             (*((volatile uint32_t *)0xE000E404))

#define NVIC_PRI2_R             (*((volatile uint32_t *)0xE000E408))

#define NVIC_PRI3_R             (*((volatile uint32_t *)0xE000E40C))

#define NVIC_PRI4_R             (*((volatile uint32_t *)0xE000E410))

#define NVIC_PRI5_R             (*((volatile uint32_t *)0xE000E414))

#define NVIC_PRI6_R             (*((volatile uint32_t *)0xE000E418))

#define NVIC_PRI7_R             (*((volatile uint32_t *)0xE000E41C))

#define NVIC_PRI8_R             (*((volatile uint32_t *)0xE000E420))

#define NVIC_PRI9_R             (*((volatile uint32_t *)0xE000E424))

#define NVIC_PRI10_R            (*((volatile uint32_t *)0xE000E428))

#define NVIC_PRI11_R            (*((volatile uint32_t *)0xE000E42C))

#define NVIC_PRI12_R            (*((volatile uint32_t *)0xE000E430))

#define NVIC_PRI13_R            (*((volatile uint32_t *)0xE000E434))

#define NVIC_PRI14_R            (*((volatile uint32_t *)0xE000E438))

#define NVIC_PRI15_R            (*((volatile uint32_t *)0xE000E43C))

#define NVIC_PRI16_R            (*((volatile uint32_t *)0xE000E440))

#define NVIC_PRI17_R            (*((volatile uint32_t *)0xE000E444))

#define NVIC_PRI18_R            (*((volatile uint32_t *)0xE000E448))

#define NVIC_PRI19_R            (*((volatile uint32_t *)0xE000E44C))

#define NVIC_PRI20_R            (*((volatile uint32_t *)0xE000E450))

#define NVIC_PRI21_R            (*((volatile uint32_t *)0xE000E454))

#define NVIC_PRI22_R            (*((volatile uint32_t *)0xE000E458))

#define NVIC_PRI23_R            (*((volatile uint32_t *)0xE000E45C))

#define NVIC_PRI24_R            (*((volatile uint32_t *)0xE000E460))

#define NVIC_PRI25_R            (*((volatile uint32_t *)0xE000E464))

#define NVIC_PRI26_R            (*((volatile uint32_t *)0xE000E468))

#define NVIC_PRI27_R            (*((volatile uint32_t *)0xE000E46C))

#define NVIC_PRI28_R            (*((volatile uint32_t *)0xE000E470))

#define NVIC_PRI29_R            (*((volatile uint32_t *)0xE000E474))

#define NVIC_PRI30_R            (*((volatile uint32_t *)0xE000E478))

#define NVIC_PRI31_R            (*((volatile uint32_t *)0xE000E47C))

#define NVIC_PRI32_R            (*((volatile uint32_t *)0xE000E480))

#define NVIC_PRI33_R            (*((volatile uint32_t *)0xE000E484))

#define NVIC_PRI34_R            (*((volatile uint32_t *)0xE000E488))

#define NVIC_CPUID_R            (*((volatile uint32_t *)0xE000ED00))

#define NVIC_INT_CTRL_R         (*((volatile uint32_t *)0xE000ED04))

#define NVIC_VTABLE_R           (*((volatile uint32_t *)0xE000ED08))

#define NVIC_APINT_R            (*((volatile uint32_t *)0xE000ED0C))

#define NVIC_SYS_CTRL_R         (*((volatile uint32_t *)0xE000ED10))

#define NVIC_CFG_CTRL_R         (*((volatile uint32_t *)0xE000ED14))

#define NVIC_SYS_PRI1_R         (*((volatile uint32_t *)0xE000ED18))

#define NVIC_SYS_PRI2_R         (*((volatile uint32_t *)0xE000ED1C))

#define NVIC_SYS_PRI3_R         (*((volatile uint32_t *)0xE000ED20))

#define NVIC_SYS_HND_CTRL_R     (*((volatile uint32_t *)0xE000ED24))

#define NVIC_FAULT_STAT_R       (*((volatile uint32_t *)0xE000ED28))

#define NVIC_HFAULT_STAT_R      (*((volatile uint32_t *)0xE000ED2C))

#define NVIC_DEBUG_STAT_R       (*((volatile uint32_t *)0xE000ED30))

#define NVIC_MM_ADDR_R          (*((volatile uint32_t *)0xE000ED34))

#define NVIC_FAULT_ADDR_R       (*((volatile uint32_t *)0xE000ED38))

#define NVIC_CPAC_R             (*((volatile uint32_t *)0xE000ED88))

#define NVIC_MPU_TYPE_R         (*((volatile uint32_t *)0xE000ED90))

#define NVIC_MPU_CTRL_R         (*((volatile uint32_t *)0xE000ED94))

#define NVIC_MPU_NUMBER_R       (*((volatile uint32_t *)0xE000ED98))

#define NVIC_MPU_BASE_R         (*((volatile uint32_t *)0xE000ED9C))

#define NVIC_MPU_ATTR_R         (*((volatile uint32_t *)0xE000EDA0))

#define NVIC_MPU_BASE1_R        (*((volatile uint32_t *)0xE000EDA4))

#define NVIC_MPU_ATTR1_R        (*((volatile uint32_t *)0xE000EDA8))

#define NVIC_MPU_BASE2_R        (*((volatile uint32_t *)0xE000EDAC))

#define NVIC_MPU_ATTR2_R        (*((volatile uint32_t *)0xE000EDB0))

#define NVIC_MPU_BASE3_R        (*((volatile uint32_t *)0xE000EDB4))

#define NVIC_MPU_ATTR3_R        (*((volatile uint32_t *)0xE000EDB8))

#define NVIC_DBG_CTRL_R         (*((volatile uint32_t *)0xE000EDF0))

#define NVIC_DBG_XFER_R         (*((volatile uint32_t *)0xE000EDF4))

#define NVIC_DBG_DATA_R         (*((volatile uint32_t *)0xE000EDF8))

#define NVIC_DBG_INT_R          (*((volatile uint32_t *)0xE000EDFC))

#define NVIC_SW_TRIG_R          (*((volatile uint32_t *)0xE000EF00))

#define NVIC_FPCC_R             (*((volatile uint32_t *)0xE000EF34))

#define NVIC_FPCA_R             (*((volatile uint32_t *)0xE000EF38))

#define NVIC_FPDSC_R            (*((volatile uint32_t *)0xE000EF3C))


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_LOAD register.

//

//*****************************************************************************

#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value

#define WDT_LOAD_S              0


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_VALUE register.

//

//*****************************************************************************

#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value

#define WDT_VALUE_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_CTL register.

//

//*****************************************************************************

#define WDT_CTL_WRC             0x80000000  // Write Complete

#define WDT_CTL_INTTYPE         0x00000004  // Watchdog Interrupt Type

#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable

#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_ICR register.

//

//*****************************************************************************

#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear

#define WDT_ICR_S               0


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_RIS register.

//

//*****************************************************************************

#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_MIS register.

//

//*****************************************************************************

#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_TEST register.

//

//*****************************************************************************

#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the WDT_O_LOCK register.

//

//*****************************************************************************

#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock

#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked

#define WDT_LOCK_LOCKED         0x00000001  // Locked

#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_O_IM register.

//

//*****************************************************************************

#define GPIO_IM_GPIO_M          0x000000FF  // GPIO Interrupt Mask Enable

#define GPIO_IM_GPIO_S          0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_O_RIS register.

//

//*****************************************************************************

#define GPIO_RIS_GPIO_M         0x000000FF  // GPIO Interrupt Raw Status

#define GPIO_RIS_GPIO_S         0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_O_MIS register.

//

//*****************************************************************************

#define GPIO_MIS_GPIO_M         0x000000FF  // GPIO Masked Interrupt Status

#define GPIO_MIS_GPIO_S         0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_O_ICR register.

//

//*****************************************************************************

#define GPIO_ICR_GPIO_M         0x000000FF  // GPIO Interrupt Clear

#define GPIO_ICR_GPIO_S         0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_O_LOCK register.

//

//*****************************************************************************

#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock

#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked

                                            // and may be modified

#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked

                                            // and may not be modified

#define GPIO_LOCK_KEY           0x4C4F434B  // Unlocks the GPIO_CR register


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_PCTL register for

// port A.

//

//*****************************************************************************

#define GPIO_PCTL_PA7_M         0xF0000000  // PA7 Mask

#define GPIO_PCTL_PA7_I2C1SDA   0x30000000  // I2C1SDA on PA7

#define GPIO_PCTL_PA7_M1PWM3    0x50000000  // M1PWM3 on PA7

#define GPIO_PCTL_PA6_M         0x0F000000  // PA6 Mask

#define GPIO_PCTL_PA6_I2C1SCL   0x03000000  // I2C1SCL on PA6

#define GPIO_PCTL_PA6_M1PWM2    0x05000000  // M1PWM2 on PA6

#define GPIO_PCTL_PA5_M         0x00F00000  // PA5 Mask

#define GPIO_PCTL_PA5_SSI0TX    0x00200000  // SSI0TX on PA5

#define GPIO_PCTL_PA4_M         0x000F0000  // PA4 Mask

#define GPIO_PCTL_PA4_SSI0RX    0x00020000  // SSI0RX on PA4

#define GPIO_PCTL_PA3_M         0x0000F000  // PA3 Mask

#define GPIO_PCTL_PA3_SSI0FSS   0x00002000  // SSI0FSS on PA3

#define GPIO_PCTL_PA2_M         0x00000F00  // PA2 Mask

#define GPIO_PCTL_PA2_SSI0CLK   0x00000200  // SSI0CLK on PA2

#define GPIO_PCTL_PA1_M         0x000000F0  // PA1 Mask

#define GPIO_PCTL_PA1_U0TX      0x00000010  // U0TX on PA1

#define GPIO_PCTL_PA1_CAN1TX    0x00000080  // CAN1TX on PA1

#define GPIO_PCTL_PA0_M         0x0000000F  // PA0 Mask

#define GPIO_PCTL_PA0_U0RX      0x00000001  // U0RX on PA0

#define GPIO_PCTL_PA0_CAN1RX    0x00000008  // CAN1RX on PA0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_PCTL register for

// port B.

//

//*****************************************************************************

#define GPIO_PCTL_PB7_M         0xF0000000  // PB7 Mask

#define GPIO_PCTL_PB7_SSI2TX    0x20000000  // SSI2TX on PB7

#define GPIO_PCTL_PB7_I2C5SDA   0x30000000  // I2C5SDA on PB7

#define GPIO_PCTL_PB7_M0PWM1    0x40000000  // M0PWM1 on PB7

#define GPIO_PCTL_PB7_T0CCP1    0x70000000  // T0CCP1 on PB7

#define GPIO_PCTL_PB6_M         0x0F000000  // PB6 Mask

#define GPIO_PCTL_PB6_SSI2RX    0x02000000  // SSI2RX on PB6

#define GPIO_PCTL_PB6_I2C5SCL   0x03000000  // I2C5SCL on PB6

#define GPIO_PCTL_PB6_M0PWM0    0x04000000  // M0PWM0 on PB6

#define GPIO_PCTL_PB6_T0CCP0    0x07000000  // T0CCP0 on PB6

#define GPIO_PCTL_PB5_M         0x00F00000  // PB5 Mask

#define GPIO_PCTL_PB5_SSI2FSS   0x00200000  // SSI2FSS on PB5

#define GPIO_PCTL_PB5_M0PWM3    0x00400000  // M0PWM3 on PB5

#define GPIO_PCTL_PB5_T1CCP1    0x00700000  // T1CCP1 on PB5

#define GPIO_PCTL_PB5_CAN0TX    0x00800000  // CAN0TX on PB5

#define GPIO_PCTL_PB4_M         0x000F0000  // PB4 Mask

#define GPIO_PCTL_PB4_SSI2CLK   0x00020000  // SSI2CLK on PB4

#define GPIO_PCTL_PB4_M0PWM2    0x00040000  // M0PWM2 on PB4

#define GPIO_PCTL_PB4_T1CCP0    0x00070000  // T1CCP0 on PB4

#define GPIO_PCTL_PB4_CAN0RX    0x00080000  // CAN0RX on PB4

#define GPIO_PCTL_PB3_M         0x0000F000  // PB3 Mask

#define GPIO_PCTL_PB3_I2C0SDA   0x00003000  // I2C0SDA on PB3

#define GPIO_PCTL_PB3_T3CCP1    0x00007000  // T3CCP1 on PB3

#define GPIO_PCTL_PB2_M         0x00000F00  // PB2 Mask

#define GPIO_PCTL_PB2_I2C0SCL   0x00000300  // I2C0SCL on PB2

#define GPIO_PCTL_PB2_T3CCP0    0x00000700  // T3CCP0 on PB2

#define GPIO_PCTL_PB1_M         0x000000F0  // PB1 Mask

#define GPIO_PCTL_PB1_USB0VBUS  0x00000000  // USB0VBUS on PB1

#define GPIO_PCTL_PB1_U1TX      0x00000010  // U1TX on PB1

#define GPIO_PCTL_PB1_T2CCP1    0x00000070  // T2CCP1 on PB1

#define GPIO_PCTL_PB0_M         0x0000000F  // PB0 Mask

#define GPIO_PCTL_PB0_USB0ID    0x00000000  // USB0ID on PB0

#define GPIO_PCTL_PB0_U1RX      0x00000001  // U1RX on PB0

#define GPIO_PCTL_PB0_T2CCP0    0x00000007  // T2CCP0 on PB0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_PCTL register for

// port C.

//

//*****************************************************************************

#define GPIO_PCTL_PC7_M         0xF0000000  // PC7 Mask

#define GPIO_PCTL_PC7_U3TX      0x10000000  // U3TX on PC7

#define GPIO_PCTL_PC7_WT1CCP1   0x70000000  // WT1CCP1 on PC7

#define GPIO_PCTL_PC7_USB0PFLT  0x80000000  // USB0PFLT on PC7

#define GPIO_PCTL_PC6_M         0x0F000000  // PC6 Mask

#define GPIO_PCTL_PC6_U3RX      0x01000000  // U3RX on PC6

#define GPIO_PCTL_PC6_PHB1      0x06000000  // PHB1 on PC6

#define GPIO_PCTL_PC6_WT1CCP0   0x07000000  // WT1CCP0 on PC6

#define GPIO_PCTL_PC6_USB0EPEN  0x08000000  // USB0EPEN on PC6

#define GPIO_PCTL_PC5_M         0x00F00000  // PC5 Mask

#define GPIO_PCTL_PC5_U4TX      0x00100000  // U4TX on PC5

#define GPIO_PCTL_PC5_U1TX      0x00200000  // U1TX on PC5

#define GPIO_PCTL_PC5_M0PWM7    0x00400000  // M0PWM7 on PC5

#define GPIO_PCTL_PC5_PHA1      0x00600000  // PHA1 on PC5

#define GPIO_PCTL_PC5_WT0CCP1   0x00700000  // WT0CCP1 on PC5

#define GPIO_PCTL_PC5_U1CTS     0x00800000  // U1CTS on PC5

#define GPIO_PCTL_PC4_M         0x000F0000  // PC4 Mask

#define GPIO_PCTL_PC4_U4RX      0x00010000  // U4RX on PC4

#define GPIO_PCTL_PC4_U1RX      0x00020000  // U1RX on PC4

#define GPIO_PCTL_PC4_M0PWM6    0x00040000  // M0PWM6 on PC4

#define GPIO_PCTL_PC4_IDX1      0x00060000  // IDX1 on PC4

#define GPIO_PCTL_PC4_WT0CCP0   0x00070000  // WT0CCP0 on PC4

#define GPIO_PCTL_PC4_U1RTS     0x00080000  // U1RTS on PC4

#define GPIO_PCTL_PC3_M         0x0000F000  // PC3 Mask

#define GPIO_PCTL_PC3_TDO       0x00001000  // TDO on PC3

#define GPIO_PCTL_PC3_T5CCP1    0x00007000  // T5CCP1 on PC3

#define GPIO_PCTL_PC2_M         0x00000F00  // PC2 Mask

#define GPIO_PCTL_PC2_TDI       0x00000100  // TDI on PC2

#define GPIO_PCTL_PC2_T5CCP0    0x00000700  // T5CCP0 on PC2

#define GPIO_PCTL_PC1_M         0x000000F0  // PC1 Mask

#define GPIO_PCTL_PC1_TMS       0x00000010  // TMS on PC1

#define GPIO_PCTL_PC1_T4CCP1    0x00000070  // T4CCP1 on PC1

#define GPIO_PCTL_PC0_M         0x0000000F  // PC0 Mask

#define GPIO_PCTL_PC0_TCK       0x00000001  // TCK on PC0

#define GPIO_PCTL_PC0_T4CCP0    0x00000007  // T4CCP0 on PC0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_PCTL register for

// port D.

//

//*****************************************************************************

#define GPIO_PCTL_PD7_M         0xF0000000  // PD7 Mask

#define GPIO_PCTL_PD7_U2TX      0x10000000  // U2TX on PD7

#define GPIO_PCTL_PD7_M0FAULT1  0x40000000  // M0FAULT1 on PD7

#define GPIO_PCTL_PD7_PHB0      0x60000000  // PHB0 on PD7

#define GPIO_PCTL_PD7_WT5CCP1   0x70000000  // WT5CCP1 on PD7

#define GPIO_PCTL_PD7_NMI       0x80000000  // NMI on PD7

#define GPIO_PCTL_PD6_M         0x0F000000  // PD6 Mask

#define GPIO_PCTL_PD6_U2RX      0x01000000  // U2RX on PD6

#define GPIO_PCTL_PD6_M0FAULT0  0x04000000  // M0FAULT0 on PD6

#define GPIO_PCTL_PD6_PHA0      0x06000000  // PHA0 on PD6

#define GPIO_PCTL_PD6_WT5CCP0   0x07000000  // WT5CCP0 on PD6

#define GPIO_PCTL_PD5_M         0x00F00000  // PD5 Mask

#define GPIO_PCTL_PD5_USB0DP    0x00000000  // USB0DP on PD5

#define GPIO_PCTL_PD5_U6TX      0x00100000  // U6TX on PD5

#define GPIO_PCTL_PD5_WT4CCP1   0x00700000  // WT4CCP1 on PD5

#define GPIO_PCTL_PD4_M         0x000F0000  // PD4 Mask

#define GPIO_PCTL_PD4_USB0DM    0x00000000  // USB0DM on PD4

#define GPIO_PCTL_PD4_U6RX      0x00010000  // U6RX on PD4

#define GPIO_PCTL_PD4_WT4CCP0   0x00070000  // WT4CCP0 on PD4

#define GPIO_PCTL_PD3_M         0x0000F000  // PD3 Mask

#define GPIO_PCTL_PD3_AIN4      0x00000000  // AIN4 on PD3

#define GPIO_PCTL_PD3_SSI3TX    0x00001000  // SSI3TX on PD3

#define GPIO_PCTL_PD3_SSI1TX    0x00002000  // SSI1TX on PD3

#define GPIO_PCTL_PD3_IDX0      0x00006000  // IDX0 on PD3

#define GPIO_PCTL_PD3_WT3CCP1   0x00007000  // WT3CCP1 on PD3

#define GPIO_PCTL_PD3_USB0PFLT  0x00008000  // USB0PFLT on PD3

#define GPIO_PCTL_PD2_M         0x00000F00  // PD2 Mask

#define GPIO_PCTL_PD2_AIN5      0x00000000  // AIN5 on PD2

#define GPIO_PCTL_PD2_SSI3RX    0x00000100  // SSI3RX on PD2

#define GPIO_PCTL_PD2_SSI1RX    0x00000200  // SSI1RX on PD2

#define GPIO_PCTL_PD2_M0FAULT0  0x00000400  // M0FAULT0 on PD2

#define GPIO_PCTL_PD2_WT3CCP0   0x00000700  // WT3CCP0 on PD2

#define GPIO_PCTL_PD2_USB0EPEN  0x00000800  // USB0EPEN on PD2

#define GPIO_PCTL_PD1_M         0x000000F0  // PD1 Mask

#define GPIO_PCTL_PD1_AIN6      0x00000000  // AIN6 on PD1

#define GPIO_PCTL_PD1_SSI3FSS   0x00000010  // SSI3FSS on PD1

#define GPIO_PCTL_PD1_SSI1FSS   0x00000020  // SSI1FSS on PD1

#define GPIO_PCTL_PD1_I2C3SDA   0x00000030  // I2C3SDA on PD1

#define GPIO_PCTL_PD1_M0PWM7    0x00000040  // M0PWM7 on PD1

#define GPIO_PCTL_PD1_M1PWM1    0x00000050  // M1PWM1 on PD1

#define GPIO_PCTL_PD1_WT2CCP1   0x00000070  // WT2CCP1 on PD1

#define GPIO_PCTL_PD0_M         0x0000000F  // PD0 Mask

#define GPIO_PCTL_PD0_AIN7      0x00000000  // AIN7 on PD0

#define GPIO_PCTL_PD0_SSI3CLK   0x00000001  // SSI3CLK on PD0

#define GPIO_PCTL_PD0_SSI1CLK   0x00000002  // SSI1CLK on PD0

#define GPIO_PCTL_PD0_I2C3SCL   0x00000003  // I2C3SCL on PD0

#define GPIO_PCTL_PD0_M0PWM6    0x00000004  // M0PWM6 on PD0

#define GPIO_PCTL_PD0_M1PWM0    0x00000005  // M1PWM0 on PD0

#define GPIO_PCTL_PD0_WT2CCP0   0x00000007  // WT2CCP0 on PD0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_PCTL register for

// port E.

//

//*****************************************************************************

#define GPIO_PCTL_PE5_M         0x00F00000  // PE5 Mask

#define GPIO_PCTL_PE5_AIN8      0x00000000  // AIN8 on PE5

#define GPIO_PCTL_PE5_U5TX      0x00100000  // U5TX on PE5

#define GPIO_PCTL_PE5_I2C2SDA   0x00300000  // I2C2SDA on PE5

#define GPIO_PCTL_PE5_M0PWM5    0x00400000  // M0PWM5 on PE5

#define GPIO_PCTL_PE5_M1PWM3    0x00500000  // M1PWM3 on PE5

#define GPIO_PCTL_PE5_CAN0TX    0x00800000  // CAN0TX on PE5

#define GPIO_PCTL_PE4_M         0x000F0000  // PE4 Mask

#define GPIO_PCTL_PE4_AIN9      0x00000000  // AIN9 on PE4

#define GPIO_PCTL_PE4_U5RX      0x00010000  // U5RX on PE4

#define GPIO_PCTL_PE4_I2C2SCL   0x00030000  // I2C2SCL on PE4

#define GPIO_PCTL_PE4_M0PWM4    0x00040000  // M0PWM4 on PE4

#define GPIO_PCTL_PE4_M1PWM2    0x00050000  // M1PWM2 on PE4

#define GPIO_PCTL_PE4_CAN0RX    0x00080000  // CAN0RX on PE4

#define GPIO_PCTL_PE3_M         0x0000F000  // PE3 Mask

#define GPIO_PCTL_PE3_AIN0      0x00000000  // AIN0 on PE3

#define GPIO_PCTL_PE2_M         0x00000F00  // PE2 Mask

#define GPIO_PCTL_PE2_AIN1      0x00000000  // AIN1 on PE2

#define GPIO_PCTL_PE1_M         0x000000F0  // PE1 Mask

#define GPIO_PCTL_PE1_AIN2      0x00000000  // AIN2 on PE1

#define GPIO_PCTL_PE1_U7TX      0x00000010  // U7TX on PE1

#define GPIO_PCTL_PE0_M         0x0000000F  // PE0 Mask

#define GPIO_PCTL_PE0_AIN3      0x00000000  // AIN3 on PE0

#define GPIO_PCTL_PE0_U7RX      0x00000001  // U7RX on PE0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_PCTL register for

// port F.

//

//*****************************************************************************

#define GPIO_PCTL_PF4_M         0x000F0000  // PF4 Mask

#define GPIO_PCTL_PF4_M0FAULT2  0x00040000  // M0FAULT2 on PF4

#define GPIO_PCTL_PF4_M1FAULT0  0x00050000  // M1FAULT0 on PF4

#define GPIO_PCTL_PF4_IDX0      0x00060000  // IDX0 on PF4

#define GPIO_PCTL_PF4_T2CCP0    0x00070000  // T2CCP0 on PF4

#define GPIO_PCTL_PF4_USB0EPEN  0x00080000  // USB0EPEN on PF4

#define GPIO_PCTL_PF3_M         0x0000F000  // PF3 Mask

#define GPIO_PCTL_PF3_SSI1FSS   0x00002000  // SSI1FSS on PF3

#define GPIO_PCTL_PF3_CAN0TX    0x00003000  // CAN0TX on PF3

#define GPIO_PCTL_PF3_M0FAULT1  0x00004000  // M0FAULT1 on PF3

#define GPIO_PCTL_PF3_M1PWM7    0x00005000  // M1PWM7 on PF3

#define GPIO_PCTL_PF3_T1CCP1    0x00007000  // T1CCP1 on PF3

#define GPIO_PCTL_PF3_TRCLK     0x0000E000  // TRCLK on PF3

#define GPIO_PCTL_PF2_M         0x00000F00  // PF2 Mask

#define GPIO_PCTL_PF2_SSI1CLK   0x00000200  // SSI1CLK on PF2

#define GPIO_PCTL_PF2_M0FAULT0  0x00000400  // M0FAULT0 on PF2

#define GPIO_PCTL_PF2_M1PWM6    0x00000500  // M1PWM6 on PF2

#define GPIO_PCTL_PF2_T1CCP0    0x00000700  // T1CCP0 on PF2

#define GPIO_PCTL_PF2_TRD0      0x00000E00  // TRD0 on PF2

#define GPIO_PCTL_PF1_M         0x000000F0  // PF1 Mask

#define GPIO_PCTL_PF1_U1CTS     0x00000010  // U1CTS on PF1

#define GPIO_PCTL_PF1_SSI1TX    0x00000020  // SSI1TX on PF1

#define GPIO_PCTL_PF1_M1PWM5    0x00000050  // M1PWM5 on PF1

#define GPIO_PCTL_PF1_PHB0      0x00000060  // PHB0 on PF1

#define GPIO_PCTL_PF1_T0CCP1    0x00000070  // T0CCP1 on PF1

#define GPIO_PCTL_PF1_C1O       0x00000090  // C1O on PF1

#define GPIO_PCTL_PF1_TRD1      0x000000E0  // TRD1 on PF1

#define GPIO_PCTL_PF0_M         0x0000000F  // PF0 Mask

#define GPIO_PCTL_PF0_U1RTS     0x00000001  // U1RTS on PF0

#define GPIO_PCTL_PF0_SSI1RX    0x00000002  // SSI1RX on PF0

#define GPIO_PCTL_PF0_CAN0RX    0x00000003  // CAN0RX on PF0

#define GPIO_PCTL_PF0_M1PWM4    0x00000005  // M1PWM4 on PF0

#define GPIO_PCTL_PF0_PHA0      0x00000006  // PHA0 on PF0

#define GPIO_PCTL_PF0_T0CCP0    0x00000007  // T0CCP0 on PF0

#define GPIO_PCTL_PF0_NMI       0x00000008  // NMI on PF0

#define GPIO_PCTL_PF0_C0O       0x00000009  // C0O on PF0


//*****************************************************************************

//

// The following are defines for the bit fields in the GPIO_PCTL register for

// port G.

//

//*****************************************************************************

#define GPIO_PCTL_PG5_M         0x00F00000  // PG5 Mask

#define GPIO_PCTL_PG5_U2TX      0x00100000  // U2TX on PG5

#define GPIO_PCTL_PG5_I2C1SDA   0x00300000  // I2C1SDA on PG5

#define GPIO_PCTL_PG5_M0PWM5    0x00400000  // M0PWM5 on PG5

#define GPIO_PCTL_PG5_M1PWM3    0x00500000  // M1PWM3 on PG5

#define GPIO_PCTL_PG5_IDX1      0x00600000  // IDX1 on PG5

#define GPIO_PCTL_PG5_WT0CCP1   0x00700000  // WT0CCP1 on PG5

#define GPIO_PCTL_PG5_USB0PFLT  0x00800000  // USB0PFLT on PG5

#define GPIO_PCTL_PG4_M         0x000F0000  // PG4 Mask

#define GPIO_PCTL_PG4_U2RX      0x00010000  // U2RX on PG4

#define GPIO_PCTL_PG4_I2C1SCL   0x00030000  // I2C1SCL on PG4

#define GPIO_PCTL_PG4_M0PWM4    0x00040000  // M0PWM4 on PG4

#define GPIO_PCTL_PG4_M1PWM2    0x00050000  // M1PWM2 on PG4

#define GPIO_PCTL_PG4_PHB1      0x00060000  // PHB1 on PG4

#define GPIO_PCTL_PG4_WT0CCP0   0x00070000  // WT0CCP0 on PG4

#define GPIO_PCTL_PG4_USB0EPEN  0x00080000  // USB0EPEN on PG4

#define GPIO_PCTL_PG3_M         0x0000F000  // PG3 Mask

#define GPIO_PCTL_PG3_I2C4SDA   0x00003000  // I2C4SDA on PG3

#define GPIO_PCTL_PG3_M0FAULT2  0x00004000  // M0FAULT2 on PG3

#define GPIO_PCTL_PG3_M1PWM1    0x00005000  // M1PWM1 on PG3

#define GPIO_PCTL_PG3_PHA1      0x00006000  // PHA1 on PG3

#define GPIO_PCTL_PG3_T5CCP1    0x00007000  // T5CCP1 on PG3

#define GPIO_PCTL_PG2_M         0x00000F00  // PG2 Mask

#define GPIO_PCTL_PG2_I2C4SCL   0x00000300  // I2C4SCL on PG2

#define GPIO_PCTL_PG2_M0FAULT1  0x00000400  // M0FAULT1 on PG2

#define GPIO_PCTL_PG2_M1PWM0    0x00000500  // M1PWM0 on PG2

#define GPIO_PCTL_PG2_T5CCP0    0x00000700  // T5CCP0 on PG2

#define GPIO_PCTL_PG1_M         0x000000F0  // PG1 Mask

#define GPIO_PCTL_PG1_I2C3SDA   0x00000030  // I2C3SDA on PG1

#define GPIO_PCTL_PG1_M1FAULT2  0x00000050  // M1FAULT2 on PG1

#define GPIO_PCTL_PG1_PHB1      0x00000060  // PHB1 on PG1

#define GPIO_PCTL_PG1_T4CCP1    0x00000070  // T4CCP1 on PG1

#define GPIO_PCTL_PG0_M         0x0000000F  // PG0 Mask

#define GPIO_PCTL_PG0_I2C3SCL   0x00000003  // I2C3SCL on PG0

#define GPIO_PCTL_PG0_M1FAULT1  0x00000005  // M1FAULT1 on PG0

#define GPIO_PCTL_PG0_PHA1      0x00000006  // PHA1 on PG0

#define GPIO_PCTL_PG0_T4CCP0    0x00000007  // T4CCP0 on PG0


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_CR0 register.

//

//*****************************************************************************

#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate

#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase

#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity

#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select

#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format

#define SSI_CR0_FRF_TI          0x00000010  // Synchronous Serial Frame Format

#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format

#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select

#define SSI_CR0_DSS_4           0x00000003  // 4-bit data

#define SSI_CR0_DSS_5           0x00000004  // 5-bit data

#define SSI_CR0_DSS_6           0x00000005  // 6-bit data

#define SSI_CR0_DSS_7           0x00000006  // 7-bit data

#define SSI_CR0_DSS_8           0x00000007  // 8-bit data

#define SSI_CR0_DSS_9           0x00000008  // 9-bit data

#define SSI_CR0_DSS_10          0x00000009  // 10-bit data

#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data

#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data

#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data

#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data

#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data

#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data

#define SSI_CR0_SCR_S           8


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_CR1 register.

//

//*****************************************************************************

#define SSI_CR1_EOT             0x00000010  // End of Transmission

#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select

#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port

                                            // Enable

#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_DR register.

//

//*****************************************************************************

#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data

#define SSI_DR_DATA_S           0


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_SR register.

//

//*****************************************************************************

#define SSI_SR_BSY              0x00000010  // SSI Busy Bit

#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full

#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty

#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full

#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_CPSR register.

//

//*****************************************************************************

#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor

#define SSI_CPSR_CPSDVSR_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_IM register.

//

//*****************************************************************************

#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask

#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask

#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt

                                            // Mask

#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt

                                            // Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_RIS register.

//

//*****************************************************************************

#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt

                                            // Status

#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt

                                            // Status

#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw

                                            // Interrupt Status

#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw

                                            // Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_MIS register.

//

//*****************************************************************************

#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked

                                            // Interrupt Status

#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked

                                            // Interrupt Status

#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked

                                            // Interrupt Status

#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked

                                            // Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_ICR register.

//

//*****************************************************************************

#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt

                                            // Clear

#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt

                                            // Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_DMACTL register.

//

//*****************************************************************************

#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable

#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the SSI_O_CC register.

//

//*****************************************************************************

#define SSI_CC_CS_M             0x0000000F  // SSI Baud Clock Source

#define SSI_CC_CS_SYSPLL        0x00000000  // System clock (based on clock

                                            // source and divisor factor)

#define SSI_CC_CS_PIOSC         0x00000005  // PIOSC


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_DR register.

//

//*****************************************************************************

#define UART_DR_OE              0x00000800  // UART Overrun Error

#define UART_DR_BE              0x00000400  // UART Break Error

#define UART_DR_PE              0x00000200  // UART Parity Error

#define UART_DR_FE              0x00000100  // UART Framing Error

#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received

#define UART_DR_DATA_S          0


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_RSR register.

//

//*****************************************************************************

#define UART_RSR_OE             0x00000008  // UART Overrun Error

#define UART_RSR_BE             0x00000004  // UART Break Error

#define UART_RSR_PE             0x00000002  // UART Parity Error

#define UART_RSR_FE             0x00000001  // UART Framing Error


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_ECR register.

//

//*****************************************************************************

#define UART_ECR_DATA_M         0x000000FF  // Error Clear

#define UART_ECR_DATA_S         0


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_FR register.

//

//*****************************************************************************

#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty

#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full

#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full

#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty

#define UART_FR_BUSY            0x00000008  // UART Busy

#define UART_FR_CTS             0x00000001  // Clear To Send


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_ILPR register.

//

//*****************************************************************************

#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor

#define UART_ILPR_ILPDVSR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_IBRD register.

//

//*****************************************************************************

#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor

#define UART_IBRD_DIVINT_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_FBRD register.

//

//*****************************************************************************

#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor

#define UART_FBRD_DIVFRAC_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_LCRH register.

//

//*****************************************************************************

#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select

#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length

#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)

#define UART_LCRH_WLEN_6        0x00000020  // 6 bits

#define UART_LCRH_WLEN_7        0x00000040  // 7 bits

#define UART_LCRH_WLEN_8        0x00000060  // 8 bits

#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs

#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select

#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select

#define UART_LCRH_PEN           0x00000002  // UART Parity Enable

#define UART_LCRH_BRK           0x00000001  // UART Send Break


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_CTL register.

//

//*****************************************************************************

#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send

#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send

#define UART_CTL_RTS            0x00000800  // Request to Send

#define UART_CTL_RXE            0x00000200  // UART Receive Enable

#define UART_CTL_TXE            0x00000100  // UART Transmit Enable

#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable

#define UART_CTL_HSE            0x00000020  // High-Speed Enable

#define UART_CTL_EOT            0x00000010  // End of Transmission

#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support

#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode

#define UART_CTL_SIREN          0x00000002  // UART SIR Enable

#define UART_CTL_UARTEN         0x00000001  // UART Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_IFLS register.

//

//*****************************************************************************

#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO

                                            // Level Select

#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full

#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full

#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)

#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full

#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full

#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO

                                            // Level Select

#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full

#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full

#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)

#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full

#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_IM register.

//

//*****************************************************************************

#define UART_IM_9BITIM          0x00001000  // 9-Bit Mode Interrupt Mask

#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt

                                            // Mask

#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask

#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask

#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt

                                            // Mask

#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt

                                            // Mask

#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask

#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask

#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem

                                            // Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_RIS register.

//

//*****************************************************************************

#define UART_RIS_9BITRIS        0x00001000  // 9-Bit Mode Raw Interrupt Status

#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt

                                            // Status

#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt

                                            // Status

#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt

                                            // Status

#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt

                                            // Status

#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw

                                            // Interrupt Status

#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt

                                            // Status

#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt

                                            // Status

#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw

                                            // Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_MIS register.

//

//*****************************************************************************

#define UART_MIS_9BITMIS        0x00001000  // 9-Bit Mode Masked Interrupt

                                            // Status

#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked

                                            // Interrupt Status

#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked

                                            // Interrupt Status

#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked

                                            // Interrupt Status

#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked

                                            // Interrupt Status

#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked

                                            // Interrupt Status

#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt

                                            // Status

#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt

                                            // Status

#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked

                                            // Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_ICR register.

//

//*****************************************************************************

#define UART_ICR_9BITIC         0x00001000  // 9-Bit Mode Interrupt Clear

#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear

#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear

#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear

#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear

#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear

#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear

#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear

#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem

                                            // Interrupt Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_DMACTL register.

//

//*****************************************************************************

#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error

#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable

#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_9BITADDR

// register.

//

//*****************************************************************************

#define UART_9BITADDR_9BITEN    0x00008000  // Enable 9-Bit Mode

#define UART_9BITADDR_ADDR_M    0x000000FF  // Self Address for 9-Bit Mode

#define UART_9BITADDR_ADDR_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_9BITAMASK

// register.

//

//*****************************************************************************

#define UART_9BITAMASK_MASK_M   0x000000FF  // Self Address Mask for 9-Bit Mode

#define UART_9BITAMASK_MASK_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_PP register.

//

//*****************************************************************************

#define UART_PP_NB              0x00000002  // 9-Bit Support

#define UART_PP_SC              0x00000001  // Smart Card Support


//*****************************************************************************

//

// The following are defines for the bit fields in the UART_O_CC register.

//

//*****************************************************************************

#define UART_CC_CS_M            0x0000000F  // UART Baud Clock Source

#define UART_CC_CS_SYSCLK       0x00000000  // System clock (based on clock

                                            // source and divisor factor)

#define UART_CC_CS_PIOSC        0x00000005  // PIOSC


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MSA register.

//

//*****************************************************************************

#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address

#define I2C_MSA_RS              0x00000001  // Receive not send

#define I2C_MSA_SA_S            1


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MCS register.

//

//*****************************************************************************

#define I2C_MCS_CLKTO           0x00000080  // Clock Timeout Error

#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy

#define I2C_MCS_IDLE            0x00000020  // I2C Idle

#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost

#define I2C_MCS_HS              0x00000010  // High-Speed Enable

#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable

#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data

#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address

#define I2C_MCS_STOP            0x00000004  // Generate STOP

#define I2C_MCS_ERROR           0x00000002  // Error

#define I2C_MCS_START           0x00000002  // Generate START

#define I2C_MCS_RUN             0x00000001  // I2C Master Enable

#define I2C_MCS_BUSY            0x00000001  // I2C Busy


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MDR register.

//

//*****************************************************************************

#define I2C_MDR_DATA_M          0x000000FF  // This byte contains the data

                                            // transferred during a transaction

#define I2C_MDR_DATA_S          0


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MTPR register.

//

//*****************************************************************************

#define I2C_MTPR_HS             0x00000080  // High-Speed Enable

#define I2C_MTPR_TPR_M          0x0000007F  // Timer Period

#define I2C_MTPR_TPR_S          0


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MIMR register.

//

//*****************************************************************************

#define I2C_MIMR_CLKIM          0x00000002  // Clock Timeout Interrupt Mask

#define I2C_MIMR_IM             0x00000001  // Master Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MRIS register.

//

//*****************************************************************************

#define I2C_MRIS_CLKRIS         0x00000002  // Clock Timeout Raw Interrupt

                                            // Status

#define I2C_MRIS_RIS            0x00000001  // Master Raw Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MMIS register.

//

//*****************************************************************************

#define I2C_MMIS_CLKMIS         0x00000002  // Clock Timeout Masked Interrupt

                                            // Status

#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MICR register.

//

//*****************************************************************************

#define I2C_MICR_CLKIC          0x00000002  // Clock Timeout Interrupt Clear

#define I2C_MICR_IC             0x00000001  // Master Interrupt Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MCR register.

//

//*****************************************************************************

#define I2C_MCR_GFE             0x00000040  // I2C Glitch Filter Enable

#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable

#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable

#define I2C_MCR_LPBK            0x00000001  // I2C Loopback


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.

//

//*****************************************************************************

#define I2C_MCLKOCNT_CNTL_M     0x000000FF  // I2C Master Count

#define I2C_MCLKOCNT_CNTL_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MBMON register.

//

//*****************************************************************************

#define I2C_MBMON_SDA           0x00000002  // I2C SDA Status

#define I2C_MBMON_SCL           0x00000001  // I2C SCL Status


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_MCR2 register.

//

//*****************************************************************************

#define I2C_MCR2_GFPW_M         0x00000070  // I2C Glitch Filter Pulse Width

#define I2C_MCR2_GFPW_BYPASS    0x00000000  // Bypass

#define I2C_MCR2_GFPW_1         0x00000010  // 1 clock

#define I2C_MCR2_GFPW_2         0x00000020  // 2 clocks

#define I2C_MCR2_GFPW_3         0x00000030  // 3 clocks

#define I2C_MCR2_GFPW_4         0x00000040  // 4 clocks

#define I2C_MCR2_GFPW_8         0x00000050  // 8 clocks

#define I2C_MCR2_GFPW_16        0x00000060  // 16 clocks

#define I2C_MCR2_GFPW_31        0x00000070  // 31 clocks


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SOAR register.

//

//*****************************************************************************

#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address

#define I2C_SOAR_OAR_S          0


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SCSR register.

//

//*****************************************************************************

#define I2C_SCSR_OAR2SEL        0x00000008  // OAR2 Address Matched

#define I2C_SCSR_FBR            0x00000004  // First Byte Received

#define I2C_SCSR_TREQ           0x00000002  // Transmit Request

#define I2C_SCSR_DA             0x00000001  // Device Active

#define I2C_SCSR_RREQ           0x00000001  // Receive Request


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SDR register.

//

//*****************************************************************************

#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer

#define I2C_SDR_DATA_S          0


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SIMR register.

//

//*****************************************************************************

#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask

#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask

#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SRIS register.

//

//*****************************************************************************

#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt

                                            // Status

#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt

                                            // Status

#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SMIS register.

//

//*****************************************************************************

#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt

                                            // Status

#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt

                                            // Status

#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SICR register.

//

//*****************************************************************************

#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear

#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear

#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SOAR2 register.

//

//*****************************************************************************

#define I2C_SOAR2_OAR2EN        0x00000080  // I2C Slave Own Address 2 Enable

#define I2C_SOAR2_OAR2_M        0x0000007F  // I2C Slave Own Address 2

#define I2C_SOAR2_OAR2_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_SACKCTL register.

//

//*****************************************************************************

#define I2C_SACKCTL_ACKOVAL     0x00000002  // I2C Slave ACK Override Value

#define I2C_SACKCTL_ACKOEN      0x00000001  // I2C Slave ACK Override Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_PP register.

//

//*****************************************************************************

#define I2C_PP_HS               0x00000001  // High-Speed Capable


//*****************************************************************************

//

// The following are defines for the bit fields in the I2C_O_PC register.

//

//*****************************************************************************

#define I2C_PC_HS               0x00000001  // High-Speed Capable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_CTL register.

//

//*****************************************************************************

#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3

#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2

#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1

#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_SYNC register.

//

//*****************************************************************************

#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter

#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter

#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter

#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_ENABLE register.

//

//*****************************************************************************

#define PWM_ENABLE_PWM7EN       0x00000080  // MnPWM7 Output Enable

#define PWM_ENABLE_PWM6EN       0x00000040  // MnPWM6 Output Enable

#define PWM_ENABLE_PWM5EN       0x00000020  // MnPWM5 Output Enable

#define PWM_ENABLE_PWM4EN       0x00000010  // MnPWM4 Output Enable

#define PWM_ENABLE_PWM3EN       0x00000008  // MnPWM3 Output Enable

#define PWM_ENABLE_PWM2EN       0x00000004  // MnPWM2 Output Enable

#define PWM_ENABLE_PWM1EN       0x00000002  // MnPWM1 Output Enable

#define PWM_ENABLE_PWM0EN       0x00000001  // MnPWM0 Output Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_INVERT register.

//

//*****************************************************************************

#define PWM_INVERT_PWM7INV      0x00000080  // Invert MnPWM7 Signal

#define PWM_INVERT_PWM6INV      0x00000040  // Invert MnPWM6 Signal

#define PWM_INVERT_PWM5INV      0x00000020  // Invert MnPWM5 Signal

#define PWM_INVERT_PWM4INV      0x00000010  // Invert MnPWM4 Signal

#define PWM_INVERT_PWM3INV      0x00000008  // Invert MnPWM3 Signal

#define PWM_INVERT_PWM2INV      0x00000004  // Invert MnPWM2 Signal

#define PWM_INVERT_PWM1INV      0x00000002  // Invert MnPWM1 Signal

#define PWM_INVERT_PWM0INV      0x00000001  // Invert MnPWM0 Signal


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_FAULT register.

//

//*****************************************************************************

#define PWM_FAULT_FAULT7        0x00000080  // MnPWM7 Fault

#define PWM_FAULT_FAULT6        0x00000040  // MnPWM6 Fault

#define PWM_FAULT_FAULT5        0x00000020  // MnPWM5 Fault

#define PWM_FAULT_FAULT4        0x00000010  // MnPWM4 Fault

#define PWM_FAULT_FAULT3        0x00000008  // MnPWM3 Fault

#define PWM_FAULT_FAULT2        0x00000004  // MnPWM2 Fault

#define PWM_FAULT_FAULT1        0x00000002  // MnPWM1 Fault

#define PWM_FAULT_FAULT0        0x00000001  // MnPWM0 Fault


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_INTEN register.

//

//*****************************************************************************

#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3

#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2

#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1

#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0

#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable

#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable

#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable

#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_RIS register.

//

//*****************************************************************************

#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3

#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2

#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1

#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0

#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted

#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted

#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted

#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_ISC register.

//

//*****************************************************************************

#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted

#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted

#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted

#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted

#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status

#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status

#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status

#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_STATUS register.

//

//*****************************************************************************

#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status

#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status

#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status

#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_FAULTVAL register.

//

//*****************************************************************************

#define PWM_FAULTVAL_PWM7       0x00000080  // MnPWM7 Fault Value

#define PWM_FAULTVAL_PWM6       0x00000040  // MnPWM6 Fault Value

#define PWM_FAULTVAL_PWM5       0x00000020  // MnPWM5 Fault Value

#define PWM_FAULTVAL_PWM4       0x00000010  // MnPWM4 Fault Value

#define PWM_FAULTVAL_PWM3       0x00000008  // MnPWM3 Fault Value

#define PWM_FAULTVAL_PWM2       0x00000004  // MnPWM2 Fault Value

#define PWM_FAULTVAL_PWM1       0x00000002  // MnPWM1 Fault Value

#define PWM_FAULTVAL_PWM0       0x00000001  // MnPWM0 Fault Value


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_ENUPD register.

//

//*****************************************************************************

#define PWM_ENUPD_ENUPD7_M      0x0000C000  // MnPWM7 Enable Update Mode

#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized

#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized

#define PWM_ENUPD_ENUPD6_M      0x00003000  // MnPWM6 Enable Update Mode

#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized

#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized

#define PWM_ENUPD_ENUPD5_M      0x00000C00  // MnPWM5 Enable Update Mode

#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized

#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized

#define PWM_ENUPD_ENUPD4_M      0x00000300  // MnPWM4 Enable Update Mode

#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized

#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized

#define PWM_ENUPD_ENUPD3_M      0x000000C0  // MnPWM3 Enable Update Mode

#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized

#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized

#define PWM_ENUPD_ENUPD2_M      0x00000030  // MnPWM2 Enable Update Mode

#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized

#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized

#define PWM_ENUPD_ENUPD1_M      0x0000000C  // MnPWM1 Enable Update Mode

#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized

#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized

#define PWM_ENUPD_ENUPD0_M      0x00000003  // MnPWM0 Enable Update Mode

#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate

#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized

#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_CTL register.

//

//*****************************************************************************

#define PWM_0_CTL_LATCH         0x00040000  // Latch Fault Input

#define PWM_0_CTL_MINFLTPER     0x00020000  // Minimum Fault Period

#define PWM_0_CTL_FLTSRC        0x00010000  // Fault Condition Source

#define PWM_0_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode

#define PWM_0_CTL_DBFALLUPD_I   0x00000000  // Immediate

#define PWM_0_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized

#define PWM_0_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized

#define PWM_0_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode

#define PWM_0_CTL_DBRISEUPD_I   0x00000000  // Immediate

#define PWM_0_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized

#define PWM_0_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized

#define PWM_0_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode

#define PWM_0_CTL_DBCTLUPD_I    0x00000000  // Immediate

#define PWM_0_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized

#define PWM_0_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized

#define PWM_0_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode

#define PWM_0_CTL_GENBUPD_I     0x00000000  // Immediate

#define PWM_0_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized

#define PWM_0_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized

#define PWM_0_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode

#define PWM_0_CTL_GENAUPD_I     0x00000000  // Immediate

#define PWM_0_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized

#define PWM_0_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized

#define PWM_0_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode

#define PWM_0_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode

#define PWM_0_CTL_LOADUPD       0x00000008  // Load Register Update Mode

#define PWM_0_CTL_DEBUG         0x00000004  // Debug Mode

#define PWM_0_CTL_MODE          0x00000002  // Counter Mode

#define PWM_0_CTL_ENABLE        0x00000001  // PWM Block Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_INTEN register.

//

//*****************************************************************************

#define PWM_0_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB

                                            // Down

#define PWM_0_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up

#define PWM_0_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA

                                            // Down

#define PWM_0_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up

#define PWM_0_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD

#define PWM_0_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0

#define PWM_0_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB

                                            // Down

#define PWM_0_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB

                                            // Up

#define PWM_0_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA

                                            // Down

#define PWM_0_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA

                                            // Up

#define PWM_0_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD

#define PWM_0_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_RIS register.

//

//*****************************************************************************

#define PWM_0_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt

                                            // Status

#define PWM_0_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status

#define PWM_0_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt

                                            // Status

#define PWM_0_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status

#define PWM_0_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status

#define PWM_0_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_ISC register.

//

//*****************************************************************************

#define PWM_0_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt

#define PWM_0_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt

#define PWM_0_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt

#define PWM_0_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt

#define PWM_0_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt

#define PWM_0_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_LOAD register.

//

//*****************************************************************************

#define PWM_0_LOAD_M            0x0000FFFF  // Counter Load Value

#define PWM_0_LOAD_S            0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_COUNT register.

//

//*****************************************************************************

#define PWM_0_COUNT_M           0x0000FFFF  // Counter Value

#define PWM_0_COUNT_S           0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_CMPA register.

//

//*****************************************************************************

#define PWM_0_CMPA_M            0x0000FFFF  // Comparator A Value

#define PWM_0_CMPA_S            0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_CMPB register.

//

//*****************************************************************************

#define PWM_0_CMPB_M            0x0000FFFF  // Comparator B Value

#define PWM_0_CMPB_S            0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_GENA register.

//

//*****************************************************************************

#define PWM_0_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_0_GENA_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA

#define PWM_0_GENA_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmA Low

#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High

#define PWM_0_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_0_GENA_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA

#define PWM_0_GENA_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmA Low

#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High

#define PWM_0_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_0_GENA_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA

#define PWM_0_GENA_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmA Low

#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High

#define PWM_0_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_0_GENA_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA

#define PWM_0_GENA_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmA Low

#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High

#define PWM_0_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_0_GENA_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_0_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA

#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low

#define PWM_0_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High

#define PWM_0_GENA_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_0_GENA_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_0_GENA_ACTZERO_INV  0x00000001  // Invert pwmA

#define PWM_0_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low

#define PWM_0_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_GENB register.

//

//*****************************************************************************

#define PWM_0_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_0_GENB_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB

#define PWM_0_GENB_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmB Low

#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High

#define PWM_0_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_0_GENB_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB

#define PWM_0_GENB_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmB Low

#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High

#define PWM_0_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_0_GENB_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB

#define PWM_0_GENB_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmB Low

#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High

#define PWM_0_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_0_GENB_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_0_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB

#define PWM_0_GENB_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmB Low

#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High

#define PWM_0_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_0_GENB_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_0_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB

#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low

#define PWM_0_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High

#define PWM_0_GENB_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_0_GENB_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_0_GENB_ACTZERO_INV  0x00000001  // Invert pwmB

#define PWM_0_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low

#define PWM_0_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_DBCTL register.

//

//*****************************************************************************

#define PWM_0_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_DBRISE register.

//

//*****************************************************************************

#define PWM_0_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay

#define PWM_0_DBRISE_DELAY_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_DBFALL register.

//

//*****************************************************************************

#define PWM_0_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay

#define PWM_0_DBFALL_DELAY_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_FLTSRC0

// register.

//

//*****************************************************************************

#define PWM_0_FLTSRC0_FAULT3    0x00000008  // Fault3 Input

#define PWM_0_FLTSRC0_FAULT2    0x00000004  // Fault2 Input

#define PWM_0_FLTSRC0_FAULT1    0x00000002  // Fault1 Input

#define PWM_0_FLTSRC0_FAULT0    0x00000001  // Fault0 Input


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_FLTSRC1

// register.

//

//*****************************************************************************

#define PWM_0_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7

#define PWM_0_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6

#define PWM_0_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5

#define PWM_0_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4

#define PWM_0_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3

#define PWM_0_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2

#define PWM_0_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1

#define PWM_0_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_MINFLTPER

// register.

//

//*****************************************************************************

#define PWM_0_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period

#define PWM_0_MINFLTPER_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_CTL register.

//

//*****************************************************************************

#define PWM_1_CTL_LATCH         0x00040000  // Latch Fault Input

#define PWM_1_CTL_MINFLTPER     0x00020000  // Minimum Fault Period

#define PWM_1_CTL_FLTSRC        0x00010000  // Fault Condition Source

#define PWM_1_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode

#define PWM_1_CTL_DBFALLUPD_I   0x00000000  // Immediate

#define PWM_1_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized

#define PWM_1_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized

#define PWM_1_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode

#define PWM_1_CTL_DBRISEUPD_I   0x00000000  // Immediate

#define PWM_1_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized

#define PWM_1_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized

#define PWM_1_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode

#define PWM_1_CTL_DBCTLUPD_I    0x00000000  // Immediate

#define PWM_1_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized

#define PWM_1_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized

#define PWM_1_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode

#define PWM_1_CTL_GENBUPD_I     0x00000000  // Immediate

#define PWM_1_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized

#define PWM_1_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized

#define PWM_1_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode

#define PWM_1_CTL_GENAUPD_I     0x00000000  // Immediate

#define PWM_1_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized

#define PWM_1_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized

#define PWM_1_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode

#define PWM_1_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode

#define PWM_1_CTL_LOADUPD       0x00000008  // Load Register Update Mode

#define PWM_1_CTL_DEBUG         0x00000004  // Debug Mode

#define PWM_1_CTL_MODE          0x00000002  // Counter Mode

#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_INTEN register.

//

//*****************************************************************************

#define PWM_1_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB

                                            // Down

#define PWM_1_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up

#define PWM_1_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA

                                            // Down

#define PWM_1_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up

#define PWM_1_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD

#define PWM_1_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0

#define PWM_1_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB

                                            // Down

#define PWM_1_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB

                                            // Up

#define PWM_1_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA

                                            // Down

#define PWM_1_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA

                                            // Up

#define PWM_1_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD

#define PWM_1_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_RIS register.

//

//*****************************************************************************

#define PWM_1_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt

                                            // Status

#define PWM_1_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status

#define PWM_1_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt

                                            // Status

#define PWM_1_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status

#define PWM_1_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status

#define PWM_1_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_ISC register.

//

//*****************************************************************************

#define PWM_1_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt

#define PWM_1_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt

#define PWM_1_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt

#define PWM_1_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt

#define PWM_1_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt

#define PWM_1_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_LOAD register.

//

//*****************************************************************************

#define PWM_1_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value

#define PWM_1_LOAD_LOAD_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_COUNT register.

//

//*****************************************************************************

#define PWM_1_COUNT_COUNT_M     0x0000FFFF  // Counter Value

#define PWM_1_COUNT_COUNT_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_CMPA register.

//

//*****************************************************************************

#define PWM_1_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value

#define PWM_1_CMPA_COMPA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_CMPB register.

//

//*****************************************************************************

#define PWM_1_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value

#define PWM_1_CMPB_COMPB_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_GENA register.

//

//*****************************************************************************

#define PWM_1_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_1_GENA_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA

#define PWM_1_GENA_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmA Low

#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High

#define PWM_1_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_1_GENA_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA

#define PWM_1_GENA_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmA Low

#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High

#define PWM_1_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_1_GENA_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA

#define PWM_1_GENA_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmA Low

#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High

#define PWM_1_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_1_GENA_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA

#define PWM_1_GENA_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmA Low

#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High

#define PWM_1_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_1_GENA_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_1_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA

#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low

#define PWM_1_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High

#define PWM_1_GENA_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_1_GENA_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_1_GENA_ACTZERO_INV  0x00000001  // Invert pwmA

#define PWM_1_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low

#define PWM_1_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_GENB register.

//

//*****************************************************************************

#define PWM_1_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_1_GENB_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB

#define PWM_1_GENB_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmB Low

#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High

#define PWM_1_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_1_GENB_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB

#define PWM_1_GENB_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmB Low

#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High

#define PWM_1_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_1_GENB_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB

#define PWM_1_GENB_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmB Low

#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High

#define PWM_1_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_1_GENB_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_1_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB

#define PWM_1_GENB_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmB Low

#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High

#define PWM_1_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_1_GENB_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_1_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB

#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low

#define PWM_1_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High

#define PWM_1_GENB_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_1_GENB_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_1_GENB_ACTZERO_INV  0x00000001  // Invert pwmB

#define PWM_1_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low

#define PWM_1_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_DBCTL register.

//

//*****************************************************************************

#define PWM_1_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_DBRISE register.

//

//*****************************************************************************

#define PWM_1_DBRISE_RISEDELAY_M                                              \

                                0x00000FFF  // Dead-Band Rise Delay

#define PWM_1_DBRISE_RISEDELAY_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_DBFALL register.

//

//*****************************************************************************

#define PWM_1_DBFALL_FALLDELAY_M                                              \

                                0x00000FFF  // Dead-Band Fall Delay

#define PWM_1_DBFALL_FALLDELAY_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_FLTSRC0

// register.

//

//*****************************************************************************

#define PWM_1_FLTSRC0_FAULT3    0x00000008  // Fault3 Input

#define PWM_1_FLTSRC0_FAULT2    0x00000004  // Fault2 Input

#define PWM_1_FLTSRC0_FAULT1    0x00000002  // Fault1 Input

#define PWM_1_FLTSRC0_FAULT0    0x00000001  // Fault0 Input


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_FLTSRC1

// register.

//

//*****************************************************************************

#define PWM_1_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7

#define PWM_1_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6

#define PWM_1_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5

#define PWM_1_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4

#define PWM_1_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3

#define PWM_1_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2

#define PWM_1_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1

#define PWM_1_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_MINFLTPER

// register.

//

//*****************************************************************************

#define PWM_1_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period

#define PWM_1_MINFLTPER_MFP_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_CTL register.

//

//*****************************************************************************

#define PWM_2_CTL_LATCH         0x00040000  // Latch Fault Input

#define PWM_2_CTL_MINFLTPER     0x00020000  // Minimum Fault Period

#define PWM_2_CTL_FLTSRC        0x00010000  // Fault Condition Source

#define PWM_2_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode

#define PWM_2_CTL_DBFALLUPD_I   0x00000000  // Immediate

#define PWM_2_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized

#define PWM_2_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized

#define PWM_2_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode

#define PWM_2_CTL_DBRISEUPD_I   0x00000000  // Immediate

#define PWM_2_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized

#define PWM_2_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized

#define PWM_2_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode

#define PWM_2_CTL_DBCTLUPD_I    0x00000000  // Immediate

#define PWM_2_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized

#define PWM_2_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized

#define PWM_2_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode

#define PWM_2_CTL_GENBUPD_I     0x00000000  // Immediate

#define PWM_2_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized

#define PWM_2_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized

#define PWM_2_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode

#define PWM_2_CTL_GENAUPD_I     0x00000000  // Immediate

#define PWM_2_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized

#define PWM_2_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized

#define PWM_2_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode

#define PWM_2_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode

#define PWM_2_CTL_LOADUPD       0x00000008  // Load Register Update Mode

#define PWM_2_CTL_DEBUG         0x00000004  // Debug Mode

#define PWM_2_CTL_MODE          0x00000002  // Counter Mode

#define PWM_2_CTL_ENABLE        0x00000001  // PWM Block Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_INTEN register.

//

//*****************************************************************************

#define PWM_2_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB

                                            // Down

#define PWM_2_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up

#define PWM_2_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA

                                            // Down

#define PWM_2_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up

#define PWM_2_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD

#define PWM_2_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0

#define PWM_2_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB

                                            // Down

#define PWM_2_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB

                                            // Up

#define PWM_2_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA

                                            // Down

#define PWM_2_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA

                                            // Up

#define PWM_2_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD

#define PWM_2_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_RIS register.

//

//*****************************************************************************

#define PWM_2_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt

                                            // Status

#define PWM_2_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status

#define PWM_2_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt

                                            // Status

#define PWM_2_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status

#define PWM_2_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status

#define PWM_2_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_ISC register.

//

//*****************************************************************************

#define PWM_2_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt

#define PWM_2_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt

#define PWM_2_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt

#define PWM_2_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt

#define PWM_2_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt

#define PWM_2_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_LOAD register.

//

//*****************************************************************************

#define PWM_2_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value

#define PWM_2_LOAD_LOAD_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_COUNT register.

//

//*****************************************************************************

#define PWM_2_COUNT_COUNT_M     0x0000FFFF  // Counter Value

#define PWM_2_COUNT_COUNT_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_CMPA register.

//

//*****************************************************************************

#define PWM_2_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value

#define PWM_2_CMPA_COMPA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_CMPB register.

//

//*****************************************************************************

#define PWM_2_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value

#define PWM_2_CMPB_COMPB_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_GENA register.

//

//*****************************************************************************

#define PWM_2_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_2_GENA_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA

#define PWM_2_GENA_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmA Low

#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High

#define PWM_2_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_2_GENA_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA

#define PWM_2_GENA_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmA Low

#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High

#define PWM_2_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_2_GENA_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA

#define PWM_2_GENA_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmA Low

#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High

#define PWM_2_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_2_GENA_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA

#define PWM_2_GENA_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmA Low

#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High

#define PWM_2_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_2_GENA_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_2_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA

#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low

#define PWM_2_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High

#define PWM_2_GENA_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_2_GENA_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_2_GENA_ACTZERO_INV  0x00000001  // Invert pwmA

#define PWM_2_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low

#define PWM_2_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_GENB register.

//

//*****************************************************************************

#define PWM_2_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_2_GENB_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB

#define PWM_2_GENB_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmB Low

#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High

#define PWM_2_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_2_GENB_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB

#define PWM_2_GENB_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmB Low

#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High

#define PWM_2_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_2_GENB_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB

#define PWM_2_GENB_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmB Low

#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High

#define PWM_2_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_2_GENB_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_2_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB

#define PWM_2_GENB_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmB Low

#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High

#define PWM_2_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_2_GENB_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_2_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB

#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low

#define PWM_2_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High

#define PWM_2_GENB_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_2_GENB_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_2_GENB_ACTZERO_INV  0x00000001  // Invert pwmB

#define PWM_2_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low

#define PWM_2_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_DBCTL register.

//

//*****************************************************************************

#define PWM_2_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_DBRISE register.

//

//*****************************************************************************

#define PWM_2_DBRISE_RISEDELAY_M                                              \

                                0x00000FFF  // Dead-Band Rise Delay

#define PWM_2_DBRISE_RISEDELAY_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_DBFALL register.

//

//*****************************************************************************

#define PWM_2_DBFALL_FALLDELAY_M                                              \

                                0x00000FFF  // Dead-Band Fall Delay

#define PWM_2_DBFALL_FALLDELAY_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_FLTSRC0

// register.

//

//*****************************************************************************

#define PWM_2_FLTSRC0_FAULT3    0x00000008  // Fault3 Input

#define PWM_2_FLTSRC0_FAULT2    0x00000004  // Fault2 Input

#define PWM_2_FLTSRC0_FAULT1    0x00000002  // Fault1 Input

#define PWM_2_FLTSRC0_FAULT0    0x00000001  // Fault0 Input


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_FLTSRC1

// register.

//

//*****************************************************************************

#define PWM_2_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7

#define PWM_2_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6

#define PWM_2_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5

#define PWM_2_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4

#define PWM_2_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3

#define PWM_2_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2

#define PWM_2_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1

#define PWM_2_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_MINFLTPER

// register.

//

//*****************************************************************************

#define PWM_2_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period

#define PWM_2_MINFLTPER_MFP_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_CTL register.

//

//*****************************************************************************

#define PWM_3_CTL_LATCH         0x00040000  // Latch Fault Input

#define PWM_3_CTL_MINFLTPER     0x00020000  // Minimum Fault Period

#define PWM_3_CTL_FLTSRC        0x00010000  // Fault Condition Source

#define PWM_3_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode

#define PWM_3_CTL_DBFALLUPD_I   0x00000000  // Immediate

#define PWM_3_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized

#define PWM_3_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized

#define PWM_3_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode

#define PWM_3_CTL_DBRISEUPD_I   0x00000000  // Immediate

#define PWM_3_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized

#define PWM_3_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized

#define PWM_3_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode

#define PWM_3_CTL_DBCTLUPD_I    0x00000000  // Immediate

#define PWM_3_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized

#define PWM_3_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized

#define PWM_3_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode

#define PWM_3_CTL_GENBUPD_I     0x00000000  // Immediate

#define PWM_3_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized

#define PWM_3_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized

#define PWM_3_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode

#define PWM_3_CTL_GENAUPD_I     0x00000000  // Immediate

#define PWM_3_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized

#define PWM_3_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized

#define PWM_3_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode

#define PWM_3_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode

#define PWM_3_CTL_LOADUPD       0x00000008  // Load Register Update Mode

#define PWM_3_CTL_DEBUG         0x00000004  // Debug Mode

#define PWM_3_CTL_MODE          0x00000002  // Counter Mode

#define PWM_3_CTL_ENABLE        0x00000001  // PWM Block Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_INTEN register.

//

//*****************************************************************************

#define PWM_3_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB

                                            // Down

#define PWM_3_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up

#define PWM_3_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA

                                            // Down

#define PWM_3_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up

#define PWM_3_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD

#define PWM_3_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0

#define PWM_3_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB

                                            // Down

#define PWM_3_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB

                                            // Up

#define PWM_3_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA

                                            // Down

#define PWM_3_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA

                                            // Up

#define PWM_3_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD

#define PWM_3_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_RIS register.

//

//*****************************************************************************

#define PWM_3_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt

                                            // Status

#define PWM_3_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status

#define PWM_3_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt

                                            // Status

#define PWM_3_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status

#define PWM_3_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status

#define PWM_3_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_ISC register.

//

//*****************************************************************************

#define PWM_3_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt

#define PWM_3_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt

#define PWM_3_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt

#define PWM_3_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt

#define PWM_3_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt

#define PWM_3_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_LOAD register.

//

//*****************************************************************************

#define PWM_3_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value

#define PWM_3_LOAD_LOAD_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_COUNT register.

//

//*****************************************************************************

#define PWM_3_COUNT_COUNT_M     0x0000FFFF  // Counter Value

#define PWM_3_COUNT_COUNT_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_CMPA register.

//

//*****************************************************************************

#define PWM_3_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value

#define PWM_3_CMPA_COMPA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_CMPB register.

//

//*****************************************************************************

#define PWM_3_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value

#define PWM_3_CMPB_COMPB_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_GENA register.

//

//*****************************************************************************

#define PWM_3_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_3_GENA_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA

#define PWM_3_GENA_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmA Low

#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High

#define PWM_3_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_3_GENA_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA

#define PWM_3_GENA_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmA Low

#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High

#define PWM_3_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_3_GENA_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA

#define PWM_3_GENA_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmA Low

#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High

#define PWM_3_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_3_GENA_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA

#define PWM_3_GENA_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmA Low

#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High

#define PWM_3_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_3_GENA_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_3_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA

#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low

#define PWM_3_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High

#define PWM_3_GENA_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_3_GENA_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_3_GENA_ACTZERO_INV  0x00000001  // Invert pwmA

#define PWM_3_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low

#define PWM_3_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_GENB register.

//

//*****************************************************************************

#define PWM_3_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down

#define PWM_3_GENB_ACTCMPBD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB

#define PWM_3_GENB_ACTCMPBD_ZERO                                              \

                                0x00000800  // Drive pwmB Low

#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High

#define PWM_3_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up

#define PWM_3_GENB_ACTCMPBU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB

#define PWM_3_GENB_ACTCMPBU_ZERO                                              \

                                0x00000200  // Drive pwmB Low

#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High

#define PWM_3_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down

#define PWM_3_GENB_ACTCMPAD_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB

#define PWM_3_GENB_ACTCMPAD_ZERO                                              \

                                0x00000080  // Drive pwmB Low

#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High

#define PWM_3_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up

#define PWM_3_GENB_ACTCMPAU_NONE                                              \

                                0x00000000  // Do nothing

#define PWM_3_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB

#define PWM_3_GENB_ACTCMPAU_ZERO                                              \

                                0x00000020  // Drive pwmB Low

#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High

#define PWM_3_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD

#define PWM_3_GENB_ACTLOAD_NONE 0x00000000  // Do nothing

#define PWM_3_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB

#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low

#define PWM_3_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High

#define PWM_3_GENB_ACTZERO_M    0x00000003  // Action for Counter=0

#define PWM_3_GENB_ACTZERO_NONE 0x00000000  // Do nothing

#define PWM_3_GENB_ACTZERO_INV  0x00000001  // Invert pwmB

#define PWM_3_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low

#define PWM_3_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_DBCTL register.

//

//*****************************************************************************

#define PWM_3_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_DBRISE register.

//

//*****************************************************************************

#define PWM_3_DBRISE_RISEDELAY_M                                              \

                                0x00000FFF  // Dead-Band Rise Delay

#define PWM_3_DBRISE_RISEDELAY_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_DBFALL register.

//

//*****************************************************************************

#define PWM_3_DBFALL_FALLDELAY_M                                              \

                                0x00000FFF  // Dead-Band Fall Delay

#define PWM_3_DBFALL_FALLDELAY_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_FLTSRC0

// register.

//

//*****************************************************************************

#define PWM_3_FLTSRC0_FAULT3    0x00000008  // Fault3 Input

#define PWM_3_FLTSRC0_FAULT2    0x00000004  // Fault2 Input

#define PWM_3_FLTSRC0_FAULT1    0x00000002  // Fault1 Input

#define PWM_3_FLTSRC0_FAULT0    0x00000001  // Fault0 Input


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_FLTSRC1

// register.

//

//*****************************************************************************

#define PWM_3_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7

#define PWM_3_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6

#define PWM_3_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5

#define PWM_3_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4

#define PWM_3_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3

#define PWM_3_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2

#define PWM_3_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1

#define PWM_3_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_MINFLTPER

// register.

//

//*****************************************************************************

#define PWM_3_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period

#define PWM_3_MINFLTPER_MFP_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.

//

//*****************************************************************************

#define PWM_0_FLTSEN_FAULT3     0x00000008  // Fault3 Sense

#define PWM_0_FLTSEN_FAULT2     0x00000004  // Fault2 Sense

#define PWM_0_FLTSEN_FAULT1     0x00000002  // Fault1 Sense

#define PWM_0_FLTSEN_FAULT0     0x00000001  // Fault0 Sense


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0

// register.

//

//*****************************************************************************

#define PWM_0_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3

#define PWM_0_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2

#define PWM_0_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1

#define PWM_0_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1

// register.

//

//*****************************************************************************

#define PWM_0_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger

#define PWM_0_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger

#define PWM_0_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger

#define PWM_0_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger

#define PWM_0_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger

#define PWM_0_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger

#define PWM_0_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger

#define PWM_0_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.

//

//*****************************************************************************

#define PWM_1_FLTSEN_FAULT3     0x00000008  // Fault3 Sense

#define PWM_1_FLTSEN_FAULT2     0x00000004  // Fault2 Sense

#define PWM_1_FLTSEN_FAULT1     0x00000002  // Fault1 Sense

#define PWM_1_FLTSEN_FAULT0     0x00000001  // Fault0 Sense


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0

// register.

//

//*****************************************************************************

#define PWM_1_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3

#define PWM_1_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2

#define PWM_1_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1

#define PWM_1_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1

// register.

//

//*****************************************************************************

#define PWM_1_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger

#define PWM_1_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger

#define PWM_1_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger

#define PWM_1_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger

#define PWM_1_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger

#define PWM_1_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger

#define PWM_1_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger

#define PWM_1_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.

//

//*****************************************************************************

#define PWM_2_FLTSEN_FAULT3     0x00000008  // Fault3 Sense

#define PWM_2_FLTSEN_FAULT2     0x00000004  // Fault2 Sense

#define PWM_2_FLTSEN_FAULT1     0x00000002  // Fault1 Sense

#define PWM_2_FLTSEN_FAULT0     0x00000001  // Fault0 Sense


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0

// register.

//

//*****************************************************************************

#define PWM_2_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3

#define PWM_2_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2

#define PWM_2_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1

#define PWM_2_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1

// register.

//

//*****************************************************************************

#define PWM_2_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger

#define PWM_2_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger

#define PWM_2_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger

#define PWM_2_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger

#define PWM_2_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger

#define PWM_2_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger

#define PWM_2_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger

#define PWM_2_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.

//

//*****************************************************************************

#define PWM_3_FLTSEN_FAULT3     0x00000008  // Fault3 Sense

#define PWM_3_FLTSEN_FAULT2     0x00000004  // Fault2 Sense

#define PWM_3_FLTSEN_FAULT1     0x00000002  // Fault1 Sense

#define PWM_3_FLTSEN_FAULT0     0x00000001  // Fault0 Sense


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0

// register.

//

//*****************************************************************************

#define PWM_3_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3

#define PWM_3_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2

#define PWM_3_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1

#define PWM_3_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1

// register.

//

//*****************************************************************************

#define PWM_3_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger

#define PWM_3_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger

#define PWM_3_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger

#define PWM_3_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger

#define PWM_3_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger

#define PWM_3_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger

#define PWM_3_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger

#define PWM_3_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger


//*****************************************************************************

//

// The following are defines for the bit fields in the PWM_O_PP register.

//

//*****************************************************************************

#define PWM_PP_ONE              0x00000400  // One-Shot Mode

#define PWM_PP_EFAULT           0x00000200  // Extended Fault

#define PWM_PP_ESYNC            0x00000100  // Extended Synchronization

#define PWM_PP_FCNT_M           0x000000F0  // Fault Inputs (per PWM unit)

#define PWM_PP_GCNT_M           0x0000000F  // Generators

#define PWM_PP_FCNT_S           4

#define PWM_PP_GCNT_S           0


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_CTL register.

//

//*****************************************************************************

#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count

#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter

#define QEI_CTL_STALLEN         0x00001000  // Stall QEI

#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse

#define QEI_CTL_INVB            0x00000400  // Invert PhB

#define QEI_CTL_INVA            0x00000200  // Invert PhA

#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity

#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1

#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2

#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4

#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8

#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16

#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32

#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64

#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128

#define QEI_CTL_VELEN           0x00000020  // Capture Velocity

#define QEI_CTL_RESMODE         0x00000010  // Reset Mode

#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode

#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode

#define QEI_CTL_SWAP            0x00000002  // Swap Signals

#define QEI_CTL_ENABLE          0x00000001  // Enable QEI

#define QEI_CTL_FILTCNT_S       16


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_STAT register.

//

//*****************************************************************************

#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation

#define QEI_STAT_ERROR          0x00000001  // Error Detected


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_POS register.

//

//*****************************************************************************

#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator

                                            // Value

#define QEI_POS_S               0


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_MAXPOS register.

//

//*****************************************************************************

#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator

                                            // Value

#define QEI_MAXPOS_S            0


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_LOAD register.

//

//*****************************************************************************

#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value

#define QEI_LOAD_S              0


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_TIME register.

//

//*****************************************************************************

#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value

#define QEI_TIME_S              0


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_COUNT register.

//

//*****************************************************************************

#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count

#define QEI_COUNT_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_SPEED register.

//

//*****************************************************************************

#define QEI_SPEED_M             0xFFFFFFFF  // Velocity

#define QEI_SPEED_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_INTEN register.

//

//*****************************************************************************

#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable

#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt

                                            // Enable

#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable

#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt

                                            // Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_RIS register.

//

//*****************************************************************************

#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected

#define QEI_RIS_DIR             0x00000004  // Direction Change Detected

#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired

#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted


//*****************************************************************************

//

// The following are defines for the bit fields in the QEI_O_ISC register.

//

//*****************************************************************************

#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt

#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt

#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt

#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_CFG register.

//

//*****************************************************************************

#define TIMER_CFG_M             0x00000007  // GPTM Configuration

#define TIMER_CFG_32_BIT_TIMER  0x00000000  // For a 16/32-bit timer, this

                                            // value selects the 32-bit timer

                                            // configuration

#define TIMER_CFG_32_BIT_RTC    0x00000001  // For a 16/32-bit timer, this

                                            // value selects the 32-bit

                                            // real-time clock (RTC) counter

                                            // configuration

#define TIMER_CFG_16_BIT        0x00000004  // For a 16/32-bit timer, this

                                            // value selects the 16-bit timer

                                            // configuration


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAMR register.

//

//*****************************************************************************

#define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy

                                            // Operation

#define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register

                                            // Update

#define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt

                                            // Enable

#define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write

#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode

#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger

#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt

                                            // Enable

#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction

#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode

                                            // Select

#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode

#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode

#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode

#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode

#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBMR register.

//

//*****************************************************************************

#define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy

                                            // Operation

#define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register

                                            // Update

#define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt

                                            // Enable

#define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write

#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode

#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger

#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt

                                            // Enable

#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction

#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode

                                            // Select

#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode

#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode

#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode

#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode

#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_CTL register.

//

//*****************************************************************************

#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level

#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger

                                            // Enable

#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode

#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge

#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge

#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges

#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable

#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable

#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level

#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger

                                            // Enable

#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Stall Enable

#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode

#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge

#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge

#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges

#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable

#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_SYNC register.

//

//*****************************************************************************

#define TIMER_SYNC_SYNCWT5_M    0x00C00000  // Synchronize GPTM 32/64-Bit Timer

                                            // 5

#define TIMER_SYNC_SYNCWT5_NONE 0x00000000  // GPTM 32/64-Bit Timer 5 is not

                                            // affected

#define TIMER_SYNC_SYNCWT5_TA   0x00400000  // A timeout event for Timer A of

                                            // GPTM 32/64-Bit Timer 5 is

                                            // triggered

#define TIMER_SYNC_SYNCWT5_TB   0x00800000  // A timeout event for Timer B of

                                            // GPTM 32/64-Bit Timer 5 is

                                            // triggered

#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000  // A timeout event for both Timer A

                                            // and Timer B of GPTM 32/64-Bit

                                            // Timer 5 is triggered

#define TIMER_SYNC_SYNCWT4_M    0x00300000  // Synchronize GPTM 32/64-Bit Timer

                                            // 4

#define TIMER_SYNC_SYNCWT4_NONE 0x00000000  // GPTM 32/64-Bit Timer 4 is not

                                            // affected

#define TIMER_SYNC_SYNCWT4_TA   0x00100000  // A timeout event for Timer A of

                                            // GPTM 32/64-Bit Timer 4 is

                                            // triggered

#define TIMER_SYNC_SYNCWT4_TB   0x00200000  // A timeout event for Timer B of

                                            // GPTM 32/64-Bit Timer 4 is

                                            // triggered

#define TIMER_SYNC_SYNCWT4_TATB 0x00300000  // A timeout event for both Timer A

                                            // and Timer B of GPTM 32/64-Bit

                                            // Timer 4 is triggered

#define TIMER_SYNC_SYNCWT3_M    0x000C0000  // Synchronize GPTM 32/64-Bit Timer

                                            // 3

#define TIMER_SYNC_SYNCWT3_NONE 0x00000000  // GPTM 32/64-Bit Timer 3 is not

                                            // affected

#define TIMER_SYNC_SYNCWT3_TA   0x00040000  // A timeout event for Timer A of

                                            // GPTM 32/64-Bit Timer 3 is

                                            // triggered

#define TIMER_SYNC_SYNCWT3_TB   0x00080000  // A timeout event for Timer B of

                                            // GPTM 32/64-Bit Timer 3 is

                                            // triggered

#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000  // A timeout event for both Timer A

                                            // and Timer B of GPTM 32/64-Bit

                                            // Timer 3 is triggered

#define TIMER_SYNC_SYNCWT2_M    0x00030000  // Synchronize GPTM 32/64-Bit Timer

                                            // 2

#define TIMER_SYNC_SYNCWT2_NONE 0x00000000  // GPTM 32/64-Bit Timer 2 is not

                                            // affected

#define TIMER_SYNC_SYNCWT2_TA   0x00010000  // A timeout event for Timer A of

                                            // GPTM 32/64-Bit Timer 2 is

                                            // triggered

#define TIMER_SYNC_SYNCWT2_TB   0x00020000  // A timeout event for Timer B of

                                            // GPTM 32/64-Bit Timer 2 is

                                            // triggered

#define TIMER_SYNC_SYNCWT2_TATB 0x00030000  // A timeout event for both Timer A

                                            // and Timer B of GPTM 32/64-Bit

                                            // Timer 2 is triggered

#define TIMER_SYNC_SYNCWT1_M    0x0000C000  // Synchronize GPTM 32/64-Bit Timer

                                            // 1

#define TIMER_SYNC_SYNCWT1_NONE 0x00000000  // GPTM 32/64-Bit Timer 1 is not

                                            // affected

#define TIMER_SYNC_SYNCWT1_TA   0x00004000  // A timeout event for Timer A of

                                            // GPTM 32/64-Bit Timer 1 is

                                            // triggered

#define TIMER_SYNC_SYNCWT1_TB   0x00008000  // A timeout event for Timer B of

                                            // GPTM 32/64-Bit Timer 1 is

                                            // triggered

#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000  // A timeout event for both Timer A

                                            // and Timer B of GPTM 32/64-Bit

                                            // Timer 1 is triggered

#define TIMER_SYNC_SYNCWT0_M    0x00003000  // Synchronize GPTM 32/64-Bit Timer

                                            // 0

#define TIMER_SYNC_SYNCWT0_NONE 0x00000000  // GPTM 32/64-Bit Timer 0 is not

                                            // affected

#define TIMER_SYNC_SYNCWT0_TA   0x00001000  // A timeout event for Timer A of

                                            // GPTM 32/64-Bit Timer 0 is

                                            // triggered

#define TIMER_SYNC_SYNCWT0_TB   0x00002000  // A timeout event for Timer B of

                                            // GPTM 32/64-Bit Timer 0 is

                                            // triggered

#define TIMER_SYNC_SYNCWT0_TATB 0x00003000  // A timeout event for both Timer A

                                            // and Timer B of GPTM 32/64-Bit

                                            // Timer 0 is triggered

#define TIMER_SYNC_SYNCT5_M     0x00000C00  // Synchronize GPTM Timer 5

#define TIMER_SYNC_SYNCT5_NONE  0x00000000  // GPTM5 is not affected

#define TIMER_SYNC_SYNCT5_TA    0x00000400  // A timeout event for Timer A of

                                            // GPTM5 is triggered

#define TIMER_SYNC_SYNCT5_TB    0x00000800  // A timeout event for Timer B of

                                            // GPTM5 is triggered

#define TIMER_SYNC_SYNCT5_TATB  0x00000C00  // A timeout event for both Timer A

                                            // and Timer B of GPTM5 is

                                            // triggered

#define TIMER_SYNC_SYNCT4_M     0x00000300  // Synchronize GPTM Timer 4

#define TIMER_SYNC_SYNCT4_NONE  0x00000000  // GPTM4 is not affected

#define TIMER_SYNC_SYNCT4_TA    0x00000100  // A timeout event for Timer A of

                                            // GPTM4 is triggered

#define TIMER_SYNC_SYNCT4_TB    0x00000200  // A timeout event for Timer B of

                                            // GPTM4 is triggered

#define TIMER_SYNC_SYNCT4_TATB  0x00000300  // A timeout event for both Timer A

                                            // and Timer B of GPTM4 is

                                            // triggered

#define TIMER_SYNC_SYNCT3_M     0x000000C0  // Synchronize GPTM Timer 3

#define TIMER_SYNC_SYNCT3_NONE  0x00000000  // GPTM3 is not affected

#define TIMER_SYNC_SYNCT3_TA    0x00000040  // A timeout event for Timer A of

                                            // GPTM3 is triggered

#define TIMER_SYNC_SYNCT3_TB    0x00000080  // A timeout event for Timer B of

                                            // GPTM3 is triggered

#define TIMER_SYNC_SYNCT3_TATB  0x000000C0  // A timeout event for both Timer A

                                            // and Timer B of GPTM3 is

                                            // triggered

#define TIMER_SYNC_SYNCT2_M     0x00000030  // Synchronize GPTM Timer 2

#define TIMER_SYNC_SYNCT2_NONE  0x00000000  // GPTM2 is not affected

#define TIMER_SYNC_SYNCT2_TA    0x00000010  // A timeout event for Timer A of

                                            // GPTM2 is triggered

#define TIMER_SYNC_SYNCT2_TB    0x00000020  // A timeout event for Timer B of

                                            // GPTM2 is triggered

#define TIMER_SYNC_SYNCT2_TATB  0x00000030  // A timeout event for both Timer A

                                            // and Timer B of GPTM2 is

                                            // triggered

#define TIMER_SYNC_SYNCT1_M     0x0000000C  // Synchronize GPTM Timer 1

#define TIMER_SYNC_SYNCT1_NONE  0x00000000  // GPTM1 is not affected

#define TIMER_SYNC_SYNCT1_TA    0x00000004  // A timeout event for Timer A of

                                            // GPTM1 is triggered

#define TIMER_SYNC_SYNCT1_TB    0x00000008  // A timeout event for Timer B of

                                            // GPTM1 is triggered

#define TIMER_SYNC_SYNCT1_TATB  0x0000000C  // A timeout event for both Timer A

                                            // and Timer B of GPTM1 is

                                            // triggered

#define TIMER_SYNC_SYNCT0_M     0x00000003  // Synchronize GPTM Timer 0

#define TIMER_SYNC_SYNCT0_NONE  0x00000000  // GPTM0 is not affected

#define TIMER_SYNC_SYNCT0_TA    0x00000001  // A timeout event for Timer A of

                                            // GPTM0 is triggered

#define TIMER_SYNC_SYNCT0_TB    0x00000002  // A timeout event for Timer B of

                                            // GPTM0 is triggered

#define TIMER_SYNC_SYNCT0_TATB  0x00000003  // A timeout event for both Timer A

                                            // and Timer B of GPTM0 is

                                            // triggered


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_IMR register.

//

//*****************************************************************************

#define TIMER_IMR_WUEIM         0x00010000  // 32/64-Bit Wide GPTM Write Update

                                            // Error Interrupt Mask

#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Match Interrupt

                                            // Mask

#define TIMER_IMR_CBEIM         0x00000400  // GPTM Timer B Capture Mode Event

                                            // Interrupt Mask

#define TIMER_IMR_CBMIM         0x00000200  // GPTM Timer B Capture Mode Match

                                            // Interrupt Mask

#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt

                                            // Mask

#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Match Interrupt

                                            // Mask

#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask

#define TIMER_IMR_CAEIM         0x00000004  // GPTM Timer A Capture Mode Event

                                            // Interrupt Mask

#define TIMER_IMR_CAMIM         0x00000002  // GPTM Timer A Capture Mode Match

                                            // Interrupt Mask

#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt

                                            // Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_RIS register.

//

//*****************************************************************************

#define TIMER_RIS_WUERIS        0x00010000  // 32/64-Bit Wide GPTM Write Update

                                            // Error Raw Interrupt Status

#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Match Raw Interrupt

#define TIMER_RIS_CBERIS        0x00000400  // GPTM Timer B Capture Mode Event

                                            // Raw Interrupt

#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Timer B Capture Mode Match

                                            // Raw Interrupt

#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw

                                            // Interrupt

#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Match Raw Interrupt

#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt

#define TIMER_RIS_CAERIS        0x00000004  // GPTM Timer A Capture Mode Event

                                            // Raw Interrupt

#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Timer A Capture Mode Match

                                            // Raw Interrupt

#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw

                                            // Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_MIS register.

//

//*****************************************************************************

#define TIMER_MIS_WUEMIS        0x00010000  // 32/64-Bit Wide GPTM Write Update

                                            // Error Masked Interrupt Status

#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Match Masked

                                            // Interrupt

#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Timer B Capture Mode Event

                                            // Masked Interrupt

#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Timer B Capture Mode Match

                                            // Masked Interrupt

#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked

                                            // Interrupt

#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Match Masked

                                            // Interrupt

#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt

#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Timer A Capture Mode Event

                                            // Masked Interrupt

#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Timer A Capture Mode Match

                                            // Masked Interrupt

#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked

                                            // Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_ICR register.

//

//*****************************************************************************

#define TIMER_ICR_WUECINT       0x00010000  // 32/64-Bit Wide GPTM Write Update

                                            // Error Interrupt Clear

#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Match Interrupt

                                            // Clear

#define TIMER_ICR_CBECINT       0x00000400  // GPTM Timer B Capture Mode Event

                                            // Interrupt Clear

#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Timer B Capture Mode Match

                                            // Interrupt Clear

#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt

                                            // Clear

#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Match Interrupt

                                            // Clear

#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear

#define TIMER_ICR_CAECINT       0x00000004  // GPTM Timer A Capture Mode Event

                                            // Interrupt Clear

#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Timer A Capture Mode Match

                                            // Interrupt Clear

#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw

                                            // Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAILR register.

//

//*****************************************************************************

#define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load

                                            // Register

#define TIMER_TAILR_S           0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBILR register.

//

//*****************************************************************************

#define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load

                                            // Register

#define TIMER_TBILR_S           0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAMATCHR

// register.

//

//*****************************************************************************

#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register

#define TIMER_TAMATCHR_TAMR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBMATCHR

// register.

//

//*****************************************************************************

#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register

#define TIMER_TBMATCHR_TBMR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAPR register.

//

//*****************************************************************************

#define TIMER_TAPR_TAPSRH_M     0x0000FF00  // GPTM Timer A Prescale High Byte

#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale

#define TIMER_TAPR_TAPSRH_S     8

#define TIMER_TAPR_TAPSR_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBPR register.

//

//*****************************************************************************

#define TIMER_TBPR_TBPSRH_M     0x0000FF00  // GPTM Timer B Prescale High Byte

#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale

#define TIMER_TBPR_TBPSRH_S     8

#define TIMER_TBPR_TBPSR_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAPMR register.

//

//*****************************************************************************

#define TIMER_TAPMR_TAPSMRH_M   0x0000FF00  // GPTM Timer A Prescale Match High

                                            // Byte

#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match

#define TIMER_TAPMR_TAPSMRH_S   8

#define TIMER_TAPMR_TAPSMR_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBPMR register.

//

//*****************************************************************************

#define TIMER_TBPMR_TBPSMRH_M   0x0000FF00  // GPTM Timer B Prescale Match High

                                            // Byte

#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match

#define TIMER_TBPMR_TBPSMRH_S   8

#define TIMER_TBPMR_TBPSMR_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAR register.

//

//*****************************************************************************

#define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register

#define TIMER_TAR_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBR register.

//

//*****************************************************************************

#define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register

#define TIMER_TBR_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAV register.

//

//*****************************************************************************

#define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value

#define TIMER_TAV_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBV register.

//

//*****************************************************************************

#define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value

#define TIMER_TBV_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_RTCPD register.

//

//*****************************************************************************

#define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value

#define TIMER_RTCPD_RTCPD_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAPS register.

//

//*****************************************************************************

#define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot

#define TIMER_TAPS_PSS_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBPS register.

//

//*****************************************************************************

#define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value

#define TIMER_TBPS_PSS_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TAPV register.

//

//*****************************************************************************

#define TIMER_TAPV_PSV_M        0x0000FFFF  // GPTM Timer A Prescaler Value

#define TIMER_TAPV_PSV_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_TBPV register.

//

//*****************************************************************************

#define TIMER_TBPV_PSV_M        0x0000FFFF  // GPTM Timer B Prescaler Value

#define TIMER_TBPV_PSV_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the TIMER_O_PP register.

//

//*****************************************************************************

#define TIMER_PP_SIZE_M         0x0000000F  // Count Size

#define TIMER_PP_SIZE_16        0x00000000  // Timer A and Timer B counters are

                                            // 16 bits each with an 8-bit

                                            // prescale counter

#define TIMER_PP_SIZE_32        0x00000001  // Timer A and Timer B counters are

                                            // 32 bits each with a 16-bit

                                            // prescale counter


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_ACTSS register.

//

//*****************************************************************************

#define ADC_ACTSS_BUSY          0x00010000  // ADC Busy

#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable

#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable

#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable

#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_RIS register.

//

//*****************************************************************************

#define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt

                                            // Status

#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status

#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status

#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status

#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_IM register.

//

//*****************************************************************************

#define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on

                                            // SS3

#define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on

                                            // SS2

#define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on

                                            // SS1

#define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on

                                            // SS0

#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask

#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask

#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask

#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_ISC register.

//

//*****************************************************************************

#define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt

                                            // Status on SS3

#define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt

                                            // Status on SS2

#define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt

                                            // Status on SS1

#define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt

                                            // Status on SS0

#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear

#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear

#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear

#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_OSTAT register.

//

//*****************************************************************************

#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow

#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow

#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow

#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_EMUX register.

//

//*****************************************************************************

#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select

#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)

#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0

#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1

#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO Pins)

#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer

#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM generator 0

#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM generator 1

#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM generator 2

#define ADC_EMUX_EM3_PWM3       0x00009000  // PWM generator 3

#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)

#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select

#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)

#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0

#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1

#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO Pins)

#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer

#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM generator 0

#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM generator 1

#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM generator 2

#define ADC_EMUX_EM2_PWM3       0x00000900  // PWM generator 3

#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)

#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select

#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)

#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0

#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1

#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO Pins)

#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer

#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM generator 0

#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM generator 1

#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM generator 2

#define ADC_EMUX_EM1_PWM3       0x00000090  // PWM generator 3

#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)

#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select

#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)

#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0

#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1

#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO Pins)

#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer

#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM generator 0

#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM generator 1

#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM generator 2

#define ADC_EMUX_EM0_PWM3       0x00000009  // PWM generator 3

#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_USTAT register.

//

//*****************************************************************************

#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow

#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow

#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow

#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_TSSEL register.

//

//*****************************************************************************

#define ADC_TSSEL_PS3_M         0x30000000  // Generator 3 PWM Module Trigger

                                            // Select

#define ADC_TSSEL_PS3_0         0x00000000  // Use Generator 3 (and its

                                            // trigger) in PWM module 0

#define ADC_TSSEL_PS3_1         0x10000000  // Use Generator 3 (and its

                                            // trigger) in PWM module 1

#define ADC_TSSEL_PS2_M         0x00300000  // Generator 2 PWM Module Trigger

                                            // Select

#define ADC_TSSEL_PS2_0         0x00000000  // Use Generator 2 (and its

                                            // trigger) in PWM module 0

#define ADC_TSSEL_PS2_1         0x00100000  // Use Generator 2 (and its

                                            // trigger) in PWM module 1

#define ADC_TSSEL_PS1_M         0x00003000  // Generator 1 PWM Module Trigger

                                            // Select

#define ADC_TSSEL_PS1_0         0x00000000  // Use Generator 1 (and its

                                            // trigger) in PWM module 0

#define ADC_TSSEL_PS1_1         0x00001000  // Use Generator 1 (and its

                                            // trigger) in PWM module 1

#define ADC_TSSEL_PS0_M         0x00000030  // Generator 0 PWM Module Trigger

                                            // Select

#define ADC_TSSEL_PS0_0         0x00000000  // Use Generator 0 (and its

                                            // trigger) in PWM module 0

#define ADC_TSSEL_PS0_1         0x00000010  // Use Generator 0 (and its

                                            // trigger) in PWM module 1


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSPRI register.

//

//*****************************************************************************

#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority

#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority

#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority

#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SPC register.

//

//*****************************************************************************

#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference

#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0

#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5

#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0

#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5

#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0

#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5

#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0

#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5

#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0

#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5

#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0

#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5

#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0

#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5

#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0

#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_PSSI register.

//

//*****************************************************************************

#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize

#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait

#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate

#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate

#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate

#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SAC register.

//

//*****************************************************************************

#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control

#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling

#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling

#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling

#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling

#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling

#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling

#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCISC register.

//

//*****************************************************************************

#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt

                                            // Status and Clear

#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt

                                            // Status and Clear

#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt

                                            // Status and Clear

#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt

                                            // Status and Clear

#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt

                                            // Status and Clear

#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt

                                            // Status and Clear

#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt

                                            // Status and Clear

#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt

                                            // Status and Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_CTL register.

//

//*****************************************************************************

#define ADC_CTL_DITHER          0x00000040  // Dither Mode Enable

#define ADC_CTL_VREF_M          0x00000001  // Voltage Reference Select

#define ADC_CTL_VREF_INTERNAL   0x00000000  // VDDA and GNDA are the voltage

                                            // references


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSMUX0 register.

//

//*****************************************************************************

#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select

#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select

#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select

#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select

#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select

#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select

#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select

#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select

#define ADC_SSMUX0_MUX7_S       28

#define ADC_SSMUX0_MUX6_S       24

#define ADC_SSMUX0_MUX5_S       20

#define ADC_SSMUX0_MUX4_S       16

#define ADC_SSMUX0_MUX3_S       12

#define ADC_SSMUX0_MUX2_S       8

#define ADC_SSMUX0_MUX1_S       4

#define ADC_SSMUX0_MUX0_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSCTL0 register.

//

//*****************************************************************************

#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select

#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable

#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence

#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Differential Input

                                            // Select

#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select

#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable

#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence

#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Differential Input

                                            // Select

#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select

#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable

#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence

#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Differential Input

                                            // Select

#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select

#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable

#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence

#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Differential Input

                                            // Select

#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select

#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable

#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence

#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Differential Input

                                            // Select

#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select

#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable

#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence

#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Differential Input

                                            // Select

#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select

#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable

#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence

#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Differential Input

                                            // Select

#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select

#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable

#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence

#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Differential Input

                                            // Select


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.

//

//*****************************************************************************

#define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data

#define ADC_SSFIFO0_DATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.

//

//*****************************************************************************

#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full

#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty

#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer

#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer

#define ADC_SSFSTAT0_HPTR_S     4

#define ADC_SSFSTAT0_TPTR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSOP0 register.

//

//*****************************************************************************

#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator

                                            // Operation

#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator

                                            // Operation

#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator

                                            // Operation

#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator

                                            // Operation

#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator

                                            // Operation

#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator

                                            // Operation

#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator

                                            // Operation

#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator

                                            // Operation


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSDC0 register.

//

//*****************************************************************************

#define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator

                                            // Select

#define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator

                                            // Select

#define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator

                                            // Select

#define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator

                                            // Select

#define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator

                                            // Select

#define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator

                                            // Select

#define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator

                                            // Select

#define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator

                                            // Select

#define ADC_SSDC0_S6DCSEL_S     24

#define ADC_SSDC0_S5DCSEL_S     20

#define ADC_SSDC0_S4DCSEL_S     16

#define ADC_SSDC0_S3DCSEL_S     12

#define ADC_SSDC0_S2DCSEL_S     8

#define ADC_SSDC0_S1DCSEL_S     4

#define ADC_SSDC0_S0DCSEL_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSMUX1 register.

//

//*****************************************************************************

#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select

#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select

#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select

#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select

#define ADC_SSMUX1_MUX3_S       12

#define ADC_SSMUX1_MUX2_S       8

#define ADC_SSMUX1_MUX1_S       4

#define ADC_SSMUX1_MUX0_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSCTL1 register.

//

//*****************************************************************************

#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select

#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable

#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence

#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Differential Input

                                            // Select

#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select

#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable

#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence

#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Differential Input

                                            // Select

#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select

#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable

#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence

#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Differential Input

                                            // Select

#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select

#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable

#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence

#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Differential Input

                                            // Select


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.

//

//*****************************************************************************

#define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data

#define ADC_SSFIFO1_DATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.

//

//*****************************************************************************

#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full

#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty

#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer

#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer

#define ADC_SSFSTAT1_HPTR_S     4

#define ADC_SSFSTAT1_TPTR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSOP1 register.

//

//*****************************************************************************

#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator

                                            // Operation

#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator

                                            // Operation

#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator

                                            // Operation

#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator

                                            // Operation


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSDC1 register.

//

//*****************************************************************************

#define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator

                                            // Select

#define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator

                                            // Select

#define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator

                                            // Select

#define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator

                                            // Select

#define ADC_SSDC1_S2DCSEL_S     8

#define ADC_SSDC1_S1DCSEL_S     4

#define ADC_SSDC1_S0DCSEL_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSMUX2 register.

//

//*****************************************************************************

#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select

#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select

#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select

#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select

#define ADC_SSMUX2_MUX3_S       12

#define ADC_SSMUX2_MUX2_S       8

#define ADC_SSMUX2_MUX1_S       4

#define ADC_SSMUX2_MUX0_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSCTL2 register.

//

//*****************************************************************************

#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select

#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable

#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence

#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Differential Input

                                            // Select

#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select

#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable

#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence

#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Differential Input

                                            // Select

#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select

#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable

#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence

#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Differential Input

                                            // Select

#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select

#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable

#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence

#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Differential Input

                                            // Select


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.

//

//*****************************************************************************

#define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data

#define ADC_SSFIFO2_DATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.

//

//*****************************************************************************

#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full

#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty

#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer

#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer

#define ADC_SSFSTAT2_HPTR_S     4

#define ADC_SSFSTAT2_TPTR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSOP2 register.

//

//*****************************************************************************

#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator

                                            // Operation

#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator

                                            // Operation

#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator

                                            // Operation

#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator

                                            // Operation


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSDC2 register.

//

//*****************************************************************************

#define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator

                                            // Select

#define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator

                                            // Select

#define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator

                                            // Select

#define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator

                                            // Select

#define ADC_SSDC2_S2DCSEL_S     8

#define ADC_SSDC2_S1DCSEL_S     4

#define ADC_SSDC2_S0DCSEL_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSMUX3 register.

//

//*****************************************************************************

#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select

#define ADC_SSMUX3_MUX0_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSCTL3 register.

//

//*****************************************************************************

#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select

#define ADC_SSCTL3_IE0          0x00000004  // Sample Interrupt Enable

#define ADC_SSCTL3_END0         0x00000002  // End of Sequence

#define ADC_SSCTL3_D0           0x00000001  // Sample Differential Input Select


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.

//

//*****************************************************************************

#define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data

#define ADC_SSFIFO3_DATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.

//

//*****************************************************************************

#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full

#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty

#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer

#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer

#define ADC_SSFSTAT3_HPTR_S     4

#define ADC_SSFSTAT3_TPTR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSOP3 register.

//

//*****************************************************************************

#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator

                                            // Operation


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_SSDC3 register.

//

//*****************************************************************************

#define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator

                                            // Select


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCRIC register.

//

//*****************************************************************************

#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7

#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6

#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5

#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4

#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3

#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2

#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1

#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0

#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7

#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6

#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5

#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4

#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3

#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2

#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1

#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL0 register.

//

//*****************************************************************************

#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL1 register.

//

//*****************************************************************************

#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL2 register.

//

//*****************************************************************************

#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL3 register.

//

//*****************************************************************************

#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL4 register.

//

//*****************************************************************************

#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL5 register.

//

//*****************************************************************************

#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL6 register.

//

//*****************************************************************************

#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCTL7 register.

//

//*****************************************************************************

#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable

#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition

#define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band

#define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band

#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band

#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode

#define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once

#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always

#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once

#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable

#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition

#define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band

#define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band

#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band

#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode

#define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always

#define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once

#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always

#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP0 register.

//

//*****************************************************************************

#define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP0_COMP1_S      16

#define ADC_DCCMP0_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP1 register.

//

//*****************************************************************************

#define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP1_COMP1_S      16

#define ADC_DCCMP1_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP2 register.

//

//*****************************************************************************

#define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP2_COMP1_S      16

#define ADC_DCCMP2_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP3 register.

//

//*****************************************************************************

#define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP3_COMP1_S      16

#define ADC_DCCMP3_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP4 register.

//

//*****************************************************************************

#define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP4_COMP1_S      16

#define ADC_DCCMP4_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP5 register.

//

//*****************************************************************************

#define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP5_COMP1_S      16

#define ADC_DCCMP5_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP6 register.

//

//*****************************************************************************

#define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP6_COMP1_S      16

#define ADC_DCCMP6_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_DCCMP7 register.

//

//*****************************************************************************

#define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1

#define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0

#define ADC_DCCMP7_COMP1_S      16

#define ADC_DCCMP7_COMP0_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_PP register.

//

//*****************************************************************************

#define ADC_PP_TS               0x00800000  // Temperature Sensor

#define ADC_PP_RSL_M            0x007C0000  // Resolution

#define ADC_PP_TYPE_M           0x00030000  // ADC Architecture

#define ADC_PP_TYPE_SAR         0x00000000  // SAR

#define ADC_PP_DC_M             0x0000FC00  // Digital Comparator Count

#define ADC_PP_CH_M             0x000003F0  // ADC Channel Count

#define ADC_PP_MSR_M            0x0000000F  // Maximum ADC Sample Rate

#define ADC_PP_MSR_125K         0x00000001  // 125 ksps

#define ADC_PP_MSR_250K         0x00000003  // 250 ksps

#define ADC_PP_MSR_500K         0x00000005  // 500 ksps

#define ADC_PP_MSR_1M           0x00000007  // 1 Msps

#define ADC_PP_RSL_S            18

#define ADC_PP_DC_S             10

#define ADC_PP_CH_S             4


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_PC register.

//

//*****************************************************************************

#define ADC_PC_SR_M             0x0000000F  // ADC Sample Rate

#define ADC_PC_SR_125K          0x00000001  // 125 ksps

#define ADC_PC_SR_250K          0x00000003  // 250 ksps

#define ADC_PC_SR_500K          0x00000005  // 500 ksps

#define ADC_PC_SR_1M            0x00000007  // 1 Msps


//*****************************************************************************

//

// The following are defines for the bit fields in the ADC_O_CC register.

//

//*****************************************************************************

#define ADC_CC_CS_M             0x0000000F  // ADC Clock Source

#define ADC_CC_CS_SYSPLL        0x00000000  // PLL VCO divided by CLKDIV

#define ADC_CC_CS_PIOSC         0x00000001  // PIOSC


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACMIS register.

//

//*****************************************************************************

#define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt

                                            // Status

#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt

                                            // Status


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACRIS register.

//

//*****************************************************************************

#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status

#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACINTEN register.

//

//*****************************************************************************

#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable

#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACREFCTL

// register.

//

//*****************************************************************************

#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable

#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range

#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref

#define COMP_ACREFCTL_VREF_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.

//

//*****************************************************************************

#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACCTL0 register.

//

//*****************************************************************************

#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable

#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive

#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+

#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+

#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference

#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value

#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense

#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL

#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge

#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge

#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge

#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value

#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense

#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL

#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge

#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge

#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge

#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.

//

//*****************************************************************************

#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_ACCTL1 register.

//

//*****************************************************************************

#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable

#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive

#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+

#define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+

#define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference

#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value

#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense

#define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL

#define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge

#define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge

#define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge

#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value

#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense

#define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL

#define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge

#define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge

#define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge

#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert


//*****************************************************************************

//

// The following are defines for the bit fields in the COMP_O_PP register.

//

//*****************************************************************************

#define COMP_PP_C1O             0x00020000  // Comparator Output 1 Present

#define COMP_PP_C0O             0x00010000  // Comparator Output 0 Present

#define COMP_PP_CMP1            0x00000002  // Comparator 1 Present

#define COMP_PP_CMP0            0x00000001  // Comparator 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_CTL register.

//

//*****************************************************************************

#define CAN_CTL_TEST            0x00000080  // Test Mode Enable

#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable

#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission

#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable

#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable

#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable

#define CAN_CTL_INIT            0x00000001  // Initialization


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_STS register.

//

//*****************************************************************************

#define CAN_STS_BOFF            0x00000080  // Bus-Off Status

#define CAN_STS_EWARN           0x00000040  // Warning Status

#define CAN_STS_EPASS           0x00000020  // Error Passive

#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully

#define CAN_STS_TXOK            0x00000008  // Transmitted a Message

                                            // Successfully

#define CAN_STS_LEC_M           0x00000007  // Last Error Code

#define CAN_STS_LEC_NONE        0x00000000  // No Error

#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error

#define CAN_STS_LEC_FORM        0x00000002  // Format Error

#define CAN_STS_LEC_ACK         0x00000003  // ACK Error

#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error

#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error

#define CAN_STS_LEC_CRC         0x00000006  // CRC Error

#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_ERR register.

//

//*****************************************************************************

#define CAN_ERR_RP              0x00008000  // Received Error Passive

#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter

#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter

#define CAN_ERR_REC_S           8

#define CAN_ERR_TEC_S           0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_BIT register.

//

//*****************************************************************************

#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point

#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point

#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width

#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler

#define CAN_BIT_TSEG2_S         12

#define CAN_BIT_TSEG1_S         8

#define CAN_BIT_SJW_S           6

#define CAN_BIT_BRP_S           0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_INT register.

//

//*****************************************************************************

#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier

#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending

#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_TST register.

//

//*****************************************************************************

#define CAN_TST_RX              0x00000080  // Receive Observation

#define CAN_TST_TX_M            0x00000060  // Transmit Control

#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control

#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point

#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low

#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High

#define CAN_TST_LBACK           0x00000010  // Loopback Mode

#define CAN_TST_SILENT          0x00000008  // Silent Mode

#define CAN_TST_BASIC           0x00000004  // Basic Mode


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_BRPE register.

//

//*****************************************************************************

#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension

#define CAN_BRPE_BRPE_S         0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1CRQ register.

//

//*****************************************************************************

#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag

#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number

#define CAN_IF1CRQ_MNUM_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1CMSK register.

//

//*****************************************************************************

#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read

#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits

#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits

#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits

#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit

#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data

#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request

#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3

#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.

//

//*****************************************************************************

#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask

#define CAN_IF1MSK1_IDMSK_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.

//

//*****************************************************************************

#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier

#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction

#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask

#define CAN_IF1MSK2_IDMSK_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.

//

//*****************************************************************************

#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier

#define CAN_IF1ARB1_ID_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.

//

//*****************************************************************************

#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid

#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier

#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction

#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier

#define CAN_IF1ARB2_ID_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1MCTL register.

//

//*****************************************************************************

#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data

#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost

#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending

#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask

#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable

#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable

#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable

#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request

#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer

#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code

#define CAN_IF1MCTL_DLC_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1DA1 register.

//

//*****************************************************************************

#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data

#define CAN_IF1DA1_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1DA2 register.

//

//*****************************************************************************

#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data

#define CAN_IF1DA2_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1DB1 register.

//

//*****************************************************************************

#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data

#define CAN_IF1DB1_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF1DB2 register.

//

//*****************************************************************************

#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data

#define CAN_IF1DB2_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2CRQ register.

//

//*****************************************************************************

#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag

#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number

#define CAN_IF2CRQ_MNUM_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2CMSK register.

//

//*****************************************************************************

#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read

#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits

#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits

#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits

#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit

#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data

#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request

#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3

#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.

//

//*****************************************************************************

#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask

#define CAN_IF2MSK1_IDMSK_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.

//

//*****************************************************************************

#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier

#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction

#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask

#define CAN_IF2MSK2_IDMSK_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.

//

//*****************************************************************************

#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier

#define CAN_IF2ARB1_ID_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.

//

//*****************************************************************************

#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid

#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier

#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction

#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier

#define CAN_IF2ARB2_ID_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2MCTL register.

//

//*****************************************************************************

#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data

#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost

#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending

#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask

#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable

#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable

#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable

#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request

#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer

#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code

#define CAN_IF2MCTL_DLC_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2DA1 register.

//

//*****************************************************************************

#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data

#define CAN_IF2DA1_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2DA2 register.

//

//*****************************************************************************

#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data

#define CAN_IF2DA2_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2DB1 register.

//

//*****************************************************************************

#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data

#define CAN_IF2DB1_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_IF2DB2 register.

//

//*****************************************************************************

#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data

#define CAN_IF2DB2_DATA_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_TXRQ1 register.

//

//*****************************************************************************

#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits

#define CAN_TXRQ1_TXRQST_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_TXRQ2 register.

//

//*****************************************************************************

#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits

#define CAN_TXRQ2_TXRQST_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_NWDA1 register.

//

//*****************************************************************************

#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits

#define CAN_NWDA1_NEWDAT_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_NWDA2 register.

//

//*****************************************************************************

#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits

#define CAN_NWDA2_NEWDAT_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_MSG1INT register.

//

//*****************************************************************************

#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits

#define CAN_MSG1INT_INTPND_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_MSG2INT register.

//

//*****************************************************************************

#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits

#define CAN_MSG2INT_INTPND_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_MSG1VAL register.

//

//*****************************************************************************

#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits

#define CAN_MSG1VAL_MSGVAL_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the CAN_O_MSG2VAL register.

//

//*****************************************************************************

#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits

#define CAN_MSG2VAL_MSGVAL_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FADDR register.

//

//*****************************************************************************

#define USB_FADDR_M             0x0000007F  // Function Address

#define USB_FADDR_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_POWER register.

//

//*****************************************************************************

#define USB_POWER_ISOUP         0x00000080  // Isochronous Update

#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect

#define USB_POWER_RESET         0x00000008  // RESET Signaling

#define USB_POWER_RESUME        0x00000004  // RESUME Signaling

#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode

#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXIS register.

//

//*****************************************************************************

#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt

#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt

#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt

#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt

#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt

#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt

#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt

#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXIS register.

//

//*****************************************************************************

#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt

#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt

#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt

#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt

#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt

#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt

#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXIE register.

//

//*****************************************************************************

#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable

#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable

#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable

#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable

#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable

#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable

#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable

#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt

                                            // Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXIE register.

//

//*****************************************************************************

#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable

#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable

#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable

#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable

#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable

#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable

#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_IS register.

//

//*****************************************************************************

#define USB_IS_VBUSERR          0x00000080  // VBUS Error (OTG only)

#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST (OTG only)

#define USB_IS_DISCON           0x00000020  // Session Disconnect (OTG only)

#define USB_IS_CONN             0x00000010  // Session Connect

#define USB_IS_SOF              0x00000008  // Start of Frame

#define USB_IS_BABBLE           0x00000004  // Babble Detected

#define USB_IS_RESET            0x00000004  // RESET Signaling Detected

#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected

#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_IE register.

//

//*****************************************************************************

#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt (OTG

                                            // only)

#define USB_IE_SESREQ           0x00000040  // Enable Session Request (OTG

                                            // only)

#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt

#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt

#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt

#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt

#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt

#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt

#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FRAME register.

//

//*****************************************************************************

#define USB_FRAME_M             0x000007FF  // Frame Number

#define USB_FRAME_S             0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_EPIDX register.

//

//*****************************************************************************

#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index

#define USB_EPIDX_EPIDX_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TEST register.

//

//*****************************************************************************

#define USB_TEST_FORCEH         0x00000080  // Force Host Mode

#define USB_TEST_FIFOACC        0x00000040  // FIFO Access

#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO0 register.

//

//*****************************************************************************

#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO0_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO1 register.

//

//*****************************************************************************

#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO1_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO2 register.

//

//*****************************************************************************

#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO2_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO3 register.

//

//*****************************************************************************

#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO3_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO4 register.

//

//*****************************************************************************

#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO4_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO5 register.

//

//*****************************************************************************

#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO5_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO6 register.

//

//*****************************************************************************

#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO6_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FIFO7 register.

//

//*****************************************************************************

#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data

#define USB_FIFO7_EPDATA_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_DEVCTL register.

//

//*****************************************************************************

#define USB_DEVCTL_DEV          0x00000080  // Device Mode (OTG only)

#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected

#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected

#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level (OTG only)

#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd

#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid

#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid

#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid

#define USB_DEVCTL_HOST         0x00000004  // Host Mode

#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request (OTG only)

#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End (OTG only)


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.

//

//*****************************************************************************

#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support

#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size

#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8

#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16

#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32

#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64

#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128

#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256

#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512

#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024

#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.

//

//*****************************************************************************

#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support

#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size

#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8

#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16

#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32

#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64

#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128

#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256

#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512

#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024

#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFIFOADD

// register.

//

//*****************************************************************************

#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address

#define USB_TXFIFOADD_ADDR_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFIFOADD

// register.

//

//*****************************************************************************

#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address

#define USB_RXFIFOADD_ADDR_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_CONTIM register.

//

//*****************************************************************************

#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait

#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID

#define USB_CONTIM_WTCON_S      4

#define USB_CONTIM_WTID_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_VPLEN register.

//

//*****************************************************************************

#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length

#define USB_VPLEN_VPLEN_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_FSEOF register.

//

//*****************************************************************************

#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap

#define USB_FSEOF_FSEOFG_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_LSEOF register.

//

//*****************************************************************************

#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap

#define USB_LSEOF_LSEOFG_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR0

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR0_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR0

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR0_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT0

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT0_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR1

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR1_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR1

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR1_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT1

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT1_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFUNCADDR1

// register.

//

//*****************************************************************************

#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address

#define USB_RXFUNCADDR1_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBADDR1

// register.

//

//*****************************************************************************

#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address

#define USB_RXHUBADDR1_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBPORT1

// register.

//

//*****************************************************************************

#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port

#define USB_RXHUBPORT1_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR2

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR2_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR2

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR2_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT2

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT2_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFUNCADDR2

// register.

//

//*****************************************************************************

#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address

#define USB_RXFUNCADDR2_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBADDR2

// register.

//

//*****************************************************************************

#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address

#define USB_RXHUBADDR2_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBPORT2

// register.

//

//*****************************************************************************

#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port

#define USB_RXHUBPORT2_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR3

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR3_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR3

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR3_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT3

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT3_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFUNCADDR3

// register.

//

//*****************************************************************************

#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address

#define USB_RXFUNCADDR3_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBADDR3

// register.

//

//*****************************************************************************

#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address

#define USB_RXHUBADDR3_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBPORT3

// register.

//

//*****************************************************************************

#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port

#define USB_RXHUBPORT3_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR4

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR4_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR4

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR4_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT4

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT4_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFUNCADDR4

// register.

//

//*****************************************************************************

#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address

#define USB_RXFUNCADDR4_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBADDR4

// register.

//

//*****************************************************************************

#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address

#define USB_RXHUBADDR4_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBPORT4

// register.

//

//*****************************************************************************

#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port

#define USB_RXHUBPORT4_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR5

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR5_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR5

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR5_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT5

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT5_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFUNCADDR5

// register.

//

//*****************************************************************************

#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address

#define USB_RXFUNCADDR5_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBADDR5

// register.

//

//*****************************************************************************

#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address

#define USB_RXHUBADDR5_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBPORT5

// register.

//

//*****************************************************************************

#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port

#define USB_RXHUBPORT5_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR6

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR6_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR6

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR6_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT6

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT6_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFUNCADDR6

// register.

//

//*****************************************************************************

#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address

#define USB_RXFUNCADDR6_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBADDR6

// register.

//

//*****************************************************************************

#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address

#define USB_RXHUBADDR6_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBPORT6

// register.

//

//*****************************************************************************

#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port

#define USB_RXHUBPORT6_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXFUNCADDR7

// register.

//

//*****************************************************************************

#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address

#define USB_TXFUNCADDR7_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBADDR7

// register.

//

//*****************************************************************************

#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address

#define USB_TXHUBADDR7_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXHUBPORT7

// register.

//

//*****************************************************************************

#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port

#define USB_TXHUBPORT7_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXFUNCADDR7

// register.

//

//*****************************************************************************

#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address

#define USB_RXFUNCADDR7_ADDR_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBADDR7

// register.

//

//*****************************************************************************

#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address

#define USB_RXHUBADDR7_ADDR_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXHUBPORT7

// register.

//

//*****************************************************************************

#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port

#define USB_RXHUBPORT7_PORT_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_CSRL0 register.

//

//*****************************************************************************

#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout

#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear

#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet

#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear

#define USB_CSRL0_REQPKT        0x00000020  // Request Packet

#define USB_CSRL0_STALL         0x00000020  // Send Stall

#define USB_CSRL0_SETEND        0x00000010  // Setup End

#define USB_CSRL0_ERROR         0x00000010  // Error

#define USB_CSRL0_DATAEND       0x00000008  // Data End

#define USB_CSRL0_SETUP         0x00000008  // Setup Packet

#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled

#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready

#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_CSRH0 register.

//

//*****************************************************************************

#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable

#define USB_CSRH0_DT            0x00000002  // Data Toggle

#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_COUNT0 register.

//

//*****************************************************************************

#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count

#define USB_COUNT0_COUNT_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TYPE0 register.

//

//*****************************************************************************

#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed

#define USB_TYPE0_SPEED_FULL    0x00000080  // Full

#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_NAKLMT register.

//

//*****************************************************************************

#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit

#define USB_NAKLMT_NAKLMT_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXMAXP1 register.

//

//*****************************************************************************

#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_TXMAXP1_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRL1 register.

//

//*****************************************************************************

#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout

#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle

#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled

#define USB_TXCSRL1_STALL       0x00000010  // Send STALL

#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet

#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO

#define USB_TXCSRL1_ERROR       0x00000004  // Error

#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun

#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty

#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRH1 register.

//

//*****************************************************************************

#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set

#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers

#define USB_TXCSRH1_MODE        0x00000020  // Mode

#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable

#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle

#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode

#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable

#define USB_TXCSRH1_DT          0x00000001  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXMAXP1 register.

//

//*****************************************************************************

#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_RXMAXP1_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRL1 register.

//

//*****************************************************************************

#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle

#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled

#define USB_RXCSRL1_STALL       0x00000020  // Send STALL

#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet

#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO

#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error

#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout

#define USB_RXCSRL1_OVER        0x00000004  // Overrun

#define USB_RXCSRL1_ERROR       0x00000004  // Error

#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full

#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRH1 register.

//

//*****************************************************************************

#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear

#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request

#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers

#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable

#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET

#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error

#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode

#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable

#define USB_RXCSRH1_DT          0x00000002  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.

//

//*****************************************************************************

#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count

#define USB_RXCOUNT1_COUNT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXTYPE1 register.

//

//*****************************************************************************

#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed

#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default

#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full

#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low

#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol

#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control

#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous

#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk

#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt

#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_TXTYPE1_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXINTERVAL1

// register.

//

//*****************************************************************************

#define USB_TXINTERVAL1_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_TXINTERVAL1_TXPOLL_M                                              \

                                0x000000FF  // TX Polling

#define USB_TXINTERVAL1_TXPOLL_S                                              \

                                0

#define USB_TXINTERVAL1_NAKLMT_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXTYPE1 register.

//

//*****************************************************************************

#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed

#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default

#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full

#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low

#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol

#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control

#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous

#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk

#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt

#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_RXTYPE1_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXINTERVAL1

// register.

//

//*****************************************************************************

#define USB_RXINTERVAL1_TXPOLL_M                                              \

                                0x000000FF  // RX Polling

#define USB_RXINTERVAL1_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_RXINTERVAL1_TXPOLL_S                                              \

                                0

#define USB_RXINTERVAL1_NAKLMT_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXMAXP2 register.

//

//*****************************************************************************

#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_TXMAXP2_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRL2 register.

//

//*****************************************************************************

#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout

#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle

#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled

#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet

#define USB_TXCSRL2_STALL       0x00000010  // Send STALL

#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO

#define USB_TXCSRL2_ERROR       0x00000004  // Error

#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun

#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty

#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRH2 register.

//

//*****************************************************************************

#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set

#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers

#define USB_TXCSRH2_MODE        0x00000020  // Mode

#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable

#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle

#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode

#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable

#define USB_TXCSRH2_DT          0x00000001  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXMAXP2 register.

//

//*****************************************************************************

#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_RXMAXP2_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRL2 register.

//

//*****************************************************************************

#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle

#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled

#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet

#define USB_RXCSRL2_STALL       0x00000020  // Send STALL

#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO

#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error

#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout

#define USB_RXCSRL2_ERROR       0x00000004  // Error

#define USB_RXCSRL2_OVER        0x00000004  // Overrun

#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full

#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRH2 register.

//

//*****************************************************************************

#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear

#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request

#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers

#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable

#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET

#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error

#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode

#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable

#define USB_RXCSRH2_DT          0x00000002  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.

//

//*****************************************************************************

#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count

#define USB_RXCOUNT2_COUNT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXTYPE2 register.

//

//*****************************************************************************

#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed

#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default

#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full

#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low

#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol

#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control

#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous

#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk

#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt

#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_TXTYPE2_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXINTERVAL2

// register.

//

//*****************************************************************************

#define USB_TXINTERVAL2_TXPOLL_M                                              \

                                0x000000FF  // TX Polling

#define USB_TXINTERVAL2_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_TXINTERVAL2_NAKLMT_S                                              \

                                0

#define USB_TXINTERVAL2_TXPOLL_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXTYPE2 register.

//

//*****************************************************************************

#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed

#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default

#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full

#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low

#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol

#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control

#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous

#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk

#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt

#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_RXTYPE2_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXINTERVAL2

// register.

//

//*****************************************************************************

#define USB_RXINTERVAL2_TXPOLL_M                                              \

                                0x000000FF  // RX Polling

#define USB_RXINTERVAL2_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_RXINTERVAL2_TXPOLL_S                                              \

                                0

#define USB_RXINTERVAL2_NAKLMT_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXMAXP3 register.

//

//*****************************************************************************

#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_TXMAXP3_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRL3 register.

//

//*****************************************************************************

#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout

#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle

#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled

#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet

#define USB_TXCSRL3_STALL       0x00000010  // Send STALL

#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO

#define USB_TXCSRL3_ERROR       0x00000004  // Error

#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun

#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty

#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRH3 register.

//

//*****************************************************************************

#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set

#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers

#define USB_TXCSRH3_MODE        0x00000020  // Mode

#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable

#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle

#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode

#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable

#define USB_TXCSRH3_DT          0x00000001  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXMAXP3 register.

//

//*****************************************************************************

#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_RXMAXP3_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRL3 register.

//

//*****************************************************************************

#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle

#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled

#define USB_RXCSRL3_STALL       0x00000020  // Send STALL

#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet

#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO

#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error

#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout

#define USB_RXCSRL3_ERROR       0x00000004  // Error

#define USB_RXCSRL3_OVER        0x00000004  // Overrun

#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full

#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRH3 register.

//

//*****************************************************************************

#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear

#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request

#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers

#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable

#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET

#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error

#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode

#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable

#define USB_RXCSRH3_DT          0x00000002  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.

//

//*****************************************************************************

#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count

#define USB_RXCOUNT3_COUNT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXTYPE3 register.

//

//*****************************************************************************

#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed

#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default

#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full

#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low

#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol

#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control

#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous

#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk

#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt

#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_TXTYPE3_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXINTERVAL3

// register.

//

//*****************************************************************************

#define USB_TXINTERVAL3_TXPOLL_M                                              \

                                0x000000FF  // TX Polling

#define USB_TXINTERVAL3_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_TXINTERVAL3_TXPOLL_S                                              \

                                0

#define USB_TXINTERVAL3_NAKLMT_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXTYPE3 register.

//

//*****************************************************************************

#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed

#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default

#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full

#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low

#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol

#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control

#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous

#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk

#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt

#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_RXTYPE3_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXINTERVAL3

// register.

//

//*****************************************************************************

#define USB_RXINTERVAL3_TXPOLL_M                                              \

                                0x000000FF  // RX Polling

#define USB_RXINTERVAL3_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_RXINTERVAL3_TXPOLL_S                                              \

                                0

#define USB_RXINTERVAL3_NAKLMT_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXMAXP4 register.

//

//*****************************************************************************

#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_TXMAXP4_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRL4 register.

//

//*****************************************************************************

#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout

#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle

#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled

#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet

#define USB_TXCSRL4_STALL       0x00000010  // Send STALL

#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO

#define USB_TXCSRL4_ERROR       0x00000004  // Error

#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun

#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty

#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRH4 register.

//

//*****************************************************************************

#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set

#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers

#define USB_TXCSRH4_MODE        0x00000020  // Mode

#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable

#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle

#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode

#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable

#define USB_TXCSRH4_DT          0x00000001  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXMAXP4 register.

//

//*****************************************************************************

#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_RXMAXP4_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRL4 register.

//

//*****************************************************************************

#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle

#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled

#define USB_RXCSRL4_STALL       0x00000020  // Send STALL

#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet

#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO

#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout

#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error

#define USB_RXCSRL4_OVER        0x00000004  // Overrun

#define USB_RXCSRL4_ERROR       0x00000004  // Error

#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full

#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRH4 register.

//

//*****************************************************************************

#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear

#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request

#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers

#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable

#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET

#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error

#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode

#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable

#define USB_RXCSRH4_DT          0x00000002  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.

//

//*****************************************************************************

#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count

#define USB_RXCOUNT4_COUNT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXTYPE4 register.

//

//*****************************************************************************

#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed

#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default

#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full

#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low

#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol

#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control

#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous

#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk

#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt

#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_TXTYPE4_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXINTERVAL4

// register.

//

//*****************************************************************************

#define USB_TXINTERVAL4_TXPOLL_M                                              \

                                0x000000FF  // TX Polling

#define USB_TXINTERVAL4_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_TXINTERVAL4_NAKLMT_S                                              \

                                0

#define USB_TXINTERVAL4_TXPOLL_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXTYPE4 register.

//

//*****************************************************************************

#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed

#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default

#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full

#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low

#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol

#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control

#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous

#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk

#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt

#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_RXTYPE4_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXINTERVAL4

// register.

//

//*****************************************************************************

#define USB_RXINTERVAL4_TXPOLL_M                                              \

                                0x000000FF  // RX Polling

#define USB_RXINTERVAL4_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_RXINTERVAL4_NAKLMT_S                                              \

                                0

#define USB_RXINTERVAL4_TXPOLL_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXMAXP5 register.

//

//*****************************************************************************

#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_TXMAXP5_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRL5 register.

//

//*****************************************************************************

#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout

#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle

#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled

#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet

#define USB_TXCSRL5_STALL       0x00000010  // Send STALL

#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO

#define USB_TXCSRL5_ERROR       0x00000004  // Error

#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun

#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty

#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRH5 register.

//

//*****************************************************************************

#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set

#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers

#define USB_TXCSRH5_MODE        0x00000020  // Mode

#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable

#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle

#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode

#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable

#define USB_TXCSRH5_DT          0x00000001  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXMAXP5 register.

//

//*****************************************************************************

#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_RXMAXP5_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRL5 register.

//

//*****************************************************************************

#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle

#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled

#define USB_RXCSRL5_STALL       0x00000020  // Send STALL

#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet

#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO

#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout

#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error

#define USB_RXCSRL5_ERROR       0x00000004  // Error

#define USB_RXCSRL5_OVER        0x00000004  // Overrun

#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full

#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRH5 register.

//

//*****************************************************************************

#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear

#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request

#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers

#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable

#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET

#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error

#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode

#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable

#define USB_RXCSRH5_DT          0x00000002  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.

//

//*****************************************************************************

#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count

#define USB_RXCOUNT5_COUNT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXTYPE5 register.

//

//*****************************************************************************

#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed

#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default

#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full

#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low

#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol

#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control

#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous

#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk

#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt

#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_TXTYPE5_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXINTERVAL5

// register.

//

//*****************************************************************************

#define USB_TXINTERVAL5_TXPOLL_M                                              \

                                0x000000FF  // TX Polling

#define USB_TXINTERVAL5_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_TXINTERVAL5_NAKLMT_S                                              \

                                0

#define USB_TXINTERVAL5_TXPOLL_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXTYPE5 register.

//

//*****************************************************************************

#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed

#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default

#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full

#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low

#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol

#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control

#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous

#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk

#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt

#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_RXTYPE5_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXINTERVAL5

// register.

//

//*****************************************************************************

#define USB_RXINTERVAL5_TXPOLL_M                                              \

                                0x000000FF  // RX Polling

#define USB_RXINTERVAL5_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_RXINTERVAL5_TXPOLL_S                                              \

                                0

#define USB_RXINTERVAL5_NAKLMT_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXMAXP6 register.

//

//*****************************************************************************

#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_TXMAXP6_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRL6 register.

//

//*****************************************************************************

#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout

#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle

#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled

#define USB_TXCSRL6_STALL       0x00000010  // Send STALL

#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet

#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO

#define USB_TXCSRL6_ERROR       0x00000004  // Error

#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun

#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty

#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRH6 register.

//

//*****************************************************************************

#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set

#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers

#define USB_TXCSRH6_MODE        0x00000020  // Mode

#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable

#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle

#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode

#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable

#define USB_TXCSRH6_DT          0x00000001  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXMAXP6 register.

//

//*****************************************************************************

#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_RXMAXP6_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRL6 register.

//

//*****************************************************************************

#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle

#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled

#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet

#define USB_RXCSRL6_STALL       0x00000020  // Send STALL

#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO

#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout

#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error

#define USB_RXCSRL6_ERROR       0x00000004  // Error

#define USB_RXCSRL6_OVER        0x00000004  // Overrun

#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full

#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRH6 register.

//

//*****************************************************************************

#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear

#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request

#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers

#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable

#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET

#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error

#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode

#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable

#define USB_RXCSRH6_DT          0x00000002  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.

//

//*****************************************************************************

#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count

#define USB_RXCOUNT6_COUNT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXTYPE6 register.

//

//*****************************************************************************

#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed

#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default

#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full

#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low

#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol

#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control

#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous

#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk

#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt

#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_TXTYPE6_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXINTERVAL6

// register.

//

//*****************************************************************************

#define USB_TXINTERVAL6_TXPOLL_M                                              \

                                0x000000FF  // TX Polling

#define USB_TXINTERVAL6_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_TXINTERVAL6_TXPOLL_S                                              \

                                0

#define USB_TXINTERVAL6_NAKLMT_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXTYPE6 register.

//

//*****************************************************************************

#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed

#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default

#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full

#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low

#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol

#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control

#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous

#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk

#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt

#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_RXTYPE6_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXINTERVAL6

// register.

//

//*****************************************************************************

#define USB_RXINTERVAL6_TXPOLL_M                                              \

                                0x000000FF  // RX Polling

#define USB_RXINTERVAL6_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_RXINTERVAL6_NAKLMT_S                                              \

                                0

#define USB_RXINTERVAL6_TXPOLL_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXMAXP7 register.

//

//*****************************************************************************

#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_TXMAXP7_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRL7 register.

//

//*****************************************************************************

#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout

#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle

#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled

#define USB_TXCSRL7_STALL       0x00000010  // Send STALL

#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet

#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO

#define USB_TXCSRL7_ERROR       0x00000004  // Error

#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun

#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty

#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXCSRH7 register.

//

//*****************************************************************************

#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set

#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers

#define USB_TXCSRH7_MODE        0x00000020  // Mode

#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable

#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle

#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode

#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable

#define USB_TXCSRH7_DT          0x00000001  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXMAXP7 register.

//

//*****************************************************************************

#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload

#define USB_RXMAXP7_MAXLOAD_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRL7 register.

//

//*****************************************************************************

#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle

#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled

#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet

#define USB_RXCSRL7_STALL       0x00000020  // Send STALL

#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO

#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error

#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout

#define USB_RXCSRL7_ERROR       0x00000004  // Error

#define USB_RXCSRL7_OVER        0x00000004  // Overrun

#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full

#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCSRH7 register.

//

//*****************************************************************************

#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear

#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers

#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request

#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable

#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error

#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET

#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode

#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable

#define USB_RXCSRH7_DT          0x00000002  // Data Toggle


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.

//

//*****************************************************************************

#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count

#define USB_RXCOUNT7_COUNT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXTYPE7 register.

//

//*****************************************************************************

#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed

#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default

#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full

#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low

#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol

#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control

#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous

#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk

#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt

#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_TXTYPE7_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXINTERVAL7

// register.

//

//*****************************************************************************

#define USB_TXINTERVAL7_TXPOLL_M                                              \

                                0x000000FF  // TX Polling

#define USB_TXINTERVAL7_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_TXINTERVAL7_NAKLMT_S                                              \

                                0

#define USB_TXINTERVAL7_TXPOLL_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXTYPE7 register.

//

//*****************************************************************************

#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed

#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default

#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full

#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low

#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol

#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control

#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous

#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk

#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt

#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number

#define USB_RXTYPE7_TEP_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXINTERVAL7

// register.

//

//*****************************************************************************

#define USB_RXINTERVAL7_TXPOLL_M                                              \

                                0x000000FF  // RX Polling

#define USB_RXINTERVAL7_NAKLMT_M                                              \

                                0x000000FF  // NAK Limit

#define USB_RXINTERVAL7_NAKLMT_S                                              \

                                0

#define USB_RXINTERVAL7_TXPOLL_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1

// register.

//

//*****************************************************************************

#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count

#define USB_RQPKTCOUNT1_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2

// register.

//

//*****************************************************************************

#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count

#define USB_RQPKTCOUNT2_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3

// register.

//

//*****************************************************************************

#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count

#define USB_RQPKTCOUNT3_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4

// register.

//

//*****************************************************************************

#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count

#define USB_RQPKTCOUNT4_COUNT_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5

// register.

//

//*****************************************************************************

#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count

#define USB_RQPKTCOUNT5_COUNT_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6

// register.

//

//*****************************************************************************

#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count

#define USB_RQPKTCOUNT6_COUNT_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7

// register.

//

//*****************************************************************************

#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count

#define USB_RQPKTCOUNT7_COUNT_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS

// register.

//

//*****************************************************************************

#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer

                                            // Disable

#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer

                                            // Disable

#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer

                                            // Disable

#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer

                                            // Disable

#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer

                                            // Disable

#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer

                                            // Disable

#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer

                                            // Disable


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS

// register.

//

//*****************************************************************************

#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer

                                            // Disable

#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer

                                            // Disable

#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer

                                            // Disable

#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer

                                            // Disable

#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer

                                            // Disable

#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer

                                            // Disable

#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer

                                            // Disable


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_EPC register.

//

//*****************************************************************************

#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action

#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged

#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate

#define USB_EPC_PFLTACT_LOW     0x00000200  // Low

#define USB_EPC_PFLTACT_HIGH    0x00000300  // High

#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable

#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense

#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable

#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable

#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable

                                            // Configuration

#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low

#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High

#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low

                                            // (OTG only)

#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High

                                            // (OTG only)


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_EPCRIS register.

//

//*****************************************************************************

#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_EPCIM register.

//

//*****************************************************************************

#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_EPCISC register.

//

//*****************************************************************************

#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status

                                            // and Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_DRRIS register.

//

//*****************************************************************************

#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_DRIM register.

//

//*****************************************************************************

#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_DRISC register.

//

//*****************************************************************************

#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and

                                            // Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_GPCS register.

//

//*****************************************************************************

#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode

#define USB_GPCS_DEVMOD         0x00000001  // Device Mode


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_VDC register.

//

//*****************************************************************************

#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_VDCRIS register.

//

//*****************************************************************************

#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_VDCIM register.

//

//*****************************************************************************

#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_VDCISC register.

//

//*****************************************************************************

#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and

                                            // Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_IDVRIS register.

//

//*****************************************************************************

#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt

                                            // Status


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_IDVIM register.

//

//*****************************************************************************

#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_IDVISC register.

//

//*****************************************************************************

#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status

                                            // and Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_DMASEL register.

//

//*****************************************************************************

#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select

#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select

#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select

#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select

#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select

#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select

#define USB_DMASEL_DMACTX_S     20

#define USB_DMASEL_DMACRX_S     16

#define USB_DMASEL_DMABTX_S     12

#define USB_DMASEL_DMABRX_S     8

#define USB_DMASEL_DMAATX_S     4

#define USB_DMASEL_DMAARX_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the USB_O_PP register.

//

//*****************************************************************************

#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count

#define USB_PP_USB_M            0x000000C0  // USB Capability

#define USB_PP_USB_DEVICE       0x00000040  // DEVICE

#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST

#define USB_PP_USB_OTG          0x000000C0  // OTG

#define USB_PP_PHY              0x00000010  // PHY Present

#define USB_PP_TYPE_M           0x0000000F  // Controller Type

#define USB_PP_TYPE_0           0x00000000  // The first-generation USB

                                            // controller

#define USB_PP_ECNT_S           8


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EESIZE register.

//

//*****************************************************************************

#define EEPROM_EESIZE_BLKCNT_M  0x07FF0000  // Number of 16-Word Blocks

#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF  // Number of 32-Bit Words

#define EEPROM_EESIZE_BLKCNT_S  16

#define EEPROM_EESIZE_WORDCNT_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEBLOCK register.

//

//*****************************************************************************

#define EEPROM_EEBLOCK_BLOCK_M  0x0000FFFF  // Current Block

#define EEPROM_EEBLOCK_BLOCK_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEOFFSET

// register.

//

//*****************************************************************************

#define EEPROM_EEOFFSET_OFFSET_M                                              \

                                0x0000000F  // Current Address Offset

#define EEPROM_EEOFFSET_OFFSET_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EERDWR register.

//

//*****************************************************************************

#define EEPROM_EERDWR_VALUE_M   0xFFFFFFFF  // EEPROM Read or Write Data

#define EEPROM_EERDWR_VALUE_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EERDWRINC

// register.

//

//*****************************************************************************

#define EEPROM_EERDWRINC_VALUE_M                                              \

                                0xFFFFFFFF  // EEPROM Read or Write Data with

                                            // Increment

#define EEPROM_EERDWRINC_VALUE_S                                              \

                                0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEDONE register.

//

//*****************************************************************************

#define EEPROM_EEDONE_WRBUSY    0x00000020  // Write Busy

#define EEPROM_EEDONE_NOPERM    0x00000010  // Write Without Permission

#define EEPROM_EEDONE_WKCOPY    0x00000008  // Working on a Copy

#define EEPROM_EEDONE_WKERASE   0x00000004  // Working on an Erase

#define EEPROM_EEDONE_WORKING   0x00000001  // EEPROM Working


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EESUPP register.

//

//*****************************************************************************

#define EEPROM_EESUPP_PRETRY    0x00000008  // Programming Must Be Retried

#define EEPROM_EESUPP_ERETRY    0x00000004  // Erase Must Be Retried


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEUNLOCK

// register.

//

//*****************************************************************************

#define EEPROM_EEUNLOCK_UNLOCK_M                                              \

                                0xFFFFFFFF  // EEPROM Unlock


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEPROT register.

//

//*****************************************************************************

#define EEPROM_EEPROT_ACC       0x00000008  // Access Control

#define EEPROM_EEPROT_PROT_M    0x00000007  // Protection Control

#define EEPROM_EEPROT_PROT_RWNPW                                              \

                                0x00000000  // This setting is the default. If

                                            // there is no password, the block

                                            // is not protected and is readable

                                            // and writable

#define EEPROM_EEPROT_PROT_RWPW 0x00000001  // If there is a password, the

                                            // block is readable or writable

                                            // only when unlocked

#define EEPROM_EEPROT_PROT_RONPW                                              \

                                0x00000002  // If there is no password, the

                                            // block is readable, not writable


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEPASS0 register.

//

//*****************************************************************************

#define EEPROM_EEPASS0_PASS_M   0xFFFFFFFF  // Password

#define EEPROM_EEPASS0_PASS_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEPASS1 register.

//

//*****************************************************************************

#define EEPROM_EEPASS1_PASS_M   0xFFFFFFFF  // Password

#define EEPROM_EEPASS1_PASS_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEPASS2 register.

//

//*****************************************************************************

#define EEPROM_EEPASS2_PASS_M   0xFFFFFFFF  // Password

#define EEPROM_EEPASS2_PASS_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEINT register.

//

//*****************************************************************************

#define EEPROM_EEINT_INT        0x00000001  // Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEHIDE register.

//

//*****************************************************************************

#define EEPROM_EEHIDE_HN_M      0xFFFFFFFE  // Hide Block


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_EEDBGME register.

//

//*****************************************************************************

#define EEPROM_EEDBGME_KEY_M    0xFFFF0000  // Erase Key

#define EEPROM_EEDBGME_ME       0x00000001  // Mass Erase

#define EEPROM_EEDBGME_KEY_S    16


//*****************************************************************************

//

// The following are defines for the bit fields in the EEPROM_PP register.

//

//*****************************************************************************

#define EEPROM_PP_SIZE_M        0x0000001F  // EEPROM Size

#define EEPROM_PP_SIZE_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSEXC_RIS register.

//

//*****************************************************************************

#define SYSEXC_RIS_FPIXCRIS     0x00000020  // Floating-Point Inexact Exception

                                            // Raw Interrupt Status

#define SYSEXC_RIS_FPOFCRIS     0x00000010  // Floating-Point Overflow

                                            // Exception Raw Interrupt Status

#define SYSEXC_RIS_FPUFCRIS     0x00000008  // Floating-Point Underflow

                                            // Exception Raw Interrupt Status

#define SYSEXC_RIS_FPIOCRIS     0x00000004  // Floating-Point Invalid Operation

                                            // Raw Interrupt Status

#define SYSEXC_RIS_FPDZCRIS     0x00000002  // Floating-Point Divide By 0

                                            // Exception Raw Interrupt Status

#define SYSEXC_RIS_FPIDCRIS     0x00000001  // Floating-Point Input Denormal

                                            // Exception Raw Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSEXC_IM register.

//

//*****************************************************************************

#define SYSEXC_IM_FPIXCIM       0x00000020  // Floating-Point Inexact Exception

                                            // Interrupt Mask

#define SYSEXC_IM_FPOFCIM       0x00000010  // Floating-Point Overflow

                                            // Exception Interrupt Mask

#define SYSEXC_IM_FPUFCIM       0x00000008  // Floating-Point Underflow

                                            // Exception Interrupt Mask

#define SYSEXC_IM_FPIOCIM       0x00000004  // Floating-Point Invalid Operation

                                            // Interrupt Mask

#define SYSEXC_IM_FPDZCIM       0x00000002  // Floating-Point Divide By 0

                                            // Exception Interrupt Mask

#define SYSEXC_IM_FPIDCIM       0x00000001  // Floating-Point Input Denormal

                                            // Exception Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSEXC_MIS register.

//

//*****************************************************************************

#define SYSEXC_MIS_FPIXCMIS     0x00000020  // Floating-Point Inexact Exception

                                            // Masked Interrupt Status

#define SYSEXC_MIS_FPOFCMIS     0x00000010  // Floating-Point Overflow

                                            // Exception Masked Interrupt

                                            // Status

#define SYSEXC_MIS_FPUFCMIS     0x00000008  // Floating-Point Underflow

                                            // Exception Masked Interrupt

                                            // Status

#define SYSEXC_MIS_FPIOCMIS     0x00000004  // Floating-Point Invalid Operation

                                            // Masked Interrupt Status

#define SYSEXC_MIS_FPDZCMIS     0x00000002  // Floating-Point Divide By 0

                                            // Exception Masked Interrupt

                                            // Status

#define SYSEXC_MIS_FPIDCMIS     0x00000001  // Floating-Point Input Denormal

                                            // Exception Masked Interrupt

                                            // Status


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSEXC_IC register.

//

//*****************************************************************************

#define SYSEXC_IC_FPIXCIC       0x00000020  // Floating-Point Inexact Exception

                                            // Interrupt Clear

#define SYSEXC_IC_FPOFCIC       0x00000010  // Floating-Point Overflow

                                            // Exception Interrupt Clear

#define SYSEXC_IC_FPUFCIC       0x00000008  // Floating-Point Underflow

                                            // Exception Interrupt Clear

#define SYSEXC_IC_FPIOCIC       0x00000004  // Floating-Point Invalid Operation

                                            // Interrupt Clear

#define SYSEXC_IC_FPDZCIC       0x00000002  // Floating-Point Divide By 0

                                            // Exception Interrupt Clear

#define SYSEXC_IC_FPIDCIC       0x00000001  // Floating-Point Input Denormal

                                            // Exception Interrupt Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FMA register.

//

//*****************************************************************************

#define FLASH_FMA_OFFSET_M      0x0001FFFF  // Address Offset

#define FLASH_FMA_OFFSET_S      0


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FMD register.

//

//*****************************************************************************

#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value

#define FLASH_FMD_DATA_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FMC register.

//

//*****************************************************************************

#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key

#define FLASH_FMC_COMT          0x00000008  // Commit Register Value

#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory

#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory

#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FCRIS register.

//

//*****************************************************************************

#define FLASH_FCRIS_PROGRIS     0x00002000  // Program Verify Error Raw

                                            // Interrupt Status

#define FLASH_FCRIS_ERRIS       0x00000800  // Erase Verify Error Raw Interrupt

                                            // Status

#define FLASH_FCRIS_INVDRIS     0x00000400  // Invalid Data Raw Interrupt

                                            // Status

#define FLASH_FCRIS_VOLTRIS     0x00000200  // Pump Voltage Raw Interrupt

                                            // Status

#define FLASH_FCRIS_ERIS        0x00000004  // EEPROM Raw Interrupt Status

#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status

#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FCIM register.

//

//*****************************************************************************

#define FLASH_FCIM_PROGMASK     0x00002000  // PROGVER Interrupt Mask

#define FLASH_FCIM_ERMASK       0x00000800  // ERVER Interrupt Mask

#define FLASH_FCIM_INVDMASK     0x00000400  // Invalid Data Interrupt Mask

#define FLASH_FCIM_VOLTMASK     0x00000200  // VOLT Interrupt Mask

#define FLASH_FCIM_EMASK        0x00000004  // EEPROM Interrupt Mask

#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask

#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FCMISC register.

//

//*****************************************************************************

#define FLASH_FCMISC_PROGMISC   0x00002000  // PROGVER Masked Interrupt Status

                                            // and Clear

#define FLASH_FCMISC_ERMISC     0x00000800  // ERVER Masked Interrupt Status

                                            // and Clear

#define FLASH_FCMISC_INVDMISC   0x00000400  // Invalid Data Masked Interrupt

                                            // Status and Clear

#define FLASH_FCMISC_VOLTMISC   0x00000200  // VOLT Masked Interrupt Status and

                                            // Clear

#define FLASH_FCMISC_EMISC      0x00000004  // EEPROM Masked Interrupt Status

                                            // and Clear

#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt

                                            // Status and Clear

#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status

                                            // and Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FMC2 register.

//

//*****************************************************************************

#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FWBVAL register.

//

//*****************************************************************************

#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FWBN register.

//

//*****************************************************************************

#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_FSIZE register.

//

//*****************************************************************************

#define FLASH_FSIZE_SIZE_M      0x0000FFFF  // Flash Size

#define FLASH_FSIZE_SIZE_128KB  0x0000003F  // 128 KB of Flash


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_SSIZE register.

//

//*****************************************************************************

#define FLASH_SSIZE_SIZE_M      0x0000FFFF  // SRAM Size

#define FLASH_SSIZE_SIZE_32KB   0x0000007F  // 32 KB of SRAM


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_ROMSWMAP register.

//

//*****************************************************************************

#define FLASH_ROMSWMAP_SAFERTOS 0x00000001  // SafeRTOS Present


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_RMCTL register.

//

//*****************************************************************************

#define FLASH_RMCTL_BA          0x00000001  // Boot Alias


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_BOOTCFG register.

//

//*****************************************************************************

#define FLASH_BOOTCFG_NW        0x80000000  // Not Written

#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port

#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A

#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B

#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C

#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D

#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E

#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F

#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G

#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H

#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin

#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0

#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1

#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2

#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3

#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4

#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5

#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6

#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7

#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity

#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable

#define FLASH_BOOTCFG_KEY       0x00000010  // KEY Select

#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1

#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_USERREG0 register.

//

//*****************************************************************************

#define FLASH_USERREG0_DATA_M   0xFFFFFFFF  // User Data

#define FLASH_USERREG0_DATA_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_USERREG1 register.

//

//*****************************************************************************

#define FLASH_USERREG1_DATA_M   0xFFFFFFFF  // User Data

#define FLASH_USERREG1_DATA_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_USERREG2 register.

//

//*****************************************************************************

#define FLASH_USERREG2_DATA_M   0xFFFFFFFF  // User Data

#define FLASH_USERREG2_DATA_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the FLASH_USERREG3 register.

//

//*****************************************************************************

#define FLASH_USERREG3_DATA_M   0xFFFFFFFF  // User Data

#define FLASH_USERREG3_DATA_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DID0 register.

//

//*****************************************************************************

#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version

#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0

                                            // register format.

#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class

#define SYSCTL_DID0_CLASS_TM4C123                                             \

                                0x00050000  // Tiva TM4C123x and TM4E123x

                                            // microcontrollers

#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision

#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)

#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer

                                            // revision)

#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer

                                            // revision)

#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision

#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major

                                            // revision update

#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change

#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DID1 register.

//

//*****************************************************************************

#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version

#define SYSCTL_DID1_VER_1       0x10000000  // fury_ib

#define SYSCTL_DID1_FAM_M       0x0F000000  // Family

#define SYSCTL_DID1_FAM_TIVA    0x00000000  // Tiva family of microcontollers

#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number

#define SYSCTL_DID1_PRTNO_TM4C123FE6PM                                        \

                                0x00B00000  // TM4C123FE6PM

#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count

#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin LQFP package

#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64-pin LQFP package

#define SYSCTL_DID1_PINCNT_144  0x00008000  // 144-pin LQFP package

#define SYSCTL_DID1_PINCNT_157  0x0000A000  // 157-pin BGA package

#define SYSCTL_DID1_PINCNT_128  0x0000C000  // 128-pin TQFP package

#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range

#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range

#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range

#define SYSCTL_DID1_TEMP_IE     0x00000060  // Available in both industrial

                                            // temperature range (-40C to 85C)

                                            // and extended temperature range

                                            // (-40C to 105C) devices. See

#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type

#define SYSCTL_DID1_PKG_QFP     0x00000008  // QFP package

#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package

#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance

#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status

#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)

#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)

#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC0 register.

//

//*****************************************************************************

#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size

#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_6KB   0x00170000  // 6 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_12KB  0x002F0000  // 12 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_16KB  0x003F0000  // 16 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_20KB  0x004F0000  // 20 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_24KB  0x005F0000  // 24 KB of SRAM

#define SYSCTL_DC0_SRAMSZ_32KB  0x007F0000  // 32 KB of SRAM

#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size

#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of Flash

#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of Flash

#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of Flash

#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of Flash

#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of Flash

#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of Flash

#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F  // 192 KB of Flash

#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC1 register.

//

//*****************************************************************************

#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present

#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present

#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present

#define SYSCTL_DC1_PWM1         0x00200000  // PWM Module 1 Present

#define SYSCTL_DC1_PWM0         0x00100000  // PWM Module 0 Present

#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present

#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present

#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider

#define SYSCTL_DC1_MINSYSDIV_80 0x00001000  // Specifies an 80-MHz CPU clock

                                            // with a PLL divider of 2.5

#define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Specifies a 66-MHz CPU clock

                                            // with a PLL divider of 3

#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock

                                            // with a PLL divider of 4

#define SYSCTL_DC1_MINSYSDIV_40 0x00004000  // Specifies a 40-MHz CPU clock

                                            // with a PLL divider of 5

#define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a

                                            // PLL divider of 8

#define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a

                                            // PLL divider of 10

#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed

#define SYSCTL_DC1_ADC1SPD_125K 0x00000000  // 125K samples/second

#define SYSCTL_DC1_ADC1SPD_250K 0x00000400  // 250K samples/second

#define SYSCTL_DC1_ADC1SPD_500K 0x00000800  // 500K samples/second

#define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second

#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed

#define SYSCTL_DC1_ADC0SPD_125K 0x00000000  // 125K samples/second

#define SYSCTL_DC1_ADC0SPD_250K 0x00000100  // 250K samples/second

#define SYSCTL_DC1_ADC0SPD_500K 0x00000200  // 500K samples/second

#define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second

#define SYSCTL_DC1_MPU          0x00000080  // MPU Present

#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present

#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present

#define SYSCTL_DC1_PLL          0x00000010  // PLL Present

#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present

#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present

#define SYSCTL_DC1_SWD          0x00000002  // SWD Present

#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC2 register.

//

//*****************************************************************************

#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present

#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present

#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present

#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present

#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present

#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present

#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present

#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present

#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present

#define SYSCTL_DC2_I2C1HS       0x00008000  // I2C Module 1 Speed

#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present

#define SYSCTL_DC2_I2C0HS       0x00002000  // I2C Module 0 Speed

#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present

#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present

#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present

#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present

#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present

#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present

#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present

#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC3 register.

//

//*****************************************************************************

#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available

#define SYSCTL_DC3_CCP5         0x20000000  // T2CCP1 Pin Present

#define SYSCTL_DC3_CCP4         0x10000000  // T2CCP0 Pin Present

#define SYSCTL_DC3_CCP3         0x08000000  // T1CCP1 Pin Present

#define SYSCTL_DC3_CCP2         0x04000000  // T1CCP0 Pin Present

#define SYSCTL_DC3_CCP1         0x02000000  // T0CCP1 Pin Present

#define SYSCTL_DC3_CCP0         0x01000000  // T0CCP0 Pin Present

#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present

#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present

#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present

#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present

#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present

#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present

#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present

#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present

#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present

#define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present

#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present

#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present

#define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present

#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present

#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present

#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present

#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present

#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present

#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present

#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present

#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present

#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present

#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present

#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC4 register.

//

//*****************************************************************************

#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present

#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present

#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable

#define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate

#define SYSCTL_DC4_CCP7         0x00008000  // T3CCP1 Pin Present

#define SYSCTL_DC4_CCP6         0x00004000  // T3CCP0 Pin Present

#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present

#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present

#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present

#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present

#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present

#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present

#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present

#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present

#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present

#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present

#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC5 register.

//

//*****************************************************************************

#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present

#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present

#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present

#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present

#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active

#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active

#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present

#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present

#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present

#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present

#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present

#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present

#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present

#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC6 register.

//

//*****************************************************************************

#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present

#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present

#define SYSCTL_DC6_USB0_DEV     0x00000001  // USB0 is Device Only

#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is Device or Host

#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC7 register.

//

//*****************************************************************************

#define SYSCTL_DC7_DMACH30      0x40000000  // DMA Channel 30

#define SYSCTL_DC7_DMACH29      0x20000000  // DMA Channel 29

#define SYSCTL_DC7_DMACH28      0x10000000  // DMA Channel 28

#define SYSCTL_DC7_DMACH27      0x08000000  // DMA Channel 27

#define SYSCTL_DC7_DMACH26      0x04000000  // DMA Channel 26

#define SYSCTL_DC7_DMACH25      0x02000000  // DMA Channel 25

#define SYSCTL_DC7_DMACH24      0x01000000  // DMA Channel 24

#define SYSCTL_DC7_DMACH23      0x00800000  // DMA Channel 23

#define SYSCTL_DC7_DMACH22      0x00400000  // DMA Channel 22

#define SYSCTL_DC7_DMACH21      0x00200000  // DMA Channel 21

#define SYSCTL_DC7_DMACH20      0x00100000  // DMA Channel 20

#define SYSCTL_DC7_DMACH19      0x00080000  // DMA Channel 19

#define SYSCTL_DC7_DMACH18      0x00040000  // DMA Channel 18

#define SYSCTL_DC7_DMACH17      0x00020000  // DMA Channel 17

#define SYSCTL_DC7_DMACH16      0x00010000  // DMA Channel 16

#define SYSCTL_DC7_DMACH15      0x00008000  // DMA Channel 15

#define SYSCTL_DC7_DMACH14      0x00004000  // DMA Channel 14

#define SYSCTL_DC7_DMACH13      0x00002000  // DMA Channel 13

#define SYSCTL_DC7_DMACH12      0x00001000  // DMA Channel 12

#define SYSCTL_DC7_DMACH11      0x00000800  // DMA Channel 11

#define SYSCTL_DC7_DMACH10      0x00000400  // DMA Channel 10

#define SYSCTL_DC7_DMACH9       0x00000200  // DMA Channel 9

#define SYSCTL_DC7_DMACH8       0x00000100  // DMA Channel 8

#define SYSCTL_DC7_DMACH7       0x00000080  // DMA Channel 7

#define SYSCTL_DC7_DMACH6       0x00000040  // DMA Channel 6

#define SYSCTL_DC7_DMACH5       0x00000020  // DMA Channel 5

#define SYSCTL_DC7_DMACH4       0x00000010  // DMA Channel 4

#define SYSCTL_DC7_DMACH3       0x00000008  // DMA Channel 3

#define SYSCTL_DC7_DMACH2       0x00000004  // DMA Channel 2

#define SYSCTL_DC7_DMACH1       0x00000002  // DMA Channel 1

#define SYSCTL_DC7_DMACH0       0x00000001  // DMA Channel 0


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC8 register.

//

//*****************************************************************************

#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present

#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present

#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present

#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present

#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present

#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present

#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present

#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present

#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present

#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present

#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present

#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present

#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present

#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present

#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present

#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present

#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present

#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present

#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present

#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present

#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present

#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present

#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present

#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present

#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present

#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present

#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present

#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present

#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present

#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present

#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present

#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PBORCTL register.

//

//*****************************************************************************

#define SYSCTL_PBORCTL_BOR0     0x00000004  // VDD under BOR0 Event Action

#define SYSCTL_PBORCTL_BOR1     0x00000002  // VDD under BOR1 Event Action


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRCR0 register.

//

//*****************************************************************************

#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control

#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control

#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control

#define SYSCTL_SRCR0_PWM0       0x00100000  // PWM Reset Control

#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control

#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control

#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRCR1 register.

//

//*****************************************************************************

#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control

#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control

#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control

#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control

#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control

#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control

#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control

#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control

#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control

#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control

#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control

#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control

#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control

#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control

#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRCR2 register.

//

//*****************************************************************************

#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control

#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control

#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control

#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control

#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control

#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control

#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control

#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control

#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RIS register.

//

//*****************************************************************************

#define SYSCTL_RIS_BOR0RIS      0x00000800  // VDD under BOR0 Raw Interrupt

                                            // Status

#define SYSCTL_RIS_VDDARIS      0x00000400  // VDDA Power OK Event Raw

                                            // Interrupt Status

#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt

                                            // Status

#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt

                                            // Status

#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status

#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Failure Raw

                                            // Interrupt Status

#define SYSCTL_RIS_BOR1RIS      0x00000002  // VDD under BOR1 Raw Interrupt

                                            // Status


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_IMC register.

//

//*****************************************************************************

#define SYSCTL_IMC_BOR0IM       0x00000800  // VDD under BOR0 Interrupt Mask

#define SYSCTL_IMC_VDDAIM       0x00000400  // VDDA Power OK Interrupt Mask

#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask

#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask

#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask

#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Failure

                                            // Interrupt Mask

#define SYSCTL_IMC_BOR1IM       0x00000002  // VDD under BOR1 Interrupt Mask


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_MISC register.

//

//*****************************************************************************

#define SYSCTL_MISC_BOR0MIS     0x00000800  // VDD under BOR0 Masked Interrupt

                                            // Status

#define SYSCTL_MISC_VDDAMIS     0x00000400  // VDDA Power OK Masked Interrupt

                                            // Status

#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt

                                            // Status

#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt

                                            // Status

#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status

#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Failure Masked

                                            // Interrupt Status

#define SYSCTL_MISC_BOR1MIS     0x00000002  // VDD under BOR1 Masked Interrupt

                                            // Status


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RESC register.

//

//*****************************************************************************

#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset

#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset

#define SYSCTL_RESC_SW          0x00000010  // Software Reset

#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset

#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset

#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset

#define SYSCTL_RESC_EXT         0x00000001  // External Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCC register.

//

//*****************************************************************************

#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating

#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor

#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider

#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor

#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor

#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2

#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4

#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8

#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16

#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32

#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64

#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down

#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass

#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value

#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz

#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz

#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz

#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz

#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz

#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz

#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz

#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz

#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz

#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz

#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz

#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz

#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz

#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz

#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz

#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz

#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz

#define SYSCTL_RCC_XTAL_18MHZ   0x000005C0  // 18.0 MHz (USB)

#define SYSCTL_RCC_XTAL_20MHZ   0x00000600  // 20.0 MHz (USB)

#define SYSCTL_RCC_XTAL_24MHZ   0x00000640  // 24.0 MHz (USB)

#define SYSCTL_RCC_XTAL_25MHZ   0x00000680  // 25.0 MHz (USB)

#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source

#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC

#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC

#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4

#define SYSCTL_RCC_OSCSRC_30    0x00000030  // LFIOSC

#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable

#define SYSCTL_RCC_SYSDIV_S     23


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL

// register.

//

//*****************************************************************************

#define SYSCTL_GPIOHBCTL_PORTG  0x00000040  // Port G Advanced High-Performance

                                            // Bus

#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance

                                            // Bus

#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance

                                            // Bus

#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance

                                            // Bus

#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance

                                            // Bus

#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance

                                            // Bus

#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance

                                            // Bus


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCC2 register.

//

//*****************************************************************************

#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2

#define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200

                                            // MHz

#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2

#define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2

#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL

#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2

#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2

#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2

#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC

#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC

#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4

#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // LFIOSC

#define SYSCTL_RCC2_SYSDIV2_S   23


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.

//

//*****************************************************************************

#define SYSCTL_MOSCCTL_NOXTAL   0x00000004  // No Crystal Connected

#define SYSCTL_MOSCCTL_MOSCIM   0x00000002  // MOSC Failure Action

#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGC0 register.

//

//*****************************************************************************

#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control

#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control

#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control

#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control

#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control

#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control

#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed

#define SYSCTL_RCGC0_ADC1SPD_125K                                             \

                                0x00000000  // 125K samples/second

#define SYSCTL_RCGC0_ADC1SPD_250K                                             \

                                0x00000400  // 250K samples/second

#define SYSCTL_RCGC0_ADC1SPD_500K                                             \

                                0x00000800  // 500K samples/second

#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second

#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed

#define SYSCTL_RCGC0_ADC0SPD_125K                                             \

                                0x00000000  // 125K samples/second

#define SYSCTL_RCGC0_ADC0SPD_250K                                             \

                                0x00000100  // 250K samples/second

#define SYSCTL_RCGC0_ADC0SPD_500K                                             \

                                0x00000200  // 500K samples/second

#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second

#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGC1 register.

//

//*****************************************************************************

#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating

#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating

#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control

#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control

#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control

#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control

#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control

#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control

#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control

#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control

#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control

#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control

#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control

#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control

#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGC2 register.

//

//*****************************************************************************

#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control

#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control

#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control

#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control

#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control

#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control

#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control

#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control

#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGC0 register.

//

//*****************************************************************************

#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control

#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control

#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control

#define SYSCTL_SCGC0_PWM0       0x00100000  // PWM Clock Gating Control

#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control

#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control

#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGC1 register.

//

//*****************************************************************************

#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating

#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating

#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control

#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control

#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control

#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control

#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control

#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control

#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control

#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control

#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control

#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control

#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control

#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control

#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGC2 register.

//

//*****************************************************************************

#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control

#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control

#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control

#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control

#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control

#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control

#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control

#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control

#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGC0 register.

//

//*****************************************************************************

#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control

#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control

#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control

#define SYSCTL_DCGC0_PWM0       0x00100000  // PWM Clock Gating Control

#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control

#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control

#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGC1 register.

//

//*****************************************************************************

#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating

#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating

#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control

#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control

#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control

#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control

#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control

#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control

#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control

#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control

#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control

#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control

#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control

#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control

#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGC2 register.

//

//*****************************************************************************

#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control

#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control

#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control

#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control

#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control

#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control

#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control

#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control

#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG

// register.

//

//*****************************************************************************

#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override

#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source

#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC

#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC

#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // LFIOSC

#define SYSCTL_DSLPCLKCFG_PIOSCPD                                             \

                                0x00000002  // PIOSC Power Down Request

#define SYSCTL_DSLPCLKCFG_D_S   23


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SYSPROP register.

//

//*****************************************************************************

#define SYSCTL_SYSPROP_FPU      0x00000001  // FPU Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PIOSCCAL

// register.

//

//*****************************************************************************

#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value

#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim

#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value

#define SYSCTL_PIOSCCAL_UT_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PLLFREQ0

// register.

//

//*****************************************************************************

#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00  // PLL M Fractional Value

#define SYSCTL_PLLFREQ0_MINT_M  0x000003FF  // PLL M Integer Value

#define SYSCTL_PLLFREQ0_MFRAC_S 10

#define SYSCTL_PLLFREQ0_MINT_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PLLFREQ1

// register.

//

//*****************************************************************************

#define SYSCTL_PLLFREQ1_Q_M     0x00001F00  // PLL Q Value

#define SYSCTL_PLLFREQ1_N_M     0x0000001F  // PLL N Value

#define SYSCTL_PLLFREQ1_Q_S     8

#define SYSCTL_PLLFREQ1_N_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.

//

//*****************************************************************************

#define SYSCTL_PLLSTAT_LOCK     0x00000001  // PLL Lock


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG

// register.

//

//*****************************************************************************

#define SYSCTL_SLPPWRCFG_FLASHPM_M                                            \

                                0x00000030  // Flash Power Modes

#define SYSCTL_SLPPWRCFG_FLASHPM_NRM                                          \

                                0x00000000  // Active Mode

#define SYSCTL_SLPPWRCFG_FLASHPM_SLP                                          \

                                0x00000020  // Low Power Mode

#define SYSCTL_SLPPWRCFG_SRAMPM_M                                             \

                                0x00000003  // SRAM Power Modes

#define SYSCTL_SLPPWRCFG_SRAMPM_NRM                                           \

                                0x00000000  // Active Mode

#define SYSCTL_SLPPWRCFG_SRAMPM_SBY                                           \

                                0x00000001  // Standby Mode

#define SYSCTL_SLPPWRCFG_SRAMPM_LP                                            \

                                0x00000003  // Low Power Mode


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG

// register.

//

//*****************************************************************************

#define SYSCTL_DSLPPWRCFG_FLASHPM_M                                           \

                                0x00000030  // Flash Power Modes

#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM                                         \

                                0x00000000  // Active Mode

#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP                                         \

                                0x00000020  // Low Power Mode

#define SYSCTL_DSLPPWRCFG_SRAMPM_M                                            \

                                0x00000003  // SRAM Power Modes

#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM                                          \

                                0x00000000  // Active Mode

#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY                                          \

                                0x00000001  // Standby Mode

#define SYSCTL_DSLPPWRCFG_SRAMPM_LP                                           \

                                0x00000003  // Low Power Mode


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DC9 register.

//

//*****************************************************************************

#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present

#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present

#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present

#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present

#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present

#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present

#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present

#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present

#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present

#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present

#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present

#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present

#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present

#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present

#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present

#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.

//

//*****************************************************************************

#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer

                                            // Available


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_LDOSPCTL

// register.

//

//*****************************************************************************

#define SYSCTL_LDOSPCTL_VADJEN  0x80000000  // Voltage Adjust Enable

#define SYSCTL_LDOSPCTL_VLDO_M  0x000000FF  // LDO Output Voltage

#define SYSCTL_LDOSPCTL_VLDO_0_90V                                            \

                                0x00000012  // 0.90 V

#define SYSCTL_LDOSPCTL_VLDO_0_95V                                            \

                                0x00000013  // 0.95 V

#define SYSCTL_LDOSPCTL_VLDO_1_00V                                            \

                                0x00000014  // 1.00 V

#define SYSCTL_LDOSPCTL_VLDO_1_05V                                            \

                                0x00000015  // 1.05 V

#define SYSCTL_LDOSPCTL_VLDO_1_10V                                            \

                                0x00000016  // 1.10 V

#define SYSCTL_LDOSPCTL_VLDO_1_15V                                            \

                                0x00000017  // 1.15 V

#define SYSCTL_LDOSPCTL_VLDO_1_20V                                            \

                                0x00000018  // 1.20 V


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_LDODPCTL

// register.

//

//*****************************************************************************

#define SYSCTL_LDODPCTL_VADJEN  0x80000000  // Voltage Adjust Enable

#define SYSCTL_LDODPCTL_VLDO_M  0x000000FF  // LDO Output Voltage

#define SYSCTL_LDODPCTL_VLDO_0_90V                                            \

                                0x00000012  // 0.90 V

#define SYSCTL_LDODPCTL_VLDO_0_95V                                            \

                                0x00000013  // 0.95 V

#define SYSCTL_LDODPCTL_VLDO_1_00V                                            \

                                0x00000014  // 1.00 V

#define SYSCTL_LDODPCTL_VLDO_1_05V                                            \

                                0x00000015  // 1.05 V

#define SYSCTL_LDODPCTL_VLDO_1_10V                                            \

                                0x00000016  // 1.10 V

#define SYSCTL_LDODPCTL_VLDO_1_15V                                            \

                                0x00000017  // 1.15 V

#define SYSCTL_LDODPCTL_VLDO_1_20V                                            \

                                0x00000018  // 1.20 V


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPWD register.

//

//*****************************************************************************

#define SYSCTL_PPWD_P1          0x00000002  // Watchdog Timer 1 Present

#define SYSCTL_PPWD_P0          0x00000001  // Watchdog Timer 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPTIMER register.

//

//*****************************************************************************

#define SYSCTL_PPTIMER_P5       0x00000020  // 16/32-Bit General-Purpose Timer

                                            // 5 Present

#define SYSCTL_PPTIMER_P4       0x00000010  // 16/32-Bit General-Purpose Timer

                                            // 4 Present

#define SYSCTL_PPTIMER_P3       0x00000008  // 16/32-Bit General-Purpose Timer

                                            // 3 Present

#define SYSCTL_PPTIMER_P2       0x00000004  // 16/32-Bit General-Purpose Timer

                                            // 2 Present

#define SYSCTL_PPTIMER_P1       0x00000002  // 16/32-Bit General-Purpose Timer

                                            // 1 Present

#define SYSCTL_PPTIMER_P0       0x00000001  // 16/32-Bit General-Purpose Timer

                                            // 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPGPIO register.

//

//*****************************************************************************

#define SYSCTL_PPGPIO_P14       0x00004000  // GPIO Port Q Present

#define SYSCTL_PPGPIO_P13       0x00002000  // GPIO Port P Present

#define SYSCTL_PPGPIO_P12       0x00001000  // GPIO Port N Present

#define SYSCTL_PPGPIO_P11       0x00000800  // GPIO Port M Present

#define SYSCTL_PPGPIO_P10       0x00000400  // GPIO Port L Present

#define SYSCTL_PPGPIO_P9        0x00000200  // GPIO Port K Present

#define SYSCTL_PPGPIO_P8        0x00000100  // GPIO Port J Present

#define SYSCTL_PPGPIO_P7        0x00000080  // GPIO Port H Present

#define SYSCTL_PPGPIO_P6        0x00000040  // GPIO Port G Present

#define SYSCTL_PPGPIO_P5        0x00000020  // GPIO Port F Present

#define SYSCTL_PPGPIO_P4        0x00000010  // GPIO Port E Present

#define SYSCTL_PPGPIO_P3        0x00000008  // GPIO Port D Present

#define SYSCTL_PPGPIO_P2        0x00000004  // GPIO Port C Present

#define SYSCTL_PPGPIO_P1        0x00000002  // GPIO Port B Present

#define SYSCTL_PPGPIO_P0        0x00000001  // GPIO Port A Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPDMA register.

//

//*****************************************************************************

#define SYSCTL_PPDMA_P0         0x00000001  // uDMA Module Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPHIB register.

//

//*****************************************************************************

#define SYSCTL_PPHIB_P0         0x00000001  // Hibernation Module Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPUART register.

//

//*****************************************************************************

#define SYSCTL_PPUART_P7        0x00000080  // UART Module 7 Present

#define SYSCTL_PPUART_P6        0x00000040  // UART Module 6 Present

#define SYSCTL_PPUART_P5        0x00000020  // UART Module 5 Present

#define SYSCTL_PPUART_P4        0x00000010  // UART Module 4 Present

#define SYSCTL_PPUART_P3        0x00000008  // UART Module 3 Present

#define SYSCTL_PPUART_P2        0x00000004  // UART Module 2 Present

#define SYSCTL_PPUART_P1        0x00000002  // UART Module 1 Present

#define SYSCTL_PPUART_P0        0x00000001  // UART Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPSSI register.

//

//*****************************************************************************

#define SYSCTL_PPSSI_P3         0x00000008  // SSI Module 3 Present

#define SYSCTL_PPSSI_P2         0x00000004  // SSI Module 2 Present

#define SYSCTL_PPSSI_P1         0x00000002  // SSI Module 1 Present

#define SYSCTL_PPSSI_P0         0x00000001  // SSI Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPI2C register.

//

//*****************************************************************************

#define SYSCTL_PPI2C_P5         0x00000020  // I2C Module 5 Present

#define SYSCTL_PPI2C_P4         0x00000010  // I2C Module 4 Present

#define SYSCTL_PPI2C_P3         0x00000008  // I2C Module 3 Present

#define SYSCTL_PPI2C_P2         0x00000004  // I2C Module 2 Present

#define SYSCTL_PPI2C_P1         0x00000002  // I2C Module 1 Present

#define SYSCTL_PPI2C_P0         0x00000001  // I2C Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPUSB register.

//

//*****************************************************************************

#define SYSCTL_PPUSB_P0         0x00000001  // USB Module Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPCAN register.

//

//*****************************************************************************

#define SYSCTL_PPCAN_P1         0x00000002  // CAN Module 1 Present

#define SYSCTL_PPCAN_P0         0x00000001  // CAN Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPADC register.

//

//*****************************************************************************

#define SYSCTL_PPADC_P1         0x00000002  // ADC Module 1 Present

#define SYSCTL_PPADC_P0         0x00000001  // ADC Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPACMP register.

//

//*****************************************************************************

#define SYSCTL_PPACMP_P0        0x00000001  // Analog Comparator Module Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPPWM register.

//

//*****************************************************************************

#define SYSCTL_PPPWM_P1         0x00000002  // PWM Module 1 Present

#define SYSCTL_PPPWM_P0         0x00000001  // PWM Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPQEI register.

//

//*****************************************************************************

#define SYSCTL_PPQEI_P1         0x00000002  // QEI Module 1 Present

#define SYSCTL_PPQEI_P0         0x00000001  // QEI Module 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPEEPROM

// register.

//

//*****************************************************************************

#define SYSCTL_PPEEPROM_P0      0x00000001  // EEPROM Module Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PPWTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_PPWTIMER_P5      0x00000020  // 32/64-Bit Wide General-Purpose

                                            // Timer 5 Present

#define SYSCTL_PPWTIMER_P4      0x00000010  // 32/64-Bit Wide General-Purpose

                                            // Timer 4 Present

#define SYSCTL_PPWTIMER_P3      0x00000008  // 32/64-Bit Wide General-Purpose

                                            // Timer 3 Present

#define SYSCTL_PPWTIMER_P2      0x00000004  // 32/64-Bit Wide General-Purpose

                                            // Timer 2 Present

#define SYSCTL_PPWTIMER_P1      0x00000002  // 32/64-Bit Wide General-Purpose

                                            // Timer 1 Present

#define SYSCTL_PPWTIMER_P0      0x00000001  // 32/64-Bit Wide General-Purpose

                                            // Timer 0 Present


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRWD register.

//

//*****************************************************************************

#define SYSCTL_SRWD_R1          0x00000002  // Watchdog Timer 1 Software Reset

#define SYSCTL_SRWD_R0          0x00000001  // Watchdog Timer 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRTIMER register.

//

//*****************************************************************************

#define SYSCTL_SRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer

                                            // 5 Software Reset

#define SYSCTL_SRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer

                                            // 4 Software Reset

#define SYSCTL_SRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer

                                            // 3 Software Reset

#define SYSCTL_SRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer

                                            // 2 Software Reset

#define SYSCTL_SRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer

                                            // 1 Software Reset

#define SYSCTL_SRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer

                                            // 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRGPIO register.

//

//*****************************************************************************

#define SYSCTL_SRGPIO_R6        0x00000040  // GPIO Port G Software Reset

#define SYSCTL_SRGPIO_R5        0x00000020  // GPIO Port F Software Reset

#define SYSCTL_SRGPIO_R4        0x00000010  // GPIO Port E Software Reset

#define SYSCTL_SRGPIO_R3        0x00000008  // GPIO Port D Software Reset

#define SYSCTL_SRGPIO_R2        0x00000004  // GPIO Port C Software Reset

#define SYSCTL_SRGPIO_R1        0x00000002  // GPIO Port B Software Reset

#define SYSCTL_SRGPIO_R0        0x00000001  // GPIO Port A Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRDMA register.

//

//*****************************************************************************

#define SYSCTL_SRDMA_R0         0x00000001  // uDMA Module Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRUART register.

//

//*****************************************************************************

#define SYSCTL_SRUART_R7        0x00000080  // UART Module 7 Software Reset

#define SYSCTL_SRUART_R6        0x00000040  // UART Module 6 Software Reset

#define SYSCTL_SRUART_R5        0x00000020  // UART Module 5 Software Reset

#define SYSCTL_SRUART_R4        0x00000010  // UART Module 4 Software Reset

#define SYSCTL_SRUART_R3        0x00000008  // UART Module 3 Software Reset

#define SYSCTL_SRUART_R2        0x00000004  // UART Module 2 Software Reset

#define SYSCTL_SRUART_R1        0x00000002  // UART Module 1 Software Reset

#define SYSCTL_SRUART_R0        0x00000001  // UART Module 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRSSI register.

//

//*****************************************************************************

#define SYSCTL_SRSSI_R3         0x00000008  // SSI Module 3 Software Reset

#define SYSCTL_SRSSI_R2         0x00000004  // SSI Module 2 Software Reset

#define SYSCTL_SRSSI_R1         0x00000002  // SSI Module 1 Software Reset

#define SYSCTL_SRSSI_R0         0x00000001  // SSI Module 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRI2C register.

//

//*****************************************************************************

#define SYSCTL_SRI2C_R5         0x00000020  // I2C Module 5 Software Reset

#define SYSCTL_SRI2C_R4         0x00000010  // I2C Module 4 Software Reset

#define SYSCTL_SRI2C_R3         0x00000008  // I2C Module 3 Software Reset

#define SYSCTL_SRI2C_R2         0x00000004  // I2C Module 2 Software Reset

#define SYSCTL_SRI2C_R1         0x00000002  // I2C Module 1 Software Reset

#define SYSCTL_SRI2C_R0         0x00000001  // I2C Module 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRUSB register.

//

//*****************************************************************************

#define SYSCTL_SRUSB_R0         0x00000001  // USB Module Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRCAN register.

//

//*****************************************************************************

#define SYSCTL_SRCAN_R1         0x00000002  // CAN Module 1 Software Reset

#define SYSCTL_SRCAN_R0         0x00000001  // CAN Module 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRADC register.

//

//*****************************************************************************

#define SYSCTL_SRADC_R1         0x00000002  // ADC Module 1 Software Reset

#define SYSCTL_SRADC_R0         0x00000001  // ADC Module 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRACMP register.

//

//*****************************************************************************

#define SYSCTL_SRACMP_R0        0x00000001  // Analog Comparator Module 0

                                            // Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRPWM register.

//

//*****************************************************************************

#define SYSCTL_SRPWM_R1         0x00000002  // PWM Module 1 Software Reset

#define SYSCTL_SRPWM_R0         0x00000001  // PWM Module 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRQEI register.

//

//*****************************************************************************

#define SYSCTL_SRQEI_R1         0x00000002  // QEI Module 1 Software Reset

#define SYSCTL_SRQEI_R0         0x00000001  // QEI Module 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SREEPROM

// register.

//

//*****************************************************************************

#define SYSCTL_SREEPROM_R0      0x00000001  // EEPROM Module Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SRWTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_SRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose

                                            // Timer 5 Software Reset

#define SYSCTL_SRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose

                                            // Timer 4 Software Reset

#define SYSCTL_SRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose

                                            // Timer 3 Software Reset

#define SYSCTL_SRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose

                                            // Timer 2 Software Reset

#define SYSCTL_SRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose

                                            // Timer 1 Software Reset

#define SYSCTL_SRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose

                                            // Timer 0 Software Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCWD register.

//

//*****************************************************************************

#define SYSCTL_RCGCWD_R1        0x00000002  // Watchdog Timer 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCWD_R0        0x00000001  // Watchdog Timer 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_RCGCTIMER_R5     0x00000020  // 16/32-Bit General-Purpose Timer

                                            // 5 Run Mode Clock Gating Control

#define SYSCTL_RCGCTIMER_R4     0x00000010  // 16/32-Bit General-Purpose Timer

                                            // 4 Run Mode Clock Gating Control

#define SYSCTL_RCGCTIMER_R3     0x00000008  // 16/32-Bit General-Purpose Timer

                                            // 3 Run Mode Clock Gating Control

#define SYSCTL_RCGCTIMER_R2     0x00000004  // 16/32-Bit General-Purpose Timer

                                            // 2 Run Mode Clock Gating Control

#define SYSCTL_RCGCTIMER_R1     0x00000002  // 16/32-Bit General-Purpose Timer

                                            // 1 Run Mode Clock Gating Control

#define SYSCTL_RCGCTIMER_R0     0x00000001  // 16/32-Bit General-Purpose Timer

                                            // 0 Run Mode Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCGPIO

// register.

//

//*****************************************************************************

#define SYSCTL_RCGCGPIO_R6      0x00000040  // GPIO Port G Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCGPIO_R5      0x00000020  // GPIO Port F Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCGPIO_R4      0x00000010  // GPIO Port E Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCGPIO_R3      0x00000008  // GPIO Port D Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCGPIO_R2      0x00000004  // GPIO Port C Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCGPIO_R1      0x00000002  // GPIO Port B Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCGPIO_R0      0x00000001  // GPIO Port A Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.

//

//*****************************************************************************

#define SYSCTL_RCGCDMA_R0       0x00000001  // uDMA Module Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCUART

// register.

//

//*****************************************************************************

#define SYSCTL_RCGCUART_R7      0x00000080  // UART Module 7 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCUART_R6      0x00000040  // UART Module 6 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCUART_R5      0x00000020  // UART Module 5 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCUART_R4      0x00000010  // UART Module 4 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCUART_R3      0x00000008  // UART Module 3 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCUART_R2      0x00000004  // UART Module 2 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCUART_R1      0x00000002  // UART Module 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCUART_R0      0x00000001  // UART Module 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.

//

//*****************************************************************************

#define SYSCTL_RCGCSSI_R3       0x00000008  // SSI Module 3 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCSSI_R2       0x00000004  // SSI Module 2 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCSSI_R1       0x00000002  // SSI Module 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCSSI_R0       0x00000001  // SSI Module 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.

//

//*****************************************************************************

#define SYSCTL_RCGCI2C_R5       0x00000020  // I2C Module 5 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCI2C_R4       0x00000010  // I2C Module 4 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCI2C_R3       0x00000008  // I2C Module 3 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCI2C_R2       0x00000004  // I2C Module 2 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCI2C_R1       0x00000002  // I2C Module 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCI2C_R0       0x00000001  // I2C Module 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.

//

//*****************************************************************************

#define SYSCTL_RCGCUSB_R0       0x00000001  // USB Module Run Mode Clock Gating

                                            // Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.

//

//*****************************************************************************

#define SYSCTL_RCGCCAN_R1       0x00000002  // CAN Module 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCCAN_R0       0x00000001  // CAN Module 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCADC register.

//

//*****************************************************************************

#define SYSCTL_RCGCADC_R1       0x00000002  // ADC Module 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCADC_R0       0x00000001  // ADC Module 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCACMP

// register.

//

//*****************************************************************************

#define SYSCTL_RCGCACMP_R0      0x00000001  // Analog Comparator Module 0 Run

                                            // Mode Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.

//

//*****************************************************************************

#define SYSCTL_RCGCPWM_R1       0x00000002  // PWM Module 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCPWM_R0       0x00000001  // PWM Module 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.

//

//*****************************************************************************

#define SYSCTL_RCGCQEI_R1       0x00000002  // QEI Module 1 Run Mode Clock

                                            // Gating Control

#define SYSCTL_RCGCQEI_R0       0x00000001  // QEI Module 0 Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM

// register.

//

//*****************************************************************************

#define SYSCTL_RCGCEEPROM_R0    0x00000001  // EEPROM Module Run Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_RCGCWTIMER_R5    0x00000020  // 32/64-Bit Wide General-Purpose

                                            // Timer 5 Run Mode Clock Gating

                                            // Control

#define SYSCTL_RCGCWTIMER_R4    0x00000010  // 32/64-Bit Wide General-Purpose

                                            // Timer 4 Run Mode Clock Gating

                                            // Control

#define SYSCTL_RCGCWTIMER_R3    0x00000008  // 32/64-Bit Wide General-Purpose

                                            // Timer 3 Run Mode Clock Gating

                                            // Control

#define SYSCTL_RCGCWTIMER_R2    0x00000004  // 32/64-Bit Wide General-Purpose

                                            // Timer 2 Run Mode Clock Gating

                                            // Control

#define SYSCTL_RCGCWTIMER_R1    0x00000002  // 32/64-Bit Wide General-Purpose

                                            // Timer 1 Run Mode Clock Gating

                                            // Control

#define SYSCTL_RCGCWTIMER_R0    0x00000001  // 32/64-Bit Wide General-Purpose

                                            // Timer 0 Run Mode Clock Gating

                                            // Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCWD register.

//

//*****************************************************************************

#define SYSCTL_SCGCWD_S1        0x00000002  // Watchdog Timer 1 Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_SCGCWD_S0        0x00000001  // Watchdog Timer 0 Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_SCGCTIMER_S5     0x00000020  // 16/32-Bit General-Purpose Timer

                                            // 5 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCTIMER_S4     0x00000010  // 16/32-Bit General-Purpose Timer

                                            // 4 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCTIMER_S3     0x00000008  // 16/32-Bit General-Purpose Timer

                                            // 3 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCTIMER_S2     0x00000004  // 16/32-Bit General-Purpose Timer

                                            // 2 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCTIMER_S1     0x00000002  // 16/32-Bit General-Purpose Timer

                                            // 1 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCTIMER_S0     0x00000001  // 16/32-Bit General-Purpose Timer

                                            // 0 Sleep Mode Clock Gating

                                            // Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCGPIO

// register.

//

//*****************************************************************************

#define SYSCTL_SCGCGPIO_S6      0x00000040  // GPIO Port G Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCGPIO_S5      0x00000020  // GPIO Port F Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCGPIO_S4      0x00000010  // GPIO Port E Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCGPIO_S3      0x00000008  // GPIO Port D Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCGPIO_S2      0x00000004  // GPIO Port C Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCGPIO_S1      0x00000002  // GPIO Port B Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCGPIO_S0      0x00000001  // GPIO Port A Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.

//

//*****************************************************************************

#define SYSCTL_SCGCDMA_S0       0x00000001  // uDMA Module Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCUART

// register.

//

//*****************************************************************************

#define SYSCTL_SCGCUART_S7      0x00000080  // UART Module 7 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCUART_S6      0x00000040  // UART Module 6 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCUART_S5      0x00000020  // UART Module 5 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCUART_S4      0x00000010  // UART Module 4 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCUART_S3      0x00000008  // UART Module 3 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCUART_S2      0x00000004  // UART Module 2 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCUART_S1      0x00000002  // UART Module 1 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCUART_S0      0x00000001  // UART Module 0 Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.

//

//*****************************************************************************

#define SYSCTL_SCGCSSI_S3       0x00000008  // SSI Module 3 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCSSI_S2       0x00000004  // SSI Module 2 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCSSI_S1       0x00000002  // SSI Module 1 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCSSI_S0       0x00000001  // SSI Module 0 Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.

//

//*****************************************************************************

#define SYSCTL_SCGCI2C_S5       0x00000020  // I2C Module 5 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCI2C_S4       0x00000010  // I2C Module 4 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCI2C_S3       0x00000008  // I2C Module 3 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCI2C_S2       0x00000004  // I2C Module 2 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCI2C_S1       0x00000002  // I2C Module 1 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCI2C_S0       0x00000001  // I2C Module 0 Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.

//

//*****************************************************************************

#define SYSCTL_SCGCUSB_S0       0x00000001  // USB Module Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.

//

//*****************************************************************************

#define SYSCTL_SCGCCAN_S1       0x00000002  // CAN Module 1 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCCAN_S0       0x00000001  // CAN Module 0 Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCADC register.

//

//*****************************************************************************

#define SYSCTL_SCGCADC_S1       0x00000002  // ADC Module 1 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCADC_S0       0x00000001  // ADC Module 0 Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCACMP

// register.

//

//*****************************************************************************

#define SYSCTL_SCGCACMP_S0      0x00000001  // Analog Comparator Module 0 Sleep

                                            // Mode Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.

//

//*****************************************************************************

#define SYSCTL_SCGCPWM_S1       0x00000002  // PWM Module 1 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCPWM_S0       0x00000001  // PWM Module 0 Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.

//

//*****************************************************************************

#define SYSCTL_SCGCQEI_S1       0x00000002  // QEI Module 1 Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_SCGCQEI_S0       0x00000001  // QEI Module 0 Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM

// register.

//

//*****************************************************************************

#define SYSCTL_SCGCEEPROM_S0    0x00000001  // EEPROM Module Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_SCGCWTIMER_S5    0x00000020  // 32/64-Bit Wide General-Purpose

                                            // Timer 5 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCWTIMER_S4    0x00000010  // 32/64-Bit Wide General-Purpose

                                            // Timer 4 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCWTIMER_S3    0x00000008  // 32/64-Bit Wide General-Purpose

                                            // Timer 3 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCWTIMER_S2    0x00000004  // 32/64-Bit Wide General-Purpose

                                            // Timer 2 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCWTIMER_S1    0x00000002  // 32/64-Bit Wide General-Purpose

                                            // Timer 1 Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_SCGCWTIMER_S0    0x00000001  // 32/64-Bit Wide General-Purpose

                                            // Timer 0 Sleep Mode Clock Gating

                                            // Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCWD register.

//

//*****************************************************************************

#define SYSCTL_DCGCWD_D1        0x00000002  // Watchdog Timer 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCWD_D0        0x00000001  // Watchdog Timer 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_DCGCTIMER_D5     0x00000020  // 16/32-Bit General-Purpose Timer

                                            // 5 Deep-Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_DCGCTIMER_D4     0x00000010  // 16/32-Bit General-Purpose Timer

                                            // 4 Deep-Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_DCGCTIMER_D3     0x00000008  // 16/32-Bit General-Purpose Timer

                                            // 3 Deep-Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_DCGCTIMER_D2     0x00000004  // 16/32-Bit General-Purpose Timer

                                            // 2 Deep-Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_DCGCTIMER_D1     0x00000002  // 16/32-Bit General-Purpose Timer

                                            // 1 Deep-Sleep Mode Clock Gating

                                            // Control

#define SYSCTL_DCGCTIMER_D0     0x00000001  // 16/32-Bit General-Purpose Timer

                                            // 0 Deep-Sleep Mode Clock Gating

                                            // Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCGPIO

// register.

//

//*****************************************************************************

#define SYSCTL_DCGCGPIO_D6      0x00000040  // GPIO Port G Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCGPIO_D5      0x00000020  // GPIO Port F Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCGPIO_D4      0x00000010  // GPIO Port E Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCGPIO_D3      0x00000008  // GPIO Port D Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCGPIO_D2      0x00000004  // GPIO Port C Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCGPIO_D1      0x00000002  // GPIO Port B Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCGPIO_D0      0x00000001  // GPIO Port A Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.

//

//*****************************************************************************

#define SYSCTL_DCGCDMA_D0       0x00000001  // uDMA Module Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCUART

// register.

//

//*****************************************************************************

#define SYSCTL_DCGCUART_D7      0x00000080  // UART Module 7 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCUART_D6      0x00000040  // UART Module 6 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCUART_D5      0x00000020  // UART Module 5 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCUART_D4      0x00000010  // UART Module 4 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCUART_D3      0x00000008  // UART Module 3 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCUART_D2      0x00000004  // UART Module 2 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCUART_D1      0x00000002  // UART Module 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCUART_D0      0x00000001  // UART Module 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.

//

//*****************************************************************************

#define SYSCTL_DCGCSSI_D3       0x00000008  // SSI Module 3 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCSSI_D2       0x00000004  // SSI Module 2 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCSSI_D1       0x00000002  // SSI Module 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCSSI_D0       0x00000001  // SSI Module 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.

//

//*****************************************************************************

#define SYSCTL_DCGCI2C_D5       0x00000020  // I2C Module 5 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCI2C_D4       0x00000010  // I2C Module 4 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCI2C_D3       0x00000008  // I2C Module 3 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCI2C_D2       0x00000004  // I2C Module 2 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCI2C_D1       0x00000002  // I2C Module 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCI2C_D0       0x00000001  // I2C Module 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.

//

//*****************************************************************************

#define SYSCTL_DCGCUSB_D0       0x00000001  // USB Module Deep-Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.

//

//*****************************************************************************

#define SYSCTL_DCGCCAN_D1       0x00000002  // CAN Module 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCCAN_D0       0x00000001  // CAN Module 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCADC register.

//

//*****************************************************************************

#define SYSCTL_DCGCADC_D1       0x00000002  // ADC Module 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCADC_D0       0x00000001  // ADC Module 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCACMP

// register.

//

//*****************************************************************************

#define SYSCTL_DCGCACMP_D0      0x00000001  // Analog Comparator Module 0

                                            // Deep-Sleep Mode Clock Gating

                                            // Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.

//

//*****************************************************************************

#define SYSCTL_DCGCPWM_D1       0x00000002  // PWM Module 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCPWM_D0       0x00000001  // PWM Module 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.

//

//*****************************************************************************

#define SYSCTL_DCGCQEI_D1       0x00000002  // QEI Module 1 Deep-Sleep Mode

                                            // Clock Gating Control

#define SYSCTL_DCGCQEI_D0       0x00000001  // QEI Module 0 Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM

// register.

//

//*****************************************************************************

#define SYSCTL_DCGCEEPROM_D0    0x00000001  // EEPROM Module Deep-Sleep Mode

                                            // Clock Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_DCGCWTIMER_D5    0x00000020  // 32/64-Bit Wide General-Purpose

                                            // Timer 5 Deep-Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_DCGCWTIMER_D4    0x00000010  // 32/64-Bit Wide General-Purpose

                                            // Timer 4 Deep-Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_DCGCWTIMER_D3    0x00000008  // 32/64-Bit Wide General-Purpose

                                            // Timer 3 Deep-Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_DCGCWTIMER_D2    0x00000004  // 32/64-Bit Wide General-Purpose

                                            // Timer 2 Deep-Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_DCGCWTIMER_D1    0x00000002  // 32/64-Bit Wide General-Purpose

                                            // Timer 1 Deep-Sleep Mode Clock

                                            // Gating Control

#define SYSCTL_DCGCWTIMER_D0    0x00000001  // 32/64-Bit Wide General-Purpose

                                            // Timer 0 Deep-Sleep Mode Clock

                                            // Gating Control


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRWD register.

//

//*****************************************************************************

#define SYSCTL_PRWD_R1          0x00000002  // Watchdog Timer 1 Peripheral

                                            // Ready

#define SYSCTL_PRWD_R0          0x00000001  // Watchdog Timer 0 Peripheral

                                            // Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRTIMER register.

//

//*****************************************************************************

#define SYSCTL_PRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer

                                            // 5 Peripheral Ready

#define SYSCTL_PRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer

                                            // 4 Peripheral Ready

#define SYSCTL_PRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer

                                            // 3 Peripheral Ready

#define SYSCTL_PRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer

                                            // 2 Peripheral Ready

#define SYSCTL_PRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer

                                            // 1 Peripheral Ready

#define SYSCTL_PRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer

                                            // 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRGPIO register.

//

//*****************************************************************************

#define SYSCTL_PRGPIO_R6        0x00000040  // GPIO Port G Peripheral Ready

#define SYSCTL_PRGPIO_R5        0x00000020  // GPIO Port F Peripheral Ready

#define SYSCTL_PRGPIO_R4        0x00000010  // GPIO Port E Peripheral Ready

#define SYSCTL_PRGPIO_R3        0x00000008  // GPIO Port D Peripheral Ready

#define SYSCTL_PRGPIO_R2        0x00000004  // GPIO Port C Peripheral Ready

#define SYSCTL_PRGPIO_R1        0x00000002  // GPIO Port B Peripheral Ready

#define SYSCTL_PRGPIO_R0        0x00000001  // GPIO Port A Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRDMA register.

//

//*****************************************************************************

#define SYSCTL_PRDMA_R0         0x00000001  // uDMA Module Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRUART register.

//

//*****************************************************************************

#define SYSCTL_PRUART_R7        0x00000080  // UART Module 7 Peripheral Ready

#define SYSCTL_PRUART_R6        0x00000040  // UART Module 6 Peripheral Ready

#define SYSCTL_PRUART_R5        0x00000020  // UART Module 5 Peripheral Ready

#define SYSCTL_PRUART_R4        0x00000010  // UART Module 4 Peripheral Ready

#define SYSCTL_PRUART_R3        0x00000008  // UART Module 3 Peripheral Ready

#define SYSCTL_PRUART_R2        0x00000004  // UART Module 2 Peripheral Ready

#define SYSCTL_PRUART_R1        0x00000002  // UART Module 1 Peripheral Ready

#define SYSCTL_PRUART_R0        0x00000001  // UART Module 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRSSI register.

//

//*****************************************************************************

#define SYSCTL_PRSSI_R3         0x00000008  // SSI Module 3 Peripheral Ready

#define SYSCTL_PRSSI_R2         0x00000004  // SSI Module 2 Peripheral Ready

#define SYSCTL_PRSSI_R1         0x00000002  // SSI Module 1 Peripheral Ready

#define SYSCTL_PRSSI_R0         0x00000001  // SSI Module 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRI2C register.

//

//*****************************************************************************

#define SYSCTL_PRI2C_R5         0x00000020  // I2C Module 5 Peripheral Ready

#define SYSCTL_PRI2C_R4         0x00000010  // I2C Module 4 Peripheral Ready

#define SYSCTL_PRI2C_R3         0x00000008  // I2C Module 3 Peripheral Ready

#define SYSCTL_PRI2C_R2         0x00000004  // I2C Module 2 Peripheral Ready

#define SYSCTL_PRI2C_R1         0x00000002  // I2C Module 1 Peripheral Ready

#define SYSCTL_PRI2C_R0         0x00000001  // I2C Module 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRUSB register.

//

//*****************************************************************************

#define SYSCTL_PRUSB_R0         0x00000001  // USB Module Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRCAN register.

//

//*****************************************************************************

#define SYSCTL_PRCAN_R1         0x00000002  // CAN Module 1 Peripheral Ready

#define SYSCTL_PRCAN_R0         0x00000001  // CAN Module 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRADC register.

//

//*****************************************************************************

#define SYSCTL_PRADC_R1         0x00000002  // ADC Module 1 Peripheral Ready

#define SYSCTL_PRADC_R0         0x00000001  // ADC Module 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRACMP register.

//

//*****************************************************************************

#define SYSCTL_PRACMP_R0        0x00000001  // Analog Comparator Module 0

                                            // Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRPWM register.

//

//*****************************************************************************

#define SYSCTL_PRPWM_R1         0x00000002  // PWM Module 1 Peripheral Ready

#define SYSCTL_PRPWM_R0         0x00000001  // PWM Module 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRQEI register.

//

//*****************************************************************************

#define SYSCTL_PRQEI_R1         0x00000002  // QEI Module 1 Peripheral Ready

#define SYSCTL_PRQEI_R0         0x00000001  // QEI Module 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PREEPROM

// register.

//

//*****************************************************************************

#define SYSCTL_PREEPROM_R0      0x00000001  // EEPROM Module Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the SYSCTL_PRWTIMER

// register.

//

//*****************************************************************************

#define SYSCTL_PRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose

                                            // Timer 5 Peripheral Ready

#define SYSCTL_PRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose

                                            // Timer 4 Peripheral Ready

#define SYSCTL_PRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose

                                            // Timer 3 Peripheral Ready

#define SYSCTL_PRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose

                                            // Timer 2 Peripheral Ready

#define SYSCTL_PRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose

                                            // Timer 1 Peripheral Ready

#define SYSCTL_PRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose

                                            // Timer 0 Peripheral Ready


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_STAT register.

//

//*****************************************************************************

#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1

#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status

#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle

#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data

#define UDMA_STAT_STATE_RD_SRCENDP                                            \

                                0x00000020  // Reading source end pointer

#define UDMA_STAT_STATE_RD_DSTENDP                                            \

                                0x00000030  // Reading destination end pointer

#define UDMA_STAT_STATE_RD_SRCDAT                                             \

                                0x00000040  // Reading source data

#define UDMA_STAT_STATE_WR_DSTDAT                                             \

                                0x00000050  // Writing destination data

#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to

                                            // clear

#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data

#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled

#define UDMA_STAT_STATE_DONE    0x00000090  // Done

#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined

#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status

#define UDMA_STAT_DMACHANS_S    16


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CFG register.

//

//*****************************************************************************

#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CTLBASE register.

//

//*****************************************************************************

#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address

#define UDMA_CTLBASE_ADDR_S     10


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_ALTBASE register.

//

//*****************************************************************************

#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address

                                            // Pointer

#define UDMA_ALTBASE_ADDR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_WAITSTAT register.

//

//*****************************************************************************

#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_SWREQ register.

//

//*****************************************************************************

#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_USEBURSTSET

// register.

//

//*****************************************************************************

#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_USEBURSTCLR

// register.

//

//*****************************************************************************

#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_REQMASKSET

// register.

//

//*****************************************************************************

#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_REQMASKCLR

// register.

//

//*****************************************************************************

#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_ENASET register.

//

//*****************************************************************************

#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_ENACLR register.

//

//*****************************************************************************

#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_ALTSET register.

//

//*****************************************************************************

#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_ALTCLR register.

//

//*****************************************************************************

#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_PRIOSET register.

//

//*****************************************************************************

#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_PRIOCLR register.

//

//*****************************************************************************

#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_ERRCLR register.

//

//*****************************************************************************

#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CHASGN register.

//

//*****************************************************************************

#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select

#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel

                                            // assignment

#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel

                                            // assignment


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CHIS register.

//

//*****************************************************************************

#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CHMAP0 register.

//

//*****************************************************************************

#define UDMA_CHMAP0_CH7SEL_M    0xF0000000  // uDMA Channel 7 Source Select

#define UDMA_CHMAP0_CH6SEL_M    0x0F000000  // uDMA Channel 6 Source Select

#define UDMA_CHMAP0_CH5SEL_M    0x00F00000  // uDMA Channel 5 Source Select

#define UDMA_CHMAP0_CH4SEL_M    0x000F0000  // uDMA Channel 4 Source Select

#define UDMA_CHMAP0_CH3SEL_M    0x0000F000  // uDMA Channel 3 Source Select

#define UDMA_CHMAP0_CH2SEL_M    0x00000F00  // uDMA Channel 2 Source Select

#define UDMA_CHMAP0_CH1SEL_M    0x000000F0  // uDMA Channel 1 Source Select

#define UDMA_CHMAP0_CH0SEL_M    0x0000000F  // uDMA Channel 0 Source Select

#define UDMA_CHMAP0_CH7SEL_S    28

#define UDMA_CHMAP0_CH6SEL_S    24

#define UDMA_CHMAP0_CH5SEL_S    20

#define UDMA_CHMAP0_CH4SEL_S    16

#define UDMA_CHMAP0_CH3SEL_S    12

#define UDMA_CHMAP0_CH2SEL_S    8

#define UDMA_CHMAP0_CH1SEL_S    4

#define UDMA_CHMAP0_CH0SEL_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CHMAP1 register.

//

//*****************************************************************************

#define UDMA_CHMAP1_CH15SEL_M   0xF0000000  // uDMA Channel 15 Source Select

#define UDMA_CHMAP1_CH14SEL_M   0x0F000000  // uDMA Channel 14 Source Select

#define UDMA_CHMAP1_CH13SEL_M   0x00F00000  // uDMA Channel 13 Source Select

#define UDMA_CHMAP1_CH12SEL_M   0x000F0000  // uDMA Channel 12 Source Select

#define UDMA_CHMAP1_CH11SEL_M   0x0000F000  // uDMA Channel 11 Source Select

#define UDMA_CHMAP1_CH10SEL_M   0x00000F00  // uDMA Channel 10 Source Select

#define UDMA_CHMAP1_CH9SEL_M    0x000000F0  // uDMA Channel 9 Source Select

#define UDMA_CHMAP1_CH8SEL_M    0x0000000F  // uDMA Channel 8 Source Select

#define UDMA_CHMAP1_CH15SEL_S   28

#define UDMA_CHMAP1_CH14SEL_S   24

#define UDMA_CHMAP1_CH13SEL_S   20

#define UDMA_CHMAP1_CH12SEL_S   16

#define UDMA_CHMAP1_CH11SEL_S   12

#define UDMA_CHMAP1_CH10SEL_S   8

#define UDMA_CHMAP1_CH9SEL_S    4

#define UDMA_CHMAP1_CH8SEL_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CHMAP2 register.

//

//*****************************************************************************

#define UDMA_CHMAP2_CH23SEL_M   0xF0000000  // uDMA Channel 23 Source Select

#define UDMA_CHMAP2_CH22SEL_M   0x0F000000  // uDMA Channel 22 Source Select

#define UDMA_CHMAP2_CH21SEL_M   0x00F00000  // uDMA Channel 21 Source Select

#define UDMA_CHMAP2_CH20SEL_M   0x000F0000  // uDMA Channel 20 Source Select

#define UDMA_CHMAP2_CH19SEL_M   0x0000F000  // uDMA Channel 19 Source Select

#define UDMA_CHMAP2_CH18SEL_M   0x00000F00  // uDMA Channel 18 Source Select

#define UDMA_CHMAP2_CH17SEL_M   0x000000F0  // uDMA Channel 17 Source Select

#define UDMA_CHMAP2_CH16SEL_M   0x0000000F  // uDMA Channel 16 Source Select

#define UDMA_CHMAP2_CH23SEL_S   28

#define UDMA_CHMAP2_CH22SEL_S   24

#define UDMA_CHMAP2_CH21SEL_S   20

#define UDMA_CHMAP2_CH20SEL_S   16

#define UDMA_CHMAP2_CH19SEL_S   12

#define UDMA_CHMAP2_CH18SEL_S   8

#define UDMA_CHMAP2_CH17SEL_S   4

#define UDMA_CHMAP2_CH16SEL_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_CHMAP3 register.

//

//*****************************************************************************

#define UDMA_CHMAP3_CH31SEL_M   0xF0000000  // uDMA Channel 31 Source Select

#define UDMA_CHMAP3_CH30SEL_M   0x0F000000  // uDMA Channel 30 Source Select

#define UDMA_CHMAP3_CH29SEL_M   0x00F00000  // uDMA Channel 29 Source Select

#define UDMA_CHMAP3_CH28SEL_M   0x000F0000  // uDMA Channel 28 Source Select

#define UDMA_CHMAP3_CH27SEL_M   0x0000F000  // uDMA Channel 27 Source Select

#define UDMA_CHMAP3_CH26SEL_M   0x00000F00  // uDMA Channel 26 Source Select

#define UDMA_CHMAP3_CH25SEL_M   0x000000F0  // uDMA Channel 25 Source Select

#define UDMA_CHMAP3_CH24SEL_M   0x0000000F  // uDMA Channel 24 Source Select

#define UDMA_CHMAP3_CH31SEL_S   28

#define UDMA_CHMAP3_CH30SEL_S   24

#define UDMA_CHMAP3_CH29SEL_S   20

#define UDMA_CHMAP3_CH28SEL_S   16

#define UDMA_CHMAP3_CH27SEL_S   12

#define UDMA_CHMAP3_CH26SEL_S   8

#define UDMA_CHMAP3_CH25SEL_S   4

#define UDMA_CHMAP3_CH24SEL_S   0


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_O_SRCENDP register.

//

//*****************************************************************************

#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer

#define UDMA_SRCENDP_ADDR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_O_DSTENDP register.

//

//*****************************************************************************

#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer

#define UDMA_DSTENDP_ADDR_S     0


//*****************************************************************************

//

// The following are defines for the bit fields in the UDMA_O_CHCTL register.

//

//*****************************************************************************

#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment

#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte

#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word

#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word

#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment

#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size

#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte

#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word

#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word

#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment

#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte

#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word

#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word

#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment

#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size

#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte

#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word

#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word

#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size

#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer

#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers

#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers

#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers

#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers

#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers

#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers

#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers

#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers

#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers

#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers

#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)

#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst

#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode

#define UDMA_CHCTL_XFERMODE_STOP                                              \

                                0x00000000  // Stop

#define UDMA_CHCTL_XFERMODE_BASIC                                             \

                                0x00000001  // Basic

#define UDMA_CHCTL_XFERMODE_AUTO                                              \

                                0x00000002  // Auto-Request

#define UDMA_CHCTL_XFERMODE_PINGPONG                                          \

                                0x00000003  // Ping-Pong

#define UDMA_CHCTL_XFERMODE_MEM_SG                                            \

                                0x00000004  // Memory Scatter-Gather

#define UDMA_CHCTL_XFERMODE_MEM_SGA                                           \

                                0x00000005  // Alternate Memory Scatter-Gather

#define UDMA_CHCTL_XFERMODE_PER_SG                                            \

                                0x00000006  // Peripheral Scatter-Gather

#define UDMA_CHCTL_XFERMODE_PER_SGA                                           \

                                0x00000007  // Alternate Peripheral

                                            // Scatter-Gather

#define UDMA_CHCTL_XFERSIZE_S   4


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTLR register.

//

//*****************************************************************************

#define NVIC_ACTLR_DISOOFP      0x00000200  // Disable Out-Of-Order Floating

                                            // Point

#define NVIC_ACTLR_DISFPCA      0x00000100  // Disable CONTROL

#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding

#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer

#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple

                                            // Cycle Instructions


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ST_CTRL register.

//

//*****************************************************************************

#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag

#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source

#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable

#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ST_RELOAD register.

//

//*****************************************************************************

#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value

#define NVIC_ST_RELOAD_S        0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ST_CURRENT

// register.

//

//*****************************************************************************

#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value

#define NVIC_ST_CURRENT_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN0 register.

//

//*****************************************************************************

#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN1 register.

//

//*****************************************************************************

#define NVIC_EN1_INT_M          0xFFFFFFFF  // Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN2 register.

//

//*****************************************************************************

#define NVIC_EN2_INT_M          0xFFFFFFFF  // Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN3 register.

//

//*****************************************************************************

#define NVIC_EN3_INT_M          0xFFFFFFFF  // Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN4 register.

//

//*****************************************************************************

#define NVIC_EN4_INT_M          0x000007FF  // Interrupt Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS0 register.

//

//*****************************************************************************

#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS1 register.

//

//*****************************************************************************

#define NVIC_DIS1_INT_M         0xFFFFFFFF  // Interrupt Disable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS2 register.

//

//*****************************************************************************

#define NVIC_DIS2_INT_M         0xFFFFFFFF  // Interrupt Disable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS3 register.

//

//*****************************************************************************

#define NVIC_DIS3_INT_M         0xFFFFFFFF  // Interrupt Disable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS4 register.

//

//*****************************************************************************

#define NVIC_DIS4_INT_M         0x000007FF  // Interrupt Disable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND0 register.

//

//*****************************************************************************

#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND1 register.

//

//*****************************************************************************

#define NVIC_PEND1_INT_M        0xFFFFFFFF  // Interrupt Set Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND2 register.

//

//*****************************************************************************

#define NVIC_PEND2_INT_M        0xFFFFFFFF  // Interrupt Set Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND3 register.

//

//*****************************************************************************

#define NVIC_PEND3_INT_M        0xFFFFFFFF  // Interrupt Set Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND4 register.

//

//*****************************************************************************

#define NVIC_PEND4_INT_M        0x000007FF  // Interrupt Set Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND0 register.

//

//*****************************************************************************

#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND1 register.

//

//*****************************************************************************

#define NVIC_UNPEND1_INT_M      0xFFFFFFFF  // Interrupt Clear Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND2 register.

//

//*****************************************************************************

#define NVIC_UNPEND2_INT_M      0xFFFFFFFF  // Interrupt Clear Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND3 register.

//

//*****************************************************************************

#define NVIC_UNPEND3_INT_M      0xFFFFFFFF  // Interrupt Clear Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND4 register.

//

//*****************************************************************************

#define NVIC_UNPEND4_INT_M      0x000007FF  // Interrupt Clear Pending


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE0 register.

//

//*****************************************************************************

#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE1 register.

//

//*****************************************************************************

#define NVIC_ACTIVE1_INT_M      0xFFFFFFFF  // Interrupt Active


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE2 register.

//

//*****************************************************************************

#define NVIC_ACTIVE2_INT_M      0xFFFFFFFF  // Interrupt Active


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE3 register.

//

//*****************************************************************************

#define NVIC_ACTIVE3_INT_M      0xFFFFFFFF  // Interrupt Active


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE4 register.

//

//*****************************************************************************

#define NVIC_ACTIVE4_INT_M      0x000007FF  // Interrupt Active


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI0 register.

//

//*****************************************************************************

#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask

#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask

#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask

#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask

#define NVIC_PRI0_INT3_S        29

#define NVIC_PRI0_INT2_S        21

#define NVIC_PRI0_INT1_S        13

#define NVIC_PRI0_INT0_S        5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI1 register.

//

//*****************************************************************************

#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask

#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask

#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask

#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask

#define NVIC_PRI1_INT7_S        29

#define NVIC_PRI1_INT6_S        21

#define NVIC_PRI1_INT5_S        13

#define NVIC_PRI1_INT4_S        5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI2 register.

//

//*****************************************************************************

#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask

#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask

#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask

#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask

#define NVIC_PRI2_INT11_S       29

#define NVIC_PRI2_INT10_S       21

#define NVIC_PRI2_INT9_S        13

#define NVIC_PRI2_INT8_S        5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI3 register.

//

//*****************************************************************************

#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask

#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask

#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask

#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask

#define NVIC_PRI3_INT15_S       29

#define NVIC_PRI3_INT14_S       21

#define NVIC_PRI3_INT13_S       13

#define NVIC_PRI3_INT12_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI4 register.

//

//*****************************************************************************

#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask

#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask

#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask

#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask

#define NVIC_PRI4_INT19_S       29

#define NVIC_PRI4_INT18_S       21

#define NVIC_PRI4_INT17_S       13

#define NVIC_PRI4_INT16_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI5 register.

//

//*****************************************************************************

#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask

#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask

#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask

#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask

#define NVIC_PRI5_INT23_S       29

#define NVIC_PRI5_INT22_S       21

#define NVIC_PRI5_INT21_S       13

#define NVIC_PRI5_INT20_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI6 register.

//

//*****************************************************************************

#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask

#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask

#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask

#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask

#define NVIC_PRI6_INT27_S       29

#define NVIC_PRI6_INT26_S       21

#define NVIC_PRI6_INT25_S       13

#define NVIC_PRI6_INT24_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI7 register.

//

//*****************************************************************************

#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask

#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask

#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask

#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask

#define NVIC_PRI7_INT31_S       29

#define NVIC_PRI7_INT30_S       21

#define NVIC_PRI7_INT29_S       13

#define NVIC_PRI7_INT28_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI8 register.

//

//*****************************************************************************

#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask

#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask

#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask

#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask

#define NVIC_PRI8_INT35_S       29

#define NVIC_PRI8_INT34_S       21

#define NVIC_PRI8_INT33_S       13

#define NVIC_PRI8_INT32_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI9 register.

//

//*****************************************************************************

#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask

#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask

#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask

#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask

#define NVIC_PRI9_INT39_S       29

#define NVIC_PRI9_INT38_S       21

#define NVIC_PRI9_INT37_S       13

#define NVIC_PRI9_INT36_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI10 register.

//

//*****************************************************************************

#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask

#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask

#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask

#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask

#define NVIC_PRI10_INT43_S      29

#define NVIC_PRI10_INT42_S      21

#define NVIC_PRI10_INT41_S      13

#define NVIC_PRI10_INT40_S      5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI11 register.

//

//*****************************************************************************

#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask

#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask

#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask

#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask

#define NVIC_PRI11_INT47_S      29

#define NVIC_PRI11_INT46_S      21

#define NVIC_PRI11_INT45_S      13

#define NVIC_PRI11_INT44_S      5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI12 register.

//

//*****************************************************************************

#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask

#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask

#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask

#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask

#define NVIC_PRI12_INT51_S      29

#define NVIC_PRI12_INT50_S      21

#define NVIC_PRI12_INT49_S      13

#define NVIC_PRI12_INT48_S      5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI13 register.

//

//*****************************************************************************

#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask

#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask

#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask

#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask

#define NVIC_PRI13_INT55_S      29

#define NVIC_PRI13_INT54_S      21

#define NVIC_PRI13_INT53_S      13

#define NVIC_PRI13_INT52_S      5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI14 register.

//

//*****************************************************************************

#define NVIC_PRI14_INTD_M       0xE0000000  // Interrupt 59 Priority Mask

#define NVIC_PRI14_INTC_M       0x00E00000  // Interrupt 58 Priority Mask

#define NVIC_PRI14_INTB_M       0x0000E000  // Interrupt 57 Priority Mask

#define NVIC_PRI14_INTA_M       0x000000E0  // Interrupt 56 Priority Mask

#define NVIC_PRI14_INTD_S       29

#define NVIC_PRI14_INTC_S       21

#define NVIC_PRI14_INTB_S       13

#define NVIC_PRI14_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI15 register.

//

//*****************************************************************************

#define NVIC_PRI15_INTD_M       0xE0000000  // Interrupt 63 Priority Mask

#define NVIC_PRI15_INTC_M       0x00E00000  // Interrupt 62 Priority Mask

#define NVIC_PRI15_INTB_M       0x0000E000  // Interrupt 61 Priority Mask

#define NVIC_PRI15_INTA_M       0x000000E0  // Interrupt 60 Priority Mask

#define NVIC_PRI15_INTD_S       29

#define NVIC_PRI15_INTC_S       21

#define NVIC_PRI15_INTB_S       13

#define NVIC_PRI15_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI16 register.

//

//*****************************************************************************

#define NVIC_PRI16_INTD_M       0xE0000000  // Interrupt 67 Priority Mask

#define NVIC_PRI16_INTC_M       0x00E00000  // Interrupt 66 Priority Mask

#define NVIC_PRI16_INTB_M       0x0000E000  // Interrupt 65 Priority Mask

#define NVIC_PRI16_INTA_M       0x000000E0  // Interrupt 64 Priority Mask

#define NVIC_PRI16_INTD_S       29

#define NVIC_PRI16_INTC_S       21

#define NVIC_PRI16_INTB_S       13

#define NVIC_PRI16_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI17 register.

//

//*****************************************************************************

#define NVIC_PRI17_INTD_M       0xE0000000  // Interrupt 71 Priority Mask

#define NVIC_PRI17_INTC_M       0x00E00000  // Interrupt 70 Priority Mask

#define NVIC_PRI17_INTB_M       0x0000E000  // Interrupt 69 Priority Mask

#define NVIC_PRI17_INTA_M       0x000000E0  // Interrupt 68 Priority Mask

#define NVIC_PRI17_INTD_S       29

#define NVIC_PRI17_INTC_S       21

#define NVIC_PRI17_INTB_S       13

#define NVIC_PRI17_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI18 register.

//

//*****************************************************************************

#define NVIC_PRI18_INTD_M       0xE0000000  // Interrupt 75 Priority Mask

#define NVIC_PRI18_INTC_M       0x00E00000  // Interrupt 74 Priority Mask

#define NVIC_PRI18_INTB_M       0x0000E000  // Interrupt 73 Priority Mask

#define NVIC_PRI18_INTA_M       0x000000E0  // Interrupt 72 Priority Mask

#define NVIC_PRI18_INTD_S       29

#define NVIC_PRI18_INTC_S       21

#define NVIC_PRI18_INTB_S       13

#define NVIC_PRI18_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI19 register.

//

//*****************************************************************************

#define NVIC_PRI19_INTD_M       0xE0000000  // Interrupt 79 Priority Mask

#define NVIC_PRI19_INTC_M       0x00E00000  // Interrupt 78 Priority Mask

#define NVIC_PRI19_INTB_M       0x0000E000  // Interrupt 77 Priority Mask

#define NVIC_PRI19_INTA_M       0x000000E0  // Interrupt 76 Priority Mask

#define NVIC_PRI19_INTD_S       29

#define NVIC_PRI19_INTC_S       21

#define NVIC_PRI19_INTB_S       13

#define NVIC_PRI19_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI20 register.

//

//*****************************************************************************

#define NVIC_PRI20_INTD_M       0xE0000000  // Interrupt 83 Priority Mask

#define NVIC_PRI20_INTC_M       0x00E00000  // Interrupt 82 Priority Mask

#define NVIC_PRI20_INTB_M       0x0000E000  // Interrupt 81 Priority Mask

#define NVIC_PRI20_INTA_M       0x000000E0  // Interrupt 80 Priority Mask

#define NVIC_PRI20_INTD_S       29

#define NVIC_PRI20_INTC_S       21

#define NVIC_PRI20_INTB_S       13

#define NVIC_PRI20_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI21 register.

//

//*****************************************************************************

#define NVIC_PRI21_INTD_M       0xE0000000  // Interrupt 87 Priority Mask

#define NVIC_PRI21_INTC_M       0x00E00000  // Interrupt 86 Priority Mask

#define NVIC_PRI21_INTB_M       0x0000E000  // Interrupt 85 Priority Mask

#define NVIC_PRI21_INTA_M       0x000000E0  // Interrupt 84 Priority Mask

#define NVIC_PRI21_INTD_S       29

#define NVIC_PRI21_INTC_S       21

#define NVIC_PRI21_INTB_S       13

#define NVIC_PRI21_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI22 register.

//

//*****************************************************************************

#define NVIC_PRI22_INTD_M       0xE0000000  // Interrupt 91 Priority Mask

#define NVIC_PRI22_INTC_M       0x00E00000  // Interrupt 90 Priority Mask

#define NVIC_PRI22_INTB_M       0x0000E000  // Interrupt 89 Priority Mask

#define NVIC_PRI22_INTA_M       0x000000E0  // Interrupt 88 Priority Mask

#define NVIC_PRI22_INTD_S       29

#define NVIC_PRI22_INTC_S       21

#define NVIC_PRI22_INTB_S       13

#define NVIC_PRI22_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI23 register.

//

//*****************************************************************************

#define NVIC_PRI23_INTD_M       0xE0000000  // Interrupt 95 Priority Mask

#define NVIC_PRI23_INTC_M       0x00E00000  // Interrupt 94 Priority Mask

#define NVIC_PRI23_INTB_M       0x0000E000  // Interrupt 93 Priority Mask

#define NVIC_PRI23_INTA_M       0x000000E0  // Interrupt 92 Priority Mask

#define NVIC_PRI23_INTD_S       29

#define NVIC_PRI23_INTC_S       21

#define NVIC_PRI23_INTB_S       13

#define NVIC_PRI23_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI24 register.

//

//*****************************************************************************

#define NVIC_PRI24_INTD_M       0xE0000000  // Interrupt 99 Priority Mask

#define NVIC_PRI24_INTC_M       0x00E00000  // Interrupt 98 Priority Mask

#define NVIC_PRI24_INTB_M       0x0000E000  // Interrupt 97 Priority Mask

#define NVIC_PRI24_INTA_M       0x000000E0  // Interrupt 96 Priority Mask

#define NVIC_PRI24_INTD_S       29

#define NVIC_PRI24_INTC_S       21

#define NVIC_PRI24_INTB_S       13

#define NVIC_PRI24_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI25 register.

//

//*****************************************************************************

#define NVIC_PRI25_INTD_M       0xE0000000  // Interrupt 103 Priority Mask

#define NVIC_PRI25_INTC_M       0x00E00000  // Interrupt 102 Priority Mask

#define NVIC_PRI25_INTB_M       0x0000E000  // Interrupt 101 Priority Mask

#define NVIC_PRI25_INTA_M       0x000000E0  // Interrupt 100 Priority Mask

#define NVIC_PRI25_INTD_S       29

#define NVIC_PRI25_INTC_S       21

#define NVIC_PRI25_INTB_S       13

#define NVIC_PRI25_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI26 register.

//

//*****************************************************************************

#define NVIC_PRI26_INTD_M       0xE0000000  // Interrupt 107 Priority Mask

#define NVIC_PRI26_INTC_M       0x00E00000  // Interrupt 106 Priority Mask

#define NVIC_PRI26_INTB_M       0x0000E000  // Interrupt 105 Priority Mask

#define NVIC_PRI26_INTA_M       0x000000E0  // Interrupt 104 Priority Mask

#define NVIC_PRI26_INTD_S       29

#define NVIC_PRI26_INTC_S       21

#define NVIC_PRI26_INTB_S       13

#define NVIC_PRI26_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI27 register.

//

//*****************************************************************************

#define NVIC_PRI27_INTD_M       0xE0000000  // Interrupt 111 Priority Mask

#define NVIC_PRI27_INTC_M       0x00E00000  // Interrupt 110 Priority Mask

#define NVIC_PRI27_INTB_M       0x0000E000  // Interrupt 109 Priority Mask

#define NVIC_PRI27_INTA_M       0x000000E0  // Interrupt 108 Priority Mask

#define NVIC_PRI27_INTD_S       29

#define NVIC_PRI27_INTC_S       21

#define NVIC_PRI27_INTB_S       13

#define NVIC_PRI27_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI28 register.

//

//*****************************************************************************

#define NVIC_PRI28_INTD_M       0xE0000000  // Interrupt 115 Priority Mask

#define NVIC_PRI28_INTC_M       0x00E00000  // Interrupt 114 Priority Mask

#define NVIC_PRI28_INTB_M       0x0000E000  // Interrupt 113 Priority Mask

#define NVIC_PRI28_INTA_M       0x000000E0  // Interrupt 112 Priority Mask

#define NVIC_PRI28_INTD_S       29

#define NVIC_PRI28_INTC_S       21

#define NVIC_PRI28_INTB_S       13

#define NVIC_PRI28_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI29 register.

//

//*****************************************************************************

#define NVIC_PRI29_INTD_M       0xE0000000  // Interrupt 119 Priority Mask

#define NVIC_PRI29_INTC_M       0x00E00000  // Interrupt 118 Priority Mask

#define NVIC_PRI29_INTB_M       0x0000E000  // Interrupt 117 Priority Mask

#define NVIC_PRI29_INTA_M       0x000000E0  // Interrupt 116 Priority Mask

#define NVIC_PRI29_INTD_S       29

#define NVIC_PRI29_INTC_S       21

#define NVIC_PRI29_INTB_S       13

#define NVIC_PRI29_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI30 register.

//

//*****************************************************************************

#define NVIC_PRI30_INTD_M       0xE0000000  // Interrupt 123 Priority Mask

#define NVIC_PRI30_INTC_M       0x00E00000  // Interrupt 122 Priority Mask

#define NVIC_PRI30_INTB_M       0x0000E000  // Interrupt 121 Priority Mask

#define NVIC_PRI30_INTA_M       0x000000E0  // Interrupt 120 Priority Mask

#define NVIC_PRI30_INTD_S       29

#define NVIC_PRI30_INTC_S       21

#define NVIC_PRI30_INTB_S       13

#define NVIC_PRI30_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI31 register.

//

//*****************************************************************************

#define NVIC_PRI31_INTD_M       0xE0000000  // Interrupt 127 Priority Mask

#define NVIC_PRI31_INTC_M       0x00E00000  // Interrupt 126 Priority Mask

#define NVIC_PRI31_INTB_M       0x0000E000  // Interrupt 125 Priority Mask

#define NVIC_PRI31_INTA_M       0x000000E0  // Interrupt 124 Priority Mask

#define NVIC_PRI31_INTD_S       29

#define NVIC_PRI31_INTC_S       21

#define NVIC_PRI31_INTB_S       13

#define NVIC_PRI31_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI32 register.

//

//*****************************************************************************

#define NVIC_PRI32_INTD_M       0xE0000000  // Interrupt 131 Priority Mask

#define NVIC_PRI32_INTC_M       0x00E00000  // Interrupt 130 Priority Mask

#define NVIC_PRI32_INTB_M       0x0000E000  // Interrupt 129 Priority Mask

#define NVIC_PRI32_INTA_M       0x000000E0  // Interrupt 128 Priority Mask

#define NVIC_PRI32_INTD_S       29

#define NVIC_PRI32_INTC_S       21

#define NVIC_PRI32_INTB_S       13

#define NVIC_PRI32_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI33 register.

//

//*****************************************************************************

#define NVIC_PRI33_INTD_M       0xE0000000  // Interrupt Priority for Interrupt

                                            // [4n+3]

#define NVIC_PRI33_INTC_M       0x00E00000  // Interrupt Priority for Interrupt

                                            // [4n+2]

#define NVIC_PRI33_INTB_M       0x0000E000  // Interrupt Priority for Interrupt

                                            // [4n+1]

#define NVIC_PRI33_INTA_M       0x000000E0  // Interrupt Priority for Interrupt

                                            // [4n]

#define NVIC_PRI33_INTD_S       29

#define NVIC_PRI33_INTC_S       21

#define NVIC_PRI33_INTB_S       13

#define NVIC_PRI33_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI34 register.

//

//*****************************************************************************

#define NVIC_PRI34_INTD_M       0xE0000000  // Interrupt Priority for Interrupt

                                            // [4n+3]

#define NVIC_PRI34_INTC_M       0x00E00000  // Interrupt Priority for Interrupt

                                            // [4n+2]

#define NVIC_PRI34_INTB_M       0x0000E000  // Interrupt Priority for Interrupt

                                            // [4n+1]

#define NVIC_PRI34_INTA_M       0x000000E0  // Interrupt Priority for Interrupt

                                            // [4n]

#define NVIC_PRI34_INTD_S       29

#define NVIC_PRI34_INTC_S       21

#define NVIC_PRI34_INTB_S       13

#define NVIC_PRI34_INTA_S       5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_CPUID register.

//

//*****************************************************************************

#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code

#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM

#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number

#define NVIC_CPUID_CON_M        0x000F0000  // Constant

#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number

#define NVIC_CPUID_PARTNO_CM4   0x0000C240  // Cortex-M4 processor

#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_INT_CTRL register.

//

//*****************************************************************************

#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending

#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending

#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending

#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending

#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending

#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling

#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending

#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000  // Interrupt Pending Vector Number

#define NVIC_INT_CTRL_VEC_PEN_NMI                                             \

                                0x00002000  // NMI

#define NVIC_INT_CTRL_VEC_PEN_HARD                                            \

                                0x00003000  // Hard fault

#define NVIC_INT_CTRL_VEC_PEN_MEM                                             \

                                0x00004000  // Memory management fault

#define NVIC_INT_CTRL_VEC_PEN_BUS                                             \

                                0x00005000  // Bus fault

#define NVIC_INT_CTRL_VEC_PEN_USG                                             \

                                0x00006000  // Usage fault

#define NVIC_INT_CTRL_VEC_PEN_SVC                                             \

                                0x0000B000  // SVCall

#define NVIC_INT_CTRL_VEC_PEN_PNDSV                                           \

                                0x0000E000  // PendSV

#define NVIC_INT_CTRL_VEC_PEN_TICK                                            \

                                0x0000F000  // SysTick

#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base

#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF  // Interrupt Pending Vector Number

#define NVIC_INT_CTRL_VEC_ACT_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_VTABLE register.

//

//*****************************************************************************

#define NVIC_VTABLE_OFFSET_M    0xFFFFFC00  // Vector Table Offset

#define NVIC_VTABLE_OFFSET_S    10


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_APINT register.

//

//*****************************************************************************

#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key

#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key

#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess

#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping

#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split

#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split

#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split

#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split

#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split

#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split

#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split

#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split

#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request

#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault

#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_SYS_CTRL register.

//

//*****************************************************************************

#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending

#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable

#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_CFG_CTRL register.

//

//*****************************************************************************

#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception

                                            // Entry

#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and

                                            // Fault

#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0

#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access

#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger

#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.

//

//*****************************************************************************

#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority

#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority

#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority

#define NVIC_SYS_PRI1_USAGE_S   21

#define NVIC_SYS_PRI1_BUS_S     13

#define NVIC_SYS_PRI1_MEM_S     5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.

//

//*****************************************************************************

#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority

#define NVIC_SYS_PRI2_SVC_S     29


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.

//

//*****************************************************************************

#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority

#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority

#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority

#define NVIC_SYS_PRI3_TICK_S    29

#define NVIC_SYS_PRI3_PENDSV_S  21

#define NVIC_SYS_PRI3_DEBUG_S   5


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL

// register.

//

//*****************************************************************************

#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable

#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable

#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable

#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending

#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending

#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending

#define NVIC_SYS_HND_CTRL_USAGEP                                              \

                                0x00001000  // Usage Fault Pending

#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active

#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active

#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active

#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active

#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active

#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active

#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_FAULT_STAT

// register.

//

//*****************************************************************************

#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault

#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault

#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault

#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault

#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault

#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage

                                            // Fault

#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid

#define NVIC_FAULT_STAT_BLSPERR 0x00002000  // Bus Fault on Floating-Point Lazy

                                            // State Preservation

#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault

#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault

#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error

#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error

#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error

#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address

                                            // Register Valid

#define NVIC_FAULT_STAT_MLSPERR 0x00000020  // Memory Management Fault on

                                            // Floating-Point Lazy State

                                            // Preservation

#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation

#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation

#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation

#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_HFAULT_STAT

// register.

//

//*****************************************************************************

#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event

#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault

#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DEBUG_STAT

// register.

//

//*****************************************************************************

#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted

#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch

#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match

#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction

#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MM_ADDR register.

//

//*****************************************************************************

#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address

#define NVIC_MM_ADDR_S          0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_FAULT_ADDR

// register.

//

//*****************************************************************************

#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address

#define NVIC_FAULT_ADDR_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_CPAC register.

//

//*****************************************************************************

#define NVIC_CPAC_CP11_M        0x00C00000  // CP11 Coprocessor Access

                                            // Privilege

#define NVIC_CPAC_CP11_DIS      0x00000000  // Access Denied

#define NVIC_CPAC_CP11_PRIV     0x00400000  // Privileged Access Only

#define NVIC_CPAC_CP11_FULL     0x00C00000  // Full Access

#define NVIC_CPAC_CP10_M        0x00300000  // CP10 Coprocessor Access

                                            // Privilege

#define NVIC_CPAC_CP10_DIS      0x00000000  // Access Denied

#define NVIC_CPAC_CP10_PRIV     0x00100000  // Privileged Access Only

#define NVIC_CPAC_CP10_FULL     0x00300000  // Full Access


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_TYPE register.

//

//*****************************************************************************

#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions

#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions

#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU

#define NVIC_MPU_TYPE_IREGION_S 16

#define NVIC_MPU_TYPE_DREGION_S 8


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_CTRL register.

//

//*****************************************************************************

#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region

#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults

#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_NUMBER

// register.

//

//*****************************************************************************

#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access

#define NVIC_MPU_NUMBER_S       0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_BASE register.

//

//*****************************************************************************

#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask

#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid

#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number

#define NVIC_MPU_BASE_ADDR_S    5

#define NVIC_MPU_BASE_REGION_S  0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_ATTR register.

//

//*****************************************************************************

#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable

#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege

#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask

#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable

#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable

#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable

#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits

#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask

#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.

//

//*****************************************************************************

#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask

#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid

#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number

#define NVIC_MPU_BASE1_ADDR_S   5

#define NVIC_MPU_BASE1_REGION_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.

//

//*****************************************************************************

#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable

#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege

#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask

#define NVIC_MPU_ATTR1_SHAREABLE                                              \

                                0x00040000  // Shareable

#define NVIC_MPU_ATTR1_CACHEABLE                                              \

                                0x00020000  // Cacheable

#define NVIC_MPU_ATTR1_BUFFRABLE                                              \

                                0x00010000  // Bufferable

#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits

#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask

#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.

//

//*****************************************************************************

#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask

#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid

#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number

#define NVIC_MPU_BASE2_ADDR_S   5

#define NVIC_MPU_BASE2_REGION_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.

//

//*****************************************************************************

#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable

#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege

#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask

#define NVIC_MPU_ATTR2_SHAREABLE                                              \

                                0x00040000  // Shareable

#define NVIC_MPU_ATTR2_CACHEABLE                                              \

                                0x00020000  // Cacheable

#define NVIC_MPU_ATTR2_BUFFRABLE                                              \

                                0x00010000  // Bufferable

#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits

#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask

#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.

//

//*****************************************************************************

#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask

#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid

#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number

#define NVIC_MPU_BASE3_ADDR_S   5

#define NVIC_MPU_BASE3_REGION_S 0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.

//

//*****************************************************************************

#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable

#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege

#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask

#define NVIC_MPU_ATTR3_SHAREABLE                                              \

                                0x00040000  // Shareable

#define NVIC_MPU_ATTR3_CACHEABLE                                              \

                                0x00020000  // Cacheable

#define NVIC_MPU_ATTR3_BUFFRABLE                                              \

                                0x00010000  // Bufferable

#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits

#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask

#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DBG_CTRL register.

//

//*****************************************************************************

#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask

#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key

#define NVIC_DBG_CTRL_S_RESET_ST                                              \

                                0x02000000  // Core has reset since last read

#define NVIC_DBG_CTRL_S_RETIRE_ST                                             \

                                0x01000000  // Core has executed insruction

                                            // since last read

#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up

#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping

#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt

#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available

#define NVIC_DBG_CTRL_C_SNAPSTALL                                             \

                                0x00000020  // Breaks a stalled load/store

#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping

#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core

#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core

#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DBG_XFER register.

//

//*****************************************************************************

#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read

#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register

#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0

#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1

#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2

#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3

#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4

#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5

#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6

#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7

#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8

#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9

#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10

#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11

#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12

#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13

#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14

#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15

#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register

#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP

#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP

#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP

#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DBG_DATA register.

//

//*****************************************************************************

#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache

#define NVIC_DBG_DATA_S         0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DBG_INT register.

//

//*****************************************************************************

#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault

#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors

#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error

#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state

#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check

#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error

#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault

#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status

#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset

#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending

#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_SW_TRIG register.

//

//*****************************************************************************

#define NVIC_SW_TRIG_INTID_M    0x000000FF  // Interrupt ID

#define NVIC_SW_TRIG_INTID_S    0


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_FPCC register.

//

//*****************************************************************************

#define NVIC_FPCC_ASPEN         0x80000000  // Automatic State Preservation

                                            // Enable

#define NVIC_FPCC_LSPEN         0x40000000  // Lazy State Preservation Enable

#define NVIC_FPCC_MONRDY        0x00000100  // Monitor Ready

#define NVIC_FPCC_BFRDY         0x00000040  // Bus Fault Ready

#define NVIC_FPCC_MMRDY         0x00000020  // Memory Management Fault Ready

#define NVIC_FPCC_HFRDY         0x00000010  // Hard Fault Ready

#define NVIC_FPCC_THREAD        0x00000008  // Thread Mode

#define NVIC_FPCC_USER          0x00000002  // User Privilege Level

#define NVIC_FPCC_LSPACT        0x00000001  // Lazy State Preservation Active


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_FPCA register.

//

//*****************************************************************************

#define NVIC_FPCA_ADDRESS_M     0xFFFFFFF8  // Address

#define NVIC_FPCA_ADDRESS_S     3


//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_FPDSC register.

//

//*****************************************************************************

#define NVIC_FPDSC_AHP          0x04000000  // AHP Bit Default

#define NVIC_FPDSC_DN           0x02000000  // DN Bit Default

#define NVIC_FPDSC_FZ           0x01000000  // FZ Bit Default

#define NVIC_FPDSC_RMODE_M      0x00C00000  // RMODE Bit Default

#define NVIC_FPDSC_RMODE_RN     0x00000000  // Round to Nearest (RN) mode

#define NVIC_FPDSC_RMODE_RP     0x00400000  // Round towards Plus Infinity (RP)

                                            // mode

#define NVIC_FPDSC_RMODE_RM     0x00800000  // Round towards Minus Infinity

                                            // (RM) mode

#define NVIC_FPDSC_RMODE_RZ     0x00C00000  // Round towards Zero (RZ) mode


//*****************************************************************************

//

// The following definitions are deprecated.

//

//*****************************************************************************

#ifndef DEPRECATED

#define SYSCTL_DID0_CLASS_BLIZZARD                                            \

                                0x00050000  // Tiva(TM) C Series TM4C123-class

                                            // microcontrollers


#endif


#endif // __TM4C123FE6PM_H__