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EE445M RTOS
Taken at the University of Texas Spring 2015
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EE445M RTOS
Taken at the University of Texas Spring 2015
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Go to the source code of this file.
Macros | |
| #define | EPI_O_CFG 0x00000000 |
| #define | EPI_O_BAUD 0x00000004 |
| #define | EPI_O_BAUD2 0x00000008 |
| #define | EPI_O_HB16CFG 0x00000010 |
| #define | EPI_O_GPCFG 0x00000010 |
| #define | EPI_O_SDRAMCFG 0x00000010 |
| #define | EPI_O_HB8CFG 0x00000010 |
| #define | EPI_O_HB8CFG2 0x00000014 |
| #define | EPI_O_HB16CFG2 0x00000014 |
| #define | EPI_O_ADDRMAP 0x0000001C |
| #define | EPI_O_RSIZE0 0x00000020 |
| #define | EPI_O_RADDR0 0x00000024 |
| #define | EPI_O_RPSTD0 0x00000028 |
| #define | EPI_O_RSIZE1 0x00000030 |
| #define | EPI_O_RADDR1 0x00000034 |
| #define | EPI_O_RPSTD1 0x00000038 |
| #define | EPI_O_STAT 0x00000060 |
| #define | EPI_O_RFIFOCNT 0x0000006C |
| #define | EPI_O_READFIFO0 0x00000070 |
| #define | EPI_O_READFIFO1 0x00000074 |
| #define | EPI_O_READFIFO2 0x00000078 |
| #define | EPI_O_READFIFO3 0x0000007C |
| #define | EPI_O_READFIFO4 0x00000080 |
| #define | EPI_O_READFIFO5 0x00000084 |
| #define | EPI_O_READFIFO6 0x00000088 |
| #define | EPI_O_READFIFO7 0x0000008C |
| #define | EPI_O_FIFOLVL 0x00000200 |
| #define | EPI_O_WFIFOCNT 0x00000204 |
| #define | EPI_O_DMATXCNT 0x00000208 |
| #define | EPI_O_IM 0x00000210 |
| #define | EPI_O_RIS 0x00000214 |
| #define | EPI_O_MIS 0x00000218 |
| #define | EPI_O_EISC 0x0000021C |
| #define | EPI_O_HB8CFG3 0x00000308 |
| #define | EPI_O_HB16CFG3 0x00000308 |
| #define | EPI_O_HB16CFG4 0x0000030C |
| #define | EPI_O_HB8CFG4 0x0000030C |
| #define | EPI_O_HB8TIME 0x00000310 |
| #define | EPI_O_HB16TIME 0x00000310 |
| #define | EPI_O_HB8TIME2 0x00000314 |
| #define | EPI_O_HB16TIME2 0x00000314 |
| #define | EPI_O_HB16TIME3 0x00000318 |
| #define | EPI_O_HB8TIME3 0x00000318 |
| #define | EPI_O_HB8TIME4 0x0000031C |
| #define | EPI_O_HB16TIME4 0x0000031C |
| #define | EPI_O_HBPSRAM 0x00000360 |
| #define | EPI_CFG_INTDIV 0x00000100 |
| #define | EPI_CFG_BLKEN 0x00000010 |
| #define | EPI_CFG_MODE_M 0x0000000F |
| #define | EPI_CFG_MODE_NONE 0x00000000 |
| #define | EPI_CFG_MODE_SDRAM 0x00000001 |
| #define | EPI_CFG_MODE_HB8 0x00000002 |
| #define | EPI_CFG_MODE_HB16 0x00000003 |
| #define | EPI_BAUD_COUNT1_M 0xFFFF0000 |
| #define | EPI_BAUD_COUNT0_M 0x0000FFFF |
| #define | EPI_BAUD_COUNT1_S 16 |
| #define | EPI_BAUD_COUNT0_S 0 |
| #define | EPI_BAUD2_COUNT1_M 0xFFFF0000 |
| #define | EPI_BAUD2_COUNT0_M 0x0000FFFF |
| #define | EPI_BAUD2_COUNT1_S 16 |
| #define | EPI_BAUD2_COUNT0_S 0 |
| #define | EPI_HB16CFG_CLKGATE 0x80000000 |
| #define | EPI_HB16CFG_CLKGATEI 0x40000000 |
| #define | EPI_HB16CFG_CLKINV 0x20000000 |
| #define | EPI_HB16CFG_RDYEN 0x10000000 |
| #define | EPI_HB16CFG_IRDYINV 0x08000000 |
| #define | EPI_HB16CFG_XFFEN 0x00800000 |
| #define | EPI_HB16CFG_XFEEN 0x00400000 |
| #define | EPI_HB16CFG_WRHIGH 0x00200000 |
| #define | EPI_HB16CFG_RDHIGH 0x00100000 |
| #define | EPI_HB16CFG_ALEHIGH 0x00080000 |
| #define | EPI_HB16CFG_WRCRE 0x00040000 |
| #define | EPI_HB16CFG_RDCRE 0x00020000 |
| #define | EPI_HB16CFG_BURST 0x00010000 |
| #define | EPI_HB16CFG_MAXWAIT_M 0x0000FF00 |
| #define | EPI_HB16CFG_WRWS_M 0x000000C0 |
| #define | EPI_HB16CFG_WRWS_2 0x00000000 |
| #define | EPI_HB16CFG_WRWS_4 0x00000040 |
| #define | EPI_HB16CFG_WRWS_6 0x00000080 |
| #define | EPI_HB16CFG_WRWS_8 0x000000C0 |
| #define | EPI_HB16CFG_RDWS_M 0x00000030 |
| #define | EPI_HB16CFG_RDWS_2 0x00000000 |
| #define | EPI_HB16CFG_RDWS_4 0x00000010 |
| #define | EPI_HB16CFG_RDWS_6 0x00000020 |
| #define | EPI_HB16CFG_RDWS_8 0x00000030 |
| #define | EPI_HB16CFG_BSEL 0x00000004 |
| #define | EPI_HB16CFG_MODE_M 0x00000003 |
| #define | EPI_HB16CFG_MODE_ADMUX 0x00000000 |
| #define | EPI_HB16CFG_MODE_ADNMUX 0x00000001 |
| #define | EPI_HB16CFG_MODE_SRAM 0x00000002 |
| #define | EPI_HB16CFG_MODE_XFIFO 0x00000003 |
| #define | EPI_HB16CFG_MAXWAIT_S 8 |
| #define | EPI_GPCFG_CLKPIN 0x80000000 |
| #define | EPI_GPCFG_CLKGATE 0x40000000 |
| #define | EPI_GPCFG_FRM50 0x04000000 |
| #define | EPI_GPCFG_FRMCNT_M 0x03C00000 |
| #define | EPI_GPCFG_WR2CYC 0x00080000 |
| #define | EPI_GPCFG_ASIZE_M 0x00000030 |
| #define | EPI_GPCFG_ASIZE_NONE 0x00000000 |
| #define | EPI_GPCFG_ASIZE_4BIT 0x00000010 |
| #define | EPI_GPCFG_ASIZE_12BIT 0x00000020 |
| #define | EPI_GPCFG_ASIZE_20BIT 0x00000030 |
| #define | EPI_GPCFG_DSIZE_M 0x00000003 |
| #define | EPI_GPCFG_DSIZE_4BIT 0x00000000 |
| #define | EPI_GPCFG_DSIZE_16BIT 0x00000001 |
| #define | EPI_GPCFG_DSIZE_24BIT 0x00000002 |
| #define | EPI_GPCFG_DSIZE_32BIT 0x00000003 |
| #define | EPI_GPCFG_FRMCNT_S 22 |
| #define | EPI_SDRAMCFG_FREQ_M 0xC0000000 |
| #define | EPI_SDRAMCFG_FREQ_NONE 0x00000000 |
| #define | EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 |
| #define | EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 |
| #define | EPI_SDRAMCFG_RFSH_M 0x07FF0000 |
| #define | EPI_SDRAMCFG_SLEEP 0x00000200 |
| #define | EPI_SDRAMCFG_SIZE_M 0x00000003 |
| #define | EPI_SDRAMCFG_SIZE_8MB 0x00000000 |
| #define | EPI_SDRAMCFG_SIZE_16MB 0x00000001 |
| #define | EPI_SDRAMCFG_SIZE_32MB 0x00000002 |
| #define | EPI_SDRAMCFG_SIZE_64MB 0x00000003 |
| #define | EPI_SDRAMCFG_RFSH_S 16 |
| #define | EPI_HB8CFG_CLKGATE 0x80000000 |
| #define | EPI_HB8CFG_CLKGATEI 0x40000000 |
| #define | EPI_HB8CFG_CLKINV 0x20000000 |
| #define | EPI_HB8CFG_RDYEN 0x10000000 |
| #define | EPI_HB8CFG_IRDYINV 0x08000000 |
| #define | EPI_HB8CFG_XFFEN 0x00800000 |
| #define | EPI_HB8CFG_XFEEN 0x00400000 |
| #define | EPI_HB8CFG_WRHIGH 0x00200000 |
| #define | EPI_HB8CFG_RDHIGH 0x00100000 |
| #define | EPI_HB8CFG_ALEHIGH 0x00080000 |
| #define | EPI_HB8CFG_MAXWAIT_M 0x0000FF00 |
| #define | EPI_HB8CFG_WRWS_M 0x000000C0 |
| #define | EPI_HB8CFG_WRWS_2 0x00000000 |
| #define | EPI_HB8CFG_WRWS_4 0x00000040 |
| #define | EPI_HB8CFG_WRWS_6 0x00000080 |
| #define | EPI_HB8CFG_WRWS_8 0x000000C0 |
| #define | EPI_HB8CFG_RDWS_M 0x00000030 |
| #define | EPI_HB8CFG_RDWS_2 0x00000000 |
| #define | EPI_HB8CFG_RDWS_4 0x00000010 |
| #define | EPI_HB8CFG_RDWS_6 0x00000020 |
| #define | EPI_HB8CFG_RDWS_8 0x00000030 |
| #define | EPI_HB8CFG_MODE_M 0x00000003 |
| #define | EPI_HB8CFG_MODE_MUX 0x00000000 |
| #define | EPI_HB8CFG_MODE_NMUX 0x00000001 |
| #define | EPI_HB8CFG_MODE_SRAM 0x00000002 |
| #define | EPI_HB8CFG_MODE_FIFO 0x00000003 |
| #define | EPI_HB8CFG_MAXWAIT_S 8 |
| #define | EPI_HB8CFG2_CSCFGEXT 0x08000000 |
| #define | EPI_HB8CFG2_CSBAUD 0x04000000 |
| #define | EPI_HB8CFG2_CSCFG_M 0x03000000 |
| #define | EPI_HB8CFG2_CSCFG_ALE 0x00000000 |
| #define | EPI_HB8CFG2_CSCFG_CS 0x01000000 |
| #define | EPI_HB8CFG2_CSCFG_DCS 0x02000000 |
| #define | EPI_HB8CFG2_CSCFG_ADCS 0x03000000 |
| #define | EPI_HB8CFG2_WRHIGH 0x00200000 |
| #define | EPI_HB8CFG2_RDHIGH 0x00100000 |
| #define | EPI_HB8CFG2_ALEHIGH 0x00080000 |
| #define | EPI_HB8CFG2_WRWS_M 0x000000C0 |
| #define | EPI_HB8CFG2_WRWS_2 0x00000000 |
| #define | EPI_HB8CFG2_WRWS_4 0x00000040 |
| #define | EPI_HB8CFG2_WRWS_6 0x00000080 |
| #define | EPI_HB8CFG2_WRWS_8 0x000000C0 |
| #define | EPI_HB8CFG2_RDWS_M 0x00000030 |
| #define | EPI_HB8CFG2_RDWS_2 0x00000000 |
| #define | EPI_HB8CFG2_RDWS_4 0x00000010 |
| #define | EPI_HB8CFG2_RDWS_6 0x00000020 |
| #define | EPI_HB8CFG2_RDWS_8 0x00000030 |
| #define | EPI_HB8CFG2_MODE_M 0x00000003 |
| #define | EPI_HB8CFG2_MODE_ADMUX 0x00000000 |
| #define | EPI_HB8CFG2_MODE_AD 0x00000001 |
| #define | EPI_HB16CFG2_CSCFGEXT 0x08000000 |
| #define | EPI_HB16CFG2_CSBAUD 0x04000000 |
| #define | EPI_HB16CFG2_CSCFG_M 0x03000000 |
| #define | EPI_HB16CFG2_CSCFG_ALE 0x00000000 |
| #define | EPI_HB16CFG2_CSCFG_CS 0x01000000 |
| #define | EPI_HB16CFG2_CSCFG_DCS 0x02000000 |
| #define | EPI_HB16CFG2_CSCFG_ADCS 0x03000000 |
| #define | EPI_HB16CFG2_WRHIGH 0x00200000 |
| #define | EPI_HB16CFG2_RDHIGH 0x00100000 |
| #define | EPI_HB16CFG2_ALEHIGH 0x00080000 |
| #define | EPI_HB16CFG2_WRCRE 0x00040000 |
| #define | EPI_HB16CFG2_RDCRE 0x00020000 |
| #define | EPI_HB16CFG2_BURST 0x00010000 |
| #define | EPI_HB16CFG2_WRWS_M 0x000000C0 |
| #define | EPI_HB16CFG2_WRWS_2 0x00000000 |
| #define | EPI_HB16CFG2_WRWS_4 0x00000040 |
| #define | EPI_HB16CFG2_WRWS_6 0x00000080 |
| #define | EPI_HB16CFG2_WRWS_8 0x000000C0 |
| #define | EPI_HB16CFG2_RDWS_M 0x00000030 |
| #define | EPI_HB16CFG2_RDWS_2 0x00000000 |
| #define | EPI_HB16CFG2_RDWS_4 0x00000010 |
| #define | EPI_HB16CFG2_RDWS_6 0x00000020 |
| #define | EPI_HB16CFG2_RDWS_8 0x00000030 |
| #define | EPI_HB16CFG2_MODE_M 0x00000003 |
| #define | EPI_HB16CFG2_MODE_ADMUX 0x00000000 |
| #define | EPI_HB16CFG2_MODE_AD 0x00000001 |
| #define | EPI_ADDRMAP_ECSZ_M 0x00000C00 |
| #define | EPI_ADDRMAP_ECSZ_256B 0x00000000 |
| #define | EPI_ADDRMAP_ECSZ_64KB 0x00000400 |
| #define | EPI_ADDRMAP_ECSZ_16MB 0x00000800 |
| #define | EPI_ADDRMAP_ECSZ_256MB 0x00000C00 |
| #define | EPI_ADDRMAP_ECADR_M 0x00000300 |
| #define | EPI_ADDRMAP_ECADR_NONE 0x00000000 |
| #define | EPI_ADDRMAP_ECADR_1000 0x00000100 |
| #define | EPI_ADDRMAP_EPSZ_M 0x000000C0 |
| #define | EPI_ADDRMAP_EPSZ_256B 0x00000000 |
| #define | EPI_ADDRMAP_EPSZ_64KB 0x00000040 |
| #define | EPI_ADDRMAP_EPSZ_16MB 0x00000080 |
| #define | EPI_ADDRMAP_EPSZ_256MB 0x000000C0 |
| #define | EPI_ADDRMAP_EPADR_M 0x00000030 |
| #define | EPI_ADDRMAP_EPADR_NONE 0x00000000 |
| #define | EPI_ADDRMAP_EPADR_A000 0x00000010 |
| #define | EPI_ADDRMAP_EPADR_C000 0x00000020 |
| #define | EPI_ADDRMAP_EPADR_HBQS 0x00000030 |
| #define | EPI_ADDRMAP_ERSZ_M 0x0000000C |
| #define | EPI_ADDRMAP_ERSZ_256B 0x00000000 |
| #define | EPI_ADDRMAP_ERSZ_64KB 0x00000004 |
| #define | EPI_ADDRMAP_ERSZ_16MB 0x00000008 |
| #define | EPI_ADDRMAP_ERSZ_256MB 0x0000000C |
| #define | EPI_ADDRMAP_ERADR_M 0x00000003 |
| #define | EPI_ADDRMAP_ERADR_NONE 0x00000000 |
| #define | EPI_ADDRMAP_ERADR_6000 0x00000001 |
| #define | EPI_ADDRMAP_ERADR_8000 0x00000002 |
| #define | EPI_ADDRMAP_ERADR_HBQS 0x00000003 |
| #define | EPI_RSIZE0_SIZE_M 0x00000003 |
| #define | EPI_RSIZE0_SIZE_8BIT 0x00000001 |
| #define | EPI_RSIZE0_SIZE_16BIT 0x00000002 |
| #define | EPI_RSIZE0_SIZE_32BIT 0x00000003 |
| #define | EPI_RADDR0_ADDR_M 0xFFFFFFFF |
| #define | EPI_RADDR0_ADDR_S 0 |
| #define | EPI_RPSTD0_POSTCNT_M 0x00001FFF |
| #define | EPI_RPSTD0_POSTCNT_S 0 |
| #define | EPI_RSIZE1_SIZE_M 0x00000003 |
| #define | EPI_RSIZE1_SIZE_8BIT 0x00000001 |
| #define | EPI_RSIZE1_SIZE_16BIT 0x00000002 |
| #define | EPI_RSIZE1_SIZE_32BIT 0x00000003 |
| #define | EPI_RADDR1_ADDR_M 0xFFFFFFFF |
| #define | EPI_RADDR1_ADDR_S 0 |
| #define | EPI_RPSTD1_POSTCNT_M 0x00001FFF |
| #define | EPI_RPSTD1_POSTCNT_S 0 |
| #define | EPI_STAT_XFFULL 0x00000100 |
| #define | EPI_STAT_XFEMPTY 0x00000080 |
| #define | EPI_STAT_INITSEQ 0x00000040 |
| #define | EPI_STAT_WBUSY 0x00000020 |
| #define | EPI_STAT_NBRBUSY 0x00000010 |
| #define | EPI_STAT_ACTIVE 0x00000001 |
| #define | EPI_RFIFOCNT_COUNT_M 0x0000000F |
| #define | EPI_RFIFOCNT_COUNT_S 0 |
| #define | EPI_READFIFO0_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO0_DATA_S 0 |
| #define | EPI_READFIFO1_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO1_DATA_S 0 |
| #define | EPI_READFIFO2_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO2_DATA_S 0 |
| #define | EPI_READFIFO3_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO3_DATA_S 0 |
| #define | EPI_READFIFO4_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO4_DATA_S 0 |
| #define | EPI_READFIFO5_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO5_DATA_S 0 |
| #define | EPI_READFIFO6_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO6_DATA_S 0 |
| #define | EPI_READFIFO7_DATA_M 0xFFFFFFFF |
| #define | EPI_READFIFO7_DATA_S 0 |
| #define | EPI_FIFOLVL_WFERR 0x00020000 |
| #define | EPI_FIFOLVL_RSERR 0x00010000 |
| #define | EPI_FIFOLVL_WRFIFO_M 0x00000070 |
| #define | EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 |
| #define | EPI_FIFOLVL_WRFIFO_2 0x00000020 |
| #define | EPI_FIFOLVL_WRFIFO_1 0x00000030 |
| #define | EPI_FIFOLVL_WRFIFO_NFULL 0x00000040 |
| #define | EPI_FIFOLVL_RDFIFO_M 0x00000007 |
| #define | EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 |
| #define | EPI_FIFOLVL_RDFIFO_1 0x00000001 |
| #define | EPI_FIFOLVL_RDFIFO_2 0x00000002 |
| #define | EPI_FIFOLVL_RDFIFO_4 0x00000003 |
| #define | EPI_FIFOLVL_RDFIFO_6 0x00000004 |
| #define | EPI_FIFOLVL_RDFIFO_7 0x00000005 |
| #define | EPI_FIFOLVL_RDFIFO_8 0x00000006 |
| #define | EPI_WFIFOCNT_WTAV_M 0x00000007 |
| #define | EPI_WFIFOCNT_WTAV_S 0 |
| #define | EPI_DMATXCNT_TXCNT_M 0x0000FFFF |
| #define | EPI_DMATXCNT_TXCNT_S 0 |
| #define | EPI_IM_DMAWRIM 0x00000010 |
| #define | EPI_IM_DMARDIM 0x00000008 |
| #define | EPI_IM_WRIM 0x00000004 |
| #define | EPI_IM_RDIM 0x00000002 |
| #define | EPI_IM_ERRIM 0x00000001 |
| #define | EPI_RIS_DMAWRRIS 0x00000010 |
| #define | EPI_RIS_DMARDRIS 0x00000008 |
| #define | EPI_RIS_WRRIS 0x00000004 |
| #define | EPI_RIS_RDRIS 0x00000002 |
| #define | EPI_RIS_ERRRIS 0x00000001 |
| #define | EPI_MIS_DMAWRMIS 0x00000010 |
| #define | EPI_MIS_DMARDMIS 0x00000008 |
| #define | EPI_MIS_WRMIS 0x00000004 |
| #define | EPI_MIS_RDMIS 0x00000002 |
| #define | EPI_MIS_ERRMIS 0x00000001 |
| #define | EPI_EISC_DMAWRIC 0x00000010 |
| #define | EPI_EISC_DMARDIC 0x00000008 |
| #define | EPI_EISC_WTFULL 0x00000004 |
| #define | EPI_EISC_RSTALL 0x00000002 |
| #define | EPI_EISC_TOUT 0x00000001 |
| #define | EPI_HB8CFG3_WRHIGH 0x00200000 |
| #define | EPI_HB8CFG3_RDHIGH 0x00100000 |
| #define | EPI_HB8CFG3_ALEHIGH 0x00080000 |
| #define | EPI_HB8CFG3_WRWS_M 0x000000C0 |
| #define | EPI_HB8CFG3_WRWS_2 0x00000000 |
| #define | EPI_HB8CFG3_WRWS_4 0x00000040 |
| #define | EPI_HB8CFG3_WRWS_6 0x00000080 |
| #define | EPI_HB8CFG3_WRWS_8 0x000000C0 |
| #define | EPI_HB8CFG3_RDWS_M 0x00000030 |
| #define | EPI_HB8CFG3_RDWS_2 0x00000000 |
| #define | EPI_HB8CFG3_RDWS_4 0x00000010 |
| #define | EPI_HB8CFG3_RDWS_6 0x00000020 |
| #define | EPI_HB8CFG3_RDWS_8 0x00000030 |
| #define | EPI_HB8CFG3_MODE_M 0x00000003 |
| #define | EPI_HB8CFG3_MODE_ADMUX 0x00000000 |
| #define | EPI_HB8CFG3_MODE_AD 0x00000001 |
| #define | EPI_HB16CFG3_WRHIGH 0x00200000 |
| #define | EPI_HB16CFG3_RDHIGH 0x00100000 |
| #define | EPI_HB16CFG3_ALEHIGH 0x00080000 |
| #define | EPI_HB16CFG3_WRCRE 0x00040000 |
| #define | EPI_HB16CFG3_RDCRE 0x00020000 |
| #define | EPI_HB16CFG3_BURST 0x00010000 |
| #define | EPI_HB16CFG3_WRWS_M 0x000000C0 |
| #define | EPI_HB16CFG3_WRWS_2 0x00000000 |
| #define | EPI_HB16CFG3_WRWS_4 0x00000040 |
| #define | EPI_HB16CFG3_WRWS_6 0x00000080 |
| #define | EPI_HB16CFG3_WRWS_8 0x000000C0 |
| #define | EPI_HB16CFG3_RDWS_M 0x00000030 |
| #define | EPI_HB16CFG3_RDWS_2 0x00000000 |
| #define | EPI_HB16CFG3_RDWS_4 0x00000010 |
| #define | EPI_HB16CFG3_RDWS_6 0x00000020 |
| #define | EPI_HB16CFG3_RDWS_8 0x00000030 |
| #define | EPI_HB16CFG3_MODE_M 0x00000003 |
| #define | EPI_HB16CFG3_MODE_ADMUX 0x00000000 |
| #define | EPI_HB16CFG3_MODE_AD 0x00000001 |
| #define | EPI_HB16CFG4_WRHIGH 0x00200000 |
| #define | EPI_HB16CFG4_RDHIGH 0x00100000 |
| #define | EPI_HB16CFG4_ALEHIGH 0x00080000 |
| #define | EPI_HB16CFG4_WRCRE 0x00040000 |
| #define | EPI_HB16CFG4_RDCRE 0x00020000 |
| #define | EPI_HB16CFG4_BURST 0x00010000 |
| #define | EPI_HB16CFG4_WRWS_M 0x000000C0 |
| #define | EPI_HB16CFG4_WRWS_2 0x00000000 |
| #define | EPI_HB16CFG4_WRWS_4 0x00000040 |
| #define | EPI_HB16CFG4_WRWS_6 0x00000080 |
| #define | EPI_HB16CFG4_WRWS_8 0x000000C0 |
| #define | EPI_HB16CFG4_RDWS_M 0x00000030 |
| #define | EPI_HB16CFG4_RDWS_2 0x00000000 |
| #define | EPI_HB16CFG4_RDWS_4 0x00000010 |
| #define | EPI_HB16CFG4_RDWS_6 0x00000020 |
| #define | EPI_HB16CFG4_RDWS_8 0x00000030 |
| #define | EPI_HB16CFG4_MODE_M 0x00000003 |
| #define | EPI_HB16CFG4_MODE_ADMUX 0x00000000 |
| #define | EPI_HB16CFG4_MODE_AD 0x00000001 |
| #define | EPI_HB8CFG4_WRHIGH 0x00200000 |
| #define | EPI_HB8CFG4_RDHIGH 0x00100000 |
| #define | EPI_HB8CFG4_ALEHIGH 0x00080000 |
| #define | EPI_HB8CFG4_WRWS_M 0x000000C0 |
| #define | EPI_HB8CFG4_WRWS_2 0x00000000 |
| #define | EPI_HB8CFG4_WRWS_4 0x00000040 |
| #define | EPI_HB8CFG4_WRWS_6 0x00000080 |
| #define | EPI_HB8CFG4_WRWS_8 0x000000C0 |
| #define | EPI_HB8CFG4_RDWS_M 0x00000030 |
| #define | EPI_HB8CFG4_RDWS_2 0x00000000 |
| #define | EPI_HB8CFG4_RDWS_4 0x00000010 |
| #define | EPI_HB8CFG4_RDWS_6 0x00000020 |
| #define | EPI_HB8CFG4_RDWS_8 0x00000030 |
| #define | EPI_HB8CFG4_MODE_M 0x00000003 |
| #define | EPI_HB8CFG4_MODE_ADMUX 0x00000000 |
| #define | EPI_HB8CFG4_MODE_AD 0x00000001 |
| #define | EPI_HB8TIME_IRDYDLY_M 0x03000000 |
| #define | EPI_HB8TIME_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB8TIME_WRWSM 0x00000010 |
| #define | EPI_HB8TIME_RDWSM 0x00000001 |
| #define | EPI_HB8TIME_IRDYDLY_S 24 |
| #define | EPI_HB8TIME_CAPWIDTH_S 12 |
| #define | EPI_HB16TIME_IRDYDLY_M 0x03000000 |
| #define | EPI_HB16TIME_PSRAMSZ_M 0x00070000 |
| #define | EPI_HB16TIME_PSRAMSZ_0 0x00000000 |
| #define | EPI_HB16TIME_PSRAMSZ_128B 0x00010000 |
| #define | EPI_HB16TIME_PSRAMSZ_256B 0x00020000 |
| #define | EPI_HB16TIME_PSRAMSZ_512B 0x00030000 |
| #define | EPI_HB16TIME_PSRAMSZ_1KB 0x00040000 |
| #define | EPI_HB16TIME_PSRAMSZ_2KB 0x00050000 |
| #define | EPI_HB16TIME_PSRAMSZ_4KB 0x00060000 |
| #define | EPI_HB16TIME_PSRAMSZ_8KB 0x00070000 |
| #define | EPI_HB16TIME_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB16TIME_WRWSM 0x00000010 |
| #define | EPI_HB16TIME_RDWSM 0x00000001 |
| #define | EPI_HB16TIME_IRDYDLY_S 24 |
| #define | EPI_HB16TIME_CAPWIDTH_S 12 |
| #define | EPI_HB8TIME2_IRDYDLY_M 0x03000000 |
| #define | EPI_HB8TIME2_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB8TIME2_WRWSM 0x00000010 |
| #define | EPI_HB8TIME2_RDWSM 0x00000001 |
| #define | EPI_HB8TIME2_IRDYDLY_S 24 |
| #define | EPI_HB8TIME2_CAPWIDTH_S 12 |
| #define | EPI_HB16TIME2_IRDYDLY_M 0x03000000 |
| #define | EPI_HB16TIME2_PSRAMSZ_M 0x00070000 |
| #define | EPI_HB16TIME2_PSRAMSZ_0 0x00000000 |
| #define | EPI_HB16TIME2_PSRAMSZ_128B 0x00010000 |
| #define | EPI_HB16TIME2_PSRAMSZ_256B 0x00020000 |
| #define | EPI_HB16TIME2_PSRAMSZ_512B 0x00030000 |
| #define | EPI_HB16TIME2_PSRAMSZ_1KB 0x00040000 |
| #define | EPI_HB16TIME2_PSRAMSZ_2KB 0x00050000 |
| #define | EPI_HB16TIME2_PSRAMSZ_4KB 0x00060000 |
| #define | EPI_HB16TIME2_PSRAMSZ_8KB 0x00070000 |
| #define | EPI_HB16TIME2_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB16TIME2_WRWSM 0x00000010 |
| #define | EPI_HB16TIME2_RDWSM 0x00000001 |
| #define | EPI_HB16TIME2_IRDYDLY_S 24 |
| #define | EPI_HB16TIME2_CAPWIDTH_S 12 |
| #define | EPI_HB16TIME3_IRDYDLY_M 0x03000000 |
| #define | EPI_HB16TIME3_PSRAMSZ_M 0x00070000 |
| #define | EPI_HB16TIME3_PSRAMSZ_0 0x00000000 |
| #define | EPI_HB16TIME3_PSRAMSZ_128B 0x00010000 |
| #define | EPI_HB16TIME3_PSRAMSZ_256B 0x00020000 |
| #define | EPI_HB16TIME3_PSRAMSZ_512B 0x00030000 |
| #define | EPI_HB16TIME3_PSRAMSZ_1KB 0x00040000 |
| #define | EPI_HB16TIME3_PSRAMSZ_2KB 0x00050000 |
| #define | EPI_HB16TIME3_PSRAMSZ_4KB 0x00060000 |
| #define | EPI_HB16TIME3_PSRAMSZ_8KB 0x00070000 |
| #define | EPI_HB16TIME3_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB16TIME3_WRWSM 0x00000010 |
| #define | EPI_HB16TIME3_RDWSM 0x00000001 |
| #define | EPI_HB16TIME3_IRDYDLY_S 24 |
| #define | EPI_HB16TIME3_CAPWIDTH_S 12 |
| #define | EPI_HB8TIME3_IRDYDLY_M 0x03000000 |
| #define | EPI_HB8TIME3_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB8TIME3_WRWSM 0x00000010 |
| #define | EPI_HB8TIME3_RDWSM 0x00000001 |
| #define | EPI_HB8TIME3_IRDYDLY_S 24 |
| #define | EPI_HB8TIME3_CAPWIDTH_S 12 |
| #define | EPI_HB8TIME4_IRDYDLY_M 0x03000000 |
| #define | EPI_HB8TIME4_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB8TIME4_WRWSM 0x00000010 |
| #define | EPI_HB8TIME4_RDWSM 0x00000001 |
| #define | EPI_HB8TIME4_IRDYDLY_S 24 |
| #define | EPI_HB8TIME4_CAPWIDTH_S 12 |
| #define | EPI_HB16TIME4_IRDYDLY_M 0x03000000 |
| #define | EPI_HB16TIME4_PSRAMSZ_M 0x00070000 |
| #define | EPI_HB16TIME4_PSRAMSZ_0 0x00000000 |
| #define | EPI_HB16TIME4_PSRAMSZ_128B 0x00010000 |
| #define | EPI_HB16TIME4_PSRAMSZ_256B 0x00020000 |
| #define | EPI_HB16TIME4_PSRAMSZ_512B 0x00030000 |
| #define | EPI_HB16TIME4_PSRAMSZ_1KB 0x00040000 |
| #define | EPI_HB16TIME4_PSRAMSZ_2KB 0x00050000 |
| #define | EPI_HB16TIME4_PSRAMSZ_4KB 0x00060000 |
| #define | EPI_HB16TIME4_PSRAMSZ_8KB 0x00070000 |
| #define | EPI_HB16TIME4_CAPWIDTH_M 0x00003000 |
| #define | EPI_HB16TIME4_WRWSM 0x00000010 |
| #define | EPI_HB16TIME4_RDWSM 0x00000001 |
| #define | EPI_HB16TIME4_IRDYDLY_S 24 |
| #define | EPI_HB16TIME4_CAPWIDTH_S 12 |
| #define | EPI_HBPSRAM_CR_M 0x001FFFFF |
| #define | EPI_HBPSRAM_CR_S 0 |
| #define | EPI_FIFOLVL_WRFIFO_1_4 0x00000020 |
| #define | EPI_FIFOLVL_WRFIFO_1_2 0x00000030 |
| #define | EPI_FIFOLVL_WRFIFO_3_4 0x00000040 |
| #define | EPI_FIFOLVL_RDFIFO_1_8 0x00000001 |
| #define | EPI_FIFOLVL_RDFIFO_1_4 0x00000002 |
| #define | EPI_FIFOLVL_RDFIFO_1_2 0x00000003 |
| #define | EPI_FIFOLVL_RDFIFO_3_4 0x00000004 |
| #define | EPI_FIFOLVL_RDFIFO_7_8 0x00000005 |
| #define | EPI_FIFOLVL_RDFIFO_FULL 0x00000006 |
| #define EPI_GPCFG_FRMCNT_M 0x03C00000 |
Definition at line 178 of file hw_epi.h.
Referenced by EPIConfigGPModeSet().
| #define EPI_GPCFG_FRMCNT_S 22 |
Definition at line 193 of file hw_epi.h.
Referenced by EPIConfigGPModeSet().
| #define EPI_HB16CFG2_CSBAUD 0x04000000 |
Definition at line 285 of file hw_epi.h.
Referenced by EPIConfigHB16Set().
| #define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 |
Definition at line 151 of file hw_epi.h.
Referenced by EPIConfigHB16Set().
| #define EPI_HB16CFG_MAXWAIT_S 8 |
Definition at line 168 of file hw_epi.h.
Referenced by EPIConfigHB16Set().
| #define EPI_HB16CFG_RDCRE 0x00020000 |
Definition at line 148 of file hw_epi.h.
Referenced by EPIPSRAMConfigRegGet(), EPIPSRAMConfigRegGetNonBlocking(), and EPIPSRAMConfigRegRead().
| #define EPI_HB16CFG_WRCRE 0x00040000 |
Definition at line 146 of file hw_epi.h.
Referenced by EPIPSRAMConfigRegSet().
| #define EPI_HB8CFG2_CSBAUD 0x04000000 |
Definition at line 253 of file hw_epi.h.
Referenced by EPIConfigHB8Set().
| #define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 |
Definition at line 228 of file hw_epi.h.
Referenced by EPIConfigHB8Set().
| #define EPI_HB8CFG_MAXWAIT_S 8 |
Definition at line 244 of file hw_epi.h.
Referenced by EPIConfigHB8Set().
| #define EPI_O_ADDRMAP 0x0000001C |
Definition at line 59 of file hw_epi.h.
Referenced by EPIAddressMapSet().
| #define EPI_O_BAUD 0x00000004 |
Definition at line 50 of file hw_epi.h.
Referenced by EPIDividerCSSet(), and EPIDividerSet().
| #define EPI_O_BAUD2 0x00000008 |
Definition at line 51 of file hw_epi.h.
Referenced by EPIDividerCSSet().
| #define EPI_O_CFG 0x00000000 |
Definition at line 49 of file hw_epi.h.
Referenced by EPIModeSet().
| #define EPI_O_DMATXCNT 0x00000208 |
Definition at line 78 of file hw_epi.h.
Referenced by EPIDMATxCount().
| #define EPI_O_EISC 0x0000021C |
Definition at line 82 of file hw_epi.h.
Referenced by EPIIntErrorClear(), and EPIIntErrorStatus().
| #define EPI_O_FIFOLVL 0x00000200 |
Definition at line 76 of file hw_epi.h.
Referenced by EPIFIFOConfig().
| #define EPI_O_GPCFG 0x00000010 |
Definition at line 53 of file hw_epi.h.
Referenced by EPIConfigGPModeSet().
| #define EPI_O_HB16CFG 0x00000010 |
Definition at line 52 of file hw_epi.h.
Referenced by EPIConfigHB16CSSet(), EPIConfigHB16Set(), EPIPSRAMConfigRegGet(), EPIPSRAMConfigRegGetNonBlocking(), EPIPSRAMConfigRegRead(), and EPIPSRAMConfigRegSet().
| #define EPI_O_HB16CFG2 0x00000014 |
Definition at line 58 of file hw_epi.h.
Referenced by EPIConfigHB16Set().
| #define EPI_O_HB16CFG3 0x00000308 |
Definition at line 85 of file hw_epi.h.
Referenced by EPIConfigHB16CSSet(), EPIPSRAMConfigRegGet(), EPIPSRAMConfigRegGetNonBlocking(), EPIPSRAMConfigRegRead(), and EPIPSRAMConfigRegSet().
| #define EPI_O_HB16TIME 0x00000310 |
Definition at line 89 of file hw_epi.h.
Referenced by EPIConfigHB16TimingSet().
| #define EPI_O_HB8CFG 0x00000010 |
Definition at line 56 of file hw_epi.h.
Referenced by EPIConfigHB8CSSet(), and EPIConfigHB8Set().
| #define EPI_O_HB8CFG2 0x00000014 |
Definition at line 57 of file hw_epi.h.
Referenced by EPIConfigHB8Set().
| #define EPI_O_HB8CFG3 0x00000308 |
Definition at line 84 of file hw_epi.h.
Referenced by EPIConfigHB8CSSet().
| #define EPI_O_HB8TIME 0x00000310 |
Definition at line 88 of file hw_epi.h.
Referenced by EPIConfigHB8TimingSet().
| #define EPI_O_HBPSRAM 0x00000360 |
Definition at line 96 of file hw_epi.h.
Referenced by EPIPSRAMConfigRegGet(), EPIPSRAMConfigRegGetNonBlocking(), and EPIPSRAMConfigRegSet().
| #define EPI_O_IM 0x00000210 |
Definition at line 79 of file hw_epi.h.
Referenced by EPIIntDisable(), and EPIIntEnable().
| #define EPI_O_MIS 0x00000218 |
Definition at line 81 of file hw_epi.h.
Referenced by EPIIntStatus().
| #define EPI_O_RADDR0 0x00000024 |
Definition at line 61 of file hw_epi.h.
Referenced by EPINonBlockingReadConfigure().
| #define EPI_O_READFIFO0 0x00000070 |
Definition at line 68 of file hw_epi.h.
Referenced by EPINonBlockingReadGet16(), EPINonBlockingReadGet32(), and EPINonBlockingReadGet8().
| #define EPI_O_RFIFOCNT 0x0000006C |
Definition at line 67 of file hw_epi.h.
Referenced by EPINonBlockingReadAvail(), EPINonBlockingReadGet16(), EPINonBlockingReadGet32(), and EPINonBlockingReadGet8().
| #define EPI_O_RIS 0x00000214 |
Definition at line 80 of file hw_epi.h.
Referenced by EPIIntStatus().
| #define EPI_O_RPSTD0 0x00000028 |
Definition at line 62 of file hw_epi.h.
Referenced by EPINonBlockingReadCount(), EPINonBlockingReadStart(), and EPINonBlockingReadStop().
| #define EPI_O_RPSTD1 0x00000038 |
Definition at line 65 of file hw_epi.h.
Referenced by EPINonBlockingReadCount(), EPINonBlockingReadStart(), and EPINonBlockingReadStop().
| #define EPI_O_RSIZE0 0x00000020 |
Definition at line 60 of file hw_epi.h.
Referenced by EPINonBlockingReadConfigure().
| #define EPI_O_RSIZE1 0x00000030 |
Definition at line 63 of file hw_epi.h.
Referenced by EPINonBlockingReadConfigure().
| #define EPI_O_SDRAMCFG 0x00000010 |
Definition at line 55 of file hw_epi.h.
Referenced by EPIConfigSDRAMSet().
| #define EPI_O_WFIFOCNT 0x00000204 |
Definition at line 77 of file hw_epi.h.
Referenced by EPIWriteFIFOCountGet().
| #define EPI_SDRAMCFG_RFSH_M 0x07FF0000 |
Definition at line 204 of file hw_epi.h.
Referenced by EPIConfigSDRAMSet().
| #define EPI_SDRAMCFG_RFSH_S 16 |
Definition at line 211 of file hw_epi.h.
Referenced by EPIConfigSDRAMSet().
1.8.9.1 
