epi.c

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//*****************************************************************************
//
// epi.c - Driver for the EPI module.
//
// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************

#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_epi.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/epi.h"
#include "driverlib/interrupt.h"

//*****************************************************************************
//
//
//*****************************************************************************

//*****************************************************************************
//
// Helper masks for chip select configuration options.
//
//*****************************************************************************
#define EPI_HB8_CS_MASK         (EPI_HB8_MODE_FIFO | EPI_HB8_RDWAIT_3 |       \
                                 EPI_HB8_WRWAIT_3 | EPI_HB8_RDHIGH |          \
                                 EPI_HB8_WRHIGH | EPI_HB8_ALE_HIGH)

#define EPI_HB16_CS_MASK        (EPI_HB8_CS_MASK | EPI_HB16_BURST_TRAFFIC)

//*****************************************************************************
//
// Ensure that erratum workaround inline functions have a public version
// available in exactly one object module (this one).
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************
extern void EPIWorkaroundWordWrite(uint32_t *pui32Addr, uint32_t ui32Value);

//*****************************************************************************
//
//
//*****************************************************************************
extern uint32_t EPIWorkaroundWordRead(uint32_t *pui32Addr);

//*****************************************************************************
//
//
//*****************************************************************************
extern void EPIWorkaroundHWordWrite(uint16_t *pui16Addr, uint16_t ui16Value);

//*****************************************************************************
//
//
//*****************************************************************************
extern uint16_t EPIWorkaroundHWordRead(uint16_t *pui16Addr);

//*****************************************************************************
//
//
//*****************************************************************************
extern void EPIWorkaroundByteWrite(uint8_t *pui8Addr, uint8_t ui8Value);

//*****************************************************************************
//
//
//*****************************************************************************
extern uint8_t EPIWorkaroundByteRead(uint8_t *pui8Addr);

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIModeSet(uint32_t ui32Base, uint32_t ui32Mode)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT((ui32Mode == EPI_MODE_GENERAL) ||
           (ui32Mode == EPI_MODE_SDRAM) ||
           (ui32Mode == EPI_MODE_HB8) ||
           (ui32Mode == EPI_MODE_HB16) ||
           (ui32Mode == EPI_MODE_DISABLE));

    //
    // Write the mode word to the register.
    //
    HWREG(ui32Base + EPI_O_CFG) = ui32Mode;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIDividerSet(uint32_t ui32Base, uint32_t ui32Divider)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);

    //
    // Write the divider value to the register.
    //
    HWREG(ui32Base + EPI_O_BAUD) = ui32Divider;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIDividerCSSet(uint32_t ui32Base, uint32_t ui32CS,
                uint32_t ui32Divider)
{
    uint32_t ui32Reg;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Write the divider value to the register bitfield.
    //
    if(ui32CS < 2)
    {
        ui32Reg = HWREG(ui32Base + EPI_O_BAUD) & ~(0xffff << (16 * ui32CS));
        ui32Reg |= ((ui32Divider & 0xffff) << (16 * ui32CS));
        HWREG(ui32Base + EPI_O_BAUD) = ui32Reg;
    }
    else
    {
        ui32Reg = (HWREG(ui32Base + EPI_O_BAUD2) &
                   ~(0xffff << (16 * (ui32CS - 2))));
        ui32Reg |= ((ui32Divider & 0xffff) << (16 * (ui32CS - 2)));
        HWREG(ui32Base + EPI_O_BAUD2) = ui32Reg;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIDMATxCount(uint32_t ui32Base, uint32_t ui32Count)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Count <= 1024);

    //
    // Assign the DMA TX count value provided.
    //
    HWREG(ui32Base + EPI_O_DMATXCNT) = ui32Count & 0xffff;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigSDRAMSet(uint32_t ui32Base, uint32_t ui32Config,
                  uint32_t ui32Refresh)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Refresh < 2048);

    //
    // Fill in the refresh count field of the configuration word.
    //
    ui32Config &= ~EPI_SDRAMCFG_RFSH_M;
    ui32Config |= ui32Refresh << EPI_SDRAMCFG_RFSH_S;

    //
    // Write the SDRAM configuration register.
    //
    HWREG(ui32Base + EPI_O_SDRAMCFG) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigHB8Set(uint32_t ui32Base, uint32_t ui32Config,
                uint32_t ui32MaxWait)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32MaxWait < 256);

    //
    // Determine the CS and word access modes.
    //
    HWREG(ui32Base + EPI_O_HB8CFG2) =
        ((ui32Config & EPI_HB8_CSBAUD) ? EPI_HB8CFG2_CSBAUD : 0) |
        ((ui32Config & EPI_HB8_CSCFG_MASK) << 15);

    //
    // Fill in the max wait field of the configuration word.
    //
    ui32Config &= ~EPI_HB8CFG_MAXWAIT_M;
    ui32Config |= ui32MaxWait << EPI_HB8CFG_MAXWAIT_S;

    //
    // Write the main HostBus8 configuration register.
    //
    HWREG(ui32Base + EPI_O_HB8CFG) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigHB16Set(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32MaxWait)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32MaxWait < 256);

    //
    // Determine the CS and word access modes.
    //
    HWREG(ui32Base + EPI_O_HB16CFG2) =
        ((ui32Config & EPI_HB16_CSBAUD) ? EPI_HB16CFG2_CSBAUD : 0) |
        ((ui32Config & EPI_HB16_CSCFG_MASK) << 15);

    //
    // Fill in the max wait field of the configuration word.
    //
    ui32Config &= ~EPI_HB16CFG_MAXWAIT_M;
    ui32Config |= ui32MaxWait << EPI_HB16CFG_MAXWAIT_S;

    //
    // Write the main HostBus16 configuration register.
    //
    HWREG(ui32Base + EPI_O_HB16CFG) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigHB8CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
{
    uint32_t ui32Offset, ui32Reg;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Determine the register offset based on the ui32CS provided.
    //
    if(ui32CS < 2)
    {
        ui32Offset = EPI_O_HB8CFG + (ui32CS << 2);
    }
    else
    {
        ui32Offset = EPI_O_HB8CFG3 + ((ui32CS - 2) << 2);
    }

    //
    // Preserve the bits that will not be modified.
    //
    ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB8_CS_MASK;

    //
    // Write the target chip select HostBus8 configuration fields.
    //
    HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigHB16CSSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
{
    uint32_t ui32Offset, ui32Reg;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Determine the register offset based on the ui32CS provided.
    //
    if(ui32CS < 2)
    {
        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
    }
    else
    {
        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
    }

    //
    // Preserve the bits that will not be modified.
    //
    ui32Reg = HWREG(ui32Base + ui32Offset) & ~EPI_HB16_CS_MASK;

    //
    // Write the target chip select HostBus16 configuration fields.
    //
    HWREG(ui32Base + ui32Offset) = (ui32Reg | ui32Config);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigHB8TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Write the target chip select HostBus8 timing register.
    //
    HWREG(ui32Base + (EPI_O_HB8TIME + (ui32CS << 2))) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigHB16TimingSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32Config)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Write the target chip select HostBus16 timing register.
    //
    HWREG(ui32Base + (EPI_O_HB16TIME + (ui32CS << 2))) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIPSRAMConfigRegSet(uint32_t ui32Base, uint32_t ui32CS, uint32_t ui32CR)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Determine the register offset based on the ui32CS provided.
    //
    if(ui32CS < 2)
    {
        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
    }
    else
    {
        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
    }

    //
    // Setup for the PSRAM configuration register write.  Only 21 bits are
    // valid on a write.
    //
    HWREG(ui32Base + EPI_O_HBPSRAM) = (ui32CR & 0x1fffff);

    //
    // Set the PSRAM configuration register write enable.
    //
    HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_WRCRE;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Determine the register offset based on the ui32CS provided.
    //
    if(ui32CS < 2)
    {
        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
    }
    else
    {
        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
    }

    //
    // Set the PSRAM configuration register read enable.
    //
    HWREG(ui32Base + ui32Offset) |= EPI_HB16CFG_RDCRE;
}

//*****************************************************************************
//
//
//*****************************************************************************
bool
EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS,
                                uint32_t *pui32CR)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Determine the register offset based on the ui32CS provided.
    //
    if(ui32CS < 2)
    {
        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
    }
    else
    {
        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
    }

    //
    // Verify PSRAM read enable is not asserted.
    //
    if(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE)
    {
        return(false);
    }

    //
    // Copy the PSRAM configuration register value to the provided storage.
    // Only the lower 16 bits are valid on a read.
    //
    *pui32CR = HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff;

    //
    // Notify caller the provided storage holds the EPI PSRAM configuration
    // register contents.
    //
    return(true);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPIPSRAMConfigRegGet(uint32_t ui32Base, uint32_t ui32CS)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32CS < 4);

    //
    // Determine the register offset based on the ui32CS provided.
    //
    if(ui32CS < 2)
    {
        ui32Offset = EPI_O_HB16CFG + (ui32CS << 2);
    }
    else
    {
        ui32Offset = EPI_O_HB16CFG3 + ((ui32CS - 2) << 2);
    }

    //
    // Wait for PSRAM read enable to deassert if necessary.
    //
    while(HWREG(ui32Base + ui32Offset) & EPI_HB16CFG_RDCRE)
    {
    }

    //
    // Return the EPI PSRAM configuration register contents.
    // Only the lower 16 bits are valid on a read.
    //
    return(HWREG(ui32Base + EPI_O_HBPSRAM) & 0xffff);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIConfigGPModeSet(uint32_t ui32Base, uint32_t ui32Config,
                   uint32_t ui32FrameCount, uint32_t ui32MaxWait)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32FrameCount < 16);
    ASSERT(ui32MaxWait < 256);

    //
    // Fill in the frame count field of the configuration word.
    //
    ui32Config &= ~EPI_GPCFG_FRMCNT_M;
    ui32Config |= ui32FrameCount << EPI_GPCFG_FRMCNT_S;

    //
    // Write the non-moded configuration register.
    //
    HWREG(ui32Base + EPI_O_GPCFG) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIAddressMapSet(uint32_t ui32Base, uint32_t ui32Map)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Map < 0x1000);

    //
    // Set the value of the address mapping register.
    //
    HWREG(ui32Base + EPI_O_ADDRMAP) = ui32Map;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPINonBlockingReadConfigure(uint32_t ui32Base, uint32_t ui32Channel,
                            uint32_t ui32DataSize, uint32_t ui32Address)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Channel < 2);
    ASSERT(ui32DataSize < 4);
    ASSERT(ui32Address < 0x20000000);

    //
    // Compute the offset needed to select the correct channel regs.
    //
    ui32Offset = ui32Channel * (EPI_O_RSIZE1 - EPI_O_RSIZE0);

    //
    // Write the data size register for the channel.
    //
    HWREG(ui32Base + EPI_O_RSIZE0 + ui32Offset) = ui32DataSize;

    //
    // Write the starting address register for the channel.
    //
    HWREG(ui32Base + EPI_O_RADDR0 + ui32Offset) = ui32Address;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPINonBlockingReadStart(uint32_t ui32Base, uint32_t ui32Channel,
                        uint32_t ui32Count)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Channel < 2);
    ASSERT(ui32Count < 4096);

    //
    // Compute the offset needed to select the correct channel regs.
    //
    ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);

    //
    // Write to the read count register.
    //
    HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = ui32Count;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPINonBlockingReadStop(uint32_t ui32Base, uint32_t ui32Channel)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Channel < 2);

    //
    // Compute the offset needed to select the correct channel regs.
    //
    ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);

    //
    // Write a 0 to the read count register, which cancels the transaction.
    //
    HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset) = 0;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPINonBlockingReadCount(uint32_t ui32Base, uint32_t ui32Channel)
{
    uint32_t ui32Offset;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Channel < 2);

    //
    // Compute the offset needed to select the correct channel regs.
    //
    ui32Offset = ui32Channel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);

    //
    // Read the count remaining and return the value to the caller.
    //
    return(HWREG(ui32Base + EPI_O_RPSTD0 + ui32Offset));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPINonBlockingReadAvail(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);

    //
    // Read the FIFO count and return it to the caller.
    //
    return(HWREG(ui32Base + EPI_O_RFIFOCNT));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPINonBlockingReadGet32(uint32_t ui32Base, uint32_t ui32Count,
                        uint32_t *pui32Buf)
{
    uint32_t ui32CountRead = 0;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Count < 4096);
    ASSERT(pui32Buf);

    //
    // Read from the FIFO while there are any items to read and
    // the caller's specified count is not exceeded.
    //
    while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--)
    {
        //
        // Read from the FIFO and store in the caller supplied buffer.
        //
        *pui32Buf = HWREG(ui32Base + EPI_O_READFIFO0);

        //
        // Update the caller's buffer pointer and the count of items read.
        //
        pui32Buf++;
        ui32CountRead++;
    }

    //
    // Return the count of items read to the caller.
    //
    return(ui32CountRead);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPINonBlockingReadGet16(uint32_t ui32Base, uint32_t ui32Count,
                        uint16_t *pui16Buf)
{
    uint32_t ui32CountRead = 0;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Count < 4096);
    ASSERT(pui16Buf);

    //
    // Read from the FIFO while there are any items to read, and
    // the caller's specified count is not exceeded.
    //
    while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--)
    {
        //
        // Read from the FIFO and store in the caller-supplied buffer.
        //
        *pui16Buf = (uint16_t)HWREG(ui32Base + EPI_O_READFIFO0);

        //
        // Update the caller's buffer pointer and the count of items read.
        //
        pui16Buf++;
        ui32CountRead++;
    }

    //
    // Return the count of items read to the caller.
    //
    return(ui32CountRead);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPINonBlockingReadGet8(uint32_t ui32Base, uint32_t ui32Count,
                       uint8_t *pui8Buf)
{
    uint32_t ui32CountRead = 0;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Count < 4096);
    ASSERT(pui8Buf);

    //
    // Read from the FIFO while there are any items to read, and
    // the caller's specified count is not exceeded.
    //
    while(HWREG(ui32Base + EPI_O_RFIFOCNT) && ui32Count--)
    {
        //
        // Read from the FIFO and store in the caller supplied buffer.
        //
        *pui8Buf = (uint8_t)HWREG(ui32Base + EPI_O_READFIFO0);

        //
        // Update the caller's buffer pointer and the count of items read.
        //
        pui8Buf++;
        ui32CountRead++;
    }

    //
    // Return the count of items read to the caller.
    //
    return(ui32CountRead);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIFIFOConfig(uint32_t ui32Base, uint32_t ui32Config)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32Config == (ui32Config & 0x00030077));

    //
    // Load the configuration into the FIFO config reg.
    //
    HWREG(ui32Base + EPI_O_FIFOLVL) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPIWriteFIFOCountGet(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);

    //
    // Read the FIFO count and return it to the caller.
    //
    return(HWREG(ui32Base + EPI_O_WFIFOCNT));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32IntFlags < 17);

    //
    // Write the interrupt flags mask to the mask register.
    //
    HWREG(ui32Base + EPI_O_IM) |= ui32IntFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32IntFlags < 17);

    //
    // Write the interrupt flags mask to the mask register.
    //
    HWREG(ui32Base + EPI_O_IM) &= ~ui32IntFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPIIntStatus(uint32_t ui32Base, bool bMasked)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);

    //
    // Return either the interrupt status or the raw interrupt status as
    // requested.
    //
    if(bMasked)
    {
        return(HWREG(ui32Base + EPI_O_MIS));
    }
    else
    {
        return(HWREG(ui32Base + EPI_O_RIS));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EPIIntErrorStatus(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);

    //
    // Read the error status and return to caller.
    //
    return(HWREG(ui32Base + EPI_O_EISC));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIIntErrorClear(uint32_t ui32Base, uint32_t ui32ErrFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(ui32ErrFlags < 0x20);

    //
    // Write the error flags to the register to clear the pending errors.
    //
    HWREG(ui32Base + EPI_O_EISC) = ui32ErrFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
static uint32_t
_EPIIntNumberGet(uint32_t ui32Base)
{
    uint32_t ui32Int;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);

    //
    // By default, assume EPI is not supported.
    //
    ui32Int = 0;

    if(CLASS_IS_TM4C129)
    {
        ui32Int = INT_EPI0_TM4C129;
    }

    return(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
{
    uint32_t ui32Int;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);
    ASSERT(pfnHandler);

    //
    // Get the interrupt number for the EPI interface.
    //
    ui32Int = _EPIIntNumberGet(ui32Base);

    ASSERT(ui32Int != 0);

    //
    // Register the interrupt handler.
    //
    IntRegister(ui32Int, pfnHandler);

    //
    // Enable the EPI interface interrupt.
    //
    IntEnable(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EPIIntUnregister(uint32_t ui32Base)
{
    uint32_t ui32Int;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == EPI0_BASE);

    //
    // Get the interrupt number for the EPI interface.
    //
    ui32Int = _EPIIntNumberGet(ui32Base);

    ASSERT(ui32Int != 0);

    //
    // Disable the EPI interface interrupt.
    //
    IntDisable(ui32Int);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(ui32Int);
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************