40 #ifndef __DRIVERLIB_USB_H__
41 #define __DRIVERLIB_USB_H__
61 #define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources
62 #define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts
63 #define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error
64 #define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected
65 #define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected
66 #define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected
67 #define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected
68 #define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected
69 #define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled
70 #define USB_INTCTRL_RESET 0x00000004 // Reset signaled
71 #define USB_INTCTRL_RESUME 0x00000002 // Resume detected
72 #define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected
73 #define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid
74 #define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected
83 #define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts
84 #define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts
85 #define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt
86 #define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt
87 #define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt
88 #define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt
89 #define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt
90 #define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt
91 #define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt
92 #define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt
93 #define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt
94 #define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt
95 #define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt
96 #define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt
97 #define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt
98 #define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt
99 #define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt
101 #define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts
102 #define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt
103 #define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt
104 #define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt
105 #define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt
106 #define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt
107 #define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt
108 #define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt
109 #define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt
110 #define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt
111 #define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt
112 #define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt
113 #define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt
114 #define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt
115 #define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt
116 #define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt
118 #define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts
119 #define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt
120 #define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt
121 #define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt
122 #define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt
123 #define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt
124 #define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt
125 #define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt
126 #define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt
127 #define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt
128 #define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt
129 #define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt
130 #define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt
131 #define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt
132 #define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt
133 #define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt
135 #define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts
136 #define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt
137 #define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt
138 #define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt
139 #define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt
140 #define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt
141 #define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt
142 #define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt
143 #define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt
144 #define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt
145 #define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt
146 #define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt
147 #define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt
148 #define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt
149 #define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt
150 #define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt
152 #define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt
159 #define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined
160 #define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed
161 #define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed
162 #define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed
171 #define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts
172 #define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received
173 #define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond
174 #define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
175 #define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error
177 #define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the
179 #define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a
181 #define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
182 #define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
183 #define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts
184 #define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
186 #define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
188 #define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received
189 #define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a
191 #define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty
192 #define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted
193 #define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the
195 #define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet
196 #define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a
198 #define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received
199 #define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready
200 #define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous
202 #define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint
203 #define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data
204 #define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to
206 #define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full
207 #define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready
208 #define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data
210 #define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint
211 #define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready
212 #define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty
213 #define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted
214 #define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before
216 #define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint
217 #define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending
218 #define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready
226 #define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled
227 #define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled
228 #define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled
229 #define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0
230 #define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1
231 #define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for
234 #define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint
235 #define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint
236 #define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint
237 #define USB_EP_MODE_CTRL 0x00000300 // Control endpoint
238 #define USB_EP_MODE_MASK 0x00000300 // Mode Mask
239 #define USB_EP_SPEED_LOW 0x00000000 // Low Speed
240 #define USB_EP_SPEED_FULL 0x00001000 // Full Speed
241 #define USB_EP_SPEED_HIGH 0x00004000 // High Speed
242 #define USB_EP_HOST_IN 0x00000000 // Host IN endpoint
243 #define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint
244 #define USB_EP_DEV_IN 0x00002000 // Device IN endpoint
245 #define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint
253 #define USB_HOST_PWRFLT_LOW 0x00000010
254 #define USB_HOST_PWRFLT_HIGH 0x00000030
255 #define USB_HOST_PWRFLT_EP_NONE 0x00000000
256 #define USB_HOST_PWRFLT_EP_TRI 0x00000140
257 #define USB_HOST_PWRFLT_EP_LOW 0x00000240
258 #define USB_HOST_PWRFLT_EP_HIGH 0x00000340
259 #define USB_HOST_PWREN_MAN_LOW 0x00000000
260 #define USB_HOST_PWREN_MAN_HIGH 0x00000001
261 #define USB_HOST_PWREN_AUTOLOW 0x00000002
262 #define USB_HOST_PWREN_AUTOHIGH 0x00000003
263 #define USB_HOST_PWREN_FILTER 0x00010000
271 #define USB_HOST_LPM_RMTWAKE 0x00000100
272 #define USB_HOST_LPM_L1 0x00000001
280 #define USB_DEV_LPM_NAK 0x00000010
281 #define USB_DEV_LPM_NONE 0x00000000
282 #define USB_DEV_LPM_EN 0x0000000c
283 #define USB_DEV_LPM_EXTONLY 0x00000004
291 #define USB_DEV_LPM_LS_RMTWAKE 0x00000100
292 #define USB_DEV_LPM_LS_L1 0x00000001
301 #define USB_INTLPM_ERROR 0x00000020
302 #define USB_INTLPM_RESUME 0x00000010
303 #define USB_INTLPM_INCOMPLETE 0x00000008
304 #define USB_INTLPM_ACK 0x00000004
305 #define USB_INTLPM_NYET 0x00000002
306 #define USB_INTLPM_STALL 0x00000001
314 #define USB_CLOCK_INTERNAL 0x00000200
315 #define USB_CLOCK_EXTERNAL 0x00000300
322 #define USB_ULPI_EXTVBUS 0x00000001
323 #define USB_ULPI_EXTVBUS_IND 0x00000002
331 #define MAX_NAK_LIMIT 31 // Maximum NAK interval
332 #define DISABLE_NAK_LIMIT 0 // No NAK timeouts
340 #define MAX_PACKET_SIZE_EP0 64
347 #define USB_EP_0 0x00000000 // Endpoint 0
348 #define USB_EP_1 0x00000010 // Endpoint 1
349 #define USB_EP_2 0x00000020 // Endpoint 2
350 #define USB_EP_3 0x00000030 // Endpoint 3
351 #define USB_EP_4 0x00000040 // Endpoint 4
352 #define USB_EP_5 0x00000050 // Endpoint 5
353 #define USB_EP_6 0x00000060 // Endpoint 6
354 #define USB_EP_7 0x00000070 // Endpoint 7
355 #define NUM_USB_EP 8 // Number of supported endpoints
363 #define IndexToUSBEP(x) ((x) << 4)
364 #define USBEPToIndex(x) ((x) >> 4)
372 #define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO
373 #define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO
374 #define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO
375 #define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO
376 #define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO
377 #define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO
378 #define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO
379 #define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO
380 #define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO
388 #define USBFIFOSizeToBytes(x) (8 << (x))
396 #define USB_TRANS_OUT 0x00000102 // Normal OUT transaction
397 #define USB_TRANS_IN 0x00000102 // Normal IN transaction
398 #define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for
400 #define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint
402 #define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint
410 #define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host
412 #define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in
414 #define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not
416 #define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of
418 #define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of
420 #define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of
422 #define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of
424 #define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of
426 #define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of
428 #define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of
430 #define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of
432 #define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set.
440 #define USB_DMA_INT_CH8 0x00000080
441 #define USB_DMA_INT_CH7 0x00000040
442 #define USB_DMA_INT_CH6 0x00000020
443 #define USB_DMA_INT_CH5 0x00000010
444 #define USB_DMA_INT_CH4 0x00000008
445 #define USB_DMA_INT_CH3 0x00000004
446 #define USB_DMA_INT_CH2 0x00000002
447 #define USB_DMA_INT_CH1 0x00000001
454 #define USB_DMA_STATUS_ERROR 0x00000100
461 #define USB_CONTROLLER_VER_0 0x00000000 // This is for Blizzard class
463 #define USB_CONTROLLER_VER_1 0x00000001 // This is for Snowflake class
472 #define USB_DMA_CFG_BURST_NONE 0x00000000
473 #define USB_DMA_CFG_BURST_4 0x00000200
474 #define USB_DMA_CFG_BURST_8 0x00000400
475 #define USB_DMA_CFG_BURST_16 0x00000600
476 #define USB_DMA_CFG_INT_EN 0x00000008
477 #define USB_DMA_CFG_MODE_0 0x00000000
478 #define USB_DMA_CFG_MODE_1 0x00000004
479 #define USB_DMA_CFG_DIR_RX 0x00000000
480 #define USB_DMA_CFG_DIR_TX 0x00000002
481 #define USB_DMA_CFG_EN 0x00000001
489 #define USB_MODE_HOST_VBUS 0x00000004
490 #define USB_MODE_HOST 0x00000002
491 #define USB_MODE_DEV_VBUS 0x00000005
492 #define USB_MODE_DEV 0x00000003
493 #define USB_MODE_OTG 0x00000000
501 extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address);
505 uint32_t ui32MaxPacketSize,
508 uint32_t *pui32MaxPacketSize,
509 uint32_t *pui32Flags);
524 uint32_t ui32Config);
526 uint8_t *pui8Data, uint32_t *pui32Size);
528 uint8_t *pui8Data, uint32_t ui32Size);
530 uint32_t ui32TransType);
532 uint32_t ui32Endpoint,
537 extern uint32_t
USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint);
539 uint32_t *pui32FIFOAddress,
540 uint32_t *pui32FIFOSize, uint32_t ui32Flags);
542 uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize,
544 extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint,
547 extern uint32_t
USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint,
549 extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint,
550 uint32_t ui32Addr, uint32_t ui32Flags);
552 uint32_t ui32MaxPacketSize,
553 uint32_t ui32NAKPollInterval,
554 uint32_t ui32TargetEndpoint,
557 uint32_t ui32Endpoint);
559 bool bDataToggle, uint32_t ui32Flags);
561 uint32_t ui32Endpoint,
566 uint32_t ui32Addr, uint32_t ui32Flags);
575 extern void USBHostReset(uint32_t ui32Base,
bool bStart);
585 extern void USBIntRegister(uint32_t ui32Base,
void (*pfnHandler)(
void));
588 extern uint32_t
USBModeGet(uint32_t ui32Base);
590 uint32_t ui32Channel);
594 uint32_t ui32Endpoint, uint32_t ui32Config);
599 uint32_t ui32Channel);
603 uint32_t ui32Channel, uint32_t ui32Flags);
610 uint32_t ui32Status);
615 extern void USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address,
616 uint32_t uiEndpoint);
618 uint32_t ui32Config);
630 extern void USBHighSpeed(uint32_t ui32Base,
bool bEnable);
635 extern void USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config);
644 extern void USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode);
658 #endif // __DRIVERLIB_USB_H__
void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode)
int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, uint8_t *pui8Data, uint32_t ui32Size)
void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags)
void USBPHYPowerOn(uint32_t ui32Base)
void USBDevLPMEnable(uint32_t ui32Base)
void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, uint32_t ui32Flags)
void USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint)
uint32_t USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel)
void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void * USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel)
uint32_t USBModeGet(uint32_t ui32Base)
void USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel)
void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags)
uint32_t USBDevSpeedGet(uint32_t ui32Base)
void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Channel)
void USBHostRequestStatus(uint32_t ui32Base)
void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, bool bDataToggle, uint32_t ui32Flags)
void USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint)
void USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel, void *pvAddress)
uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint)
void USBHostPwrEnable(uint32_t ui32Base)
uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint)
void USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel)
void USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel, uint32_t ui32Status)
void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags)
void USBDevMode(uint32_t ui32Base)
void USBHostPwrFaultDisable(uint32_t ui32Base)
void USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config)
uint32_t USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel)
void USBDMAChannelAssign(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Channel, uint32_t ui32Flags)
void USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, uint32_t uiEndpoint)
uint32_t USBFrameNumberGet(uint32_t ui32Base)
void USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints)
void USBHostSuspend(uint32_t ui32Base)
void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint8_t *pui8Data, uint32_t *pui32Size)
void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Count)
void USBDevConnect(uint32_t ui32Base)
void USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, uint8_t ui8Data)
void USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, uint32_t ui32Flags)
void USBHostMode(uint32_t ui32Base)
void USBHostPwrDisable(uint32_t ui32Base)
void USBDevLPMRemoteWake(uint32_t ui32Base)
void USBHostResume(uint32_t ui32Base, bool bStart)
void USBULPIEnable(uint32_t ui32Base)
void USBOTGMode(uint32_t ui32Base)
void USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags)
uint32_t USBHostSpeedGet(uint32_t ui32Base)
void USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, bool bEnable)
void USBHighSpeed(uint32_t ui32Base, bool bEnable)
uint32_t USBLPMIntStatus(uint32_t ui32Base)
void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBIntUnregister(uint32_t ui32Base)
bool USBLPMRemoteWakeEnabled(uint32_t ui32Base)
void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, bool bIsLastPacket)
void USBClockDisable(uint32_t ui32Base)
uint32_t USBNumEndpointsGet(uint32_t ui32Base)
void USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints)
void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config)
void USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel)
void USBHostPwrFaultEnable(uint32_t ui32Base)
void USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Count, uint32_t ui32Channel)
uint32_t USBDMANumChannels(uint32_t ui32Base)
uint8_t USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg)
void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, uint32_t ui32Flags)
uint32_t USBLPMEndpointGet(uint32_t ui32Base)
void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32MaxPacketSize, uint32_t ui32Flags)
void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags)
void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags)
uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBHostReset(uint32_t ui32Base, bool bStart)
uint32_t USBIntStatusEndpoint(uint32_t ui32Base)
void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint)
int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32TransType)
void USBOTGSessionRequest(uint32_t ui32Base, bool bStart)
uint32_t USBLPMLinkStateGet(uint32_t ui32Base)
void USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel)
uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBHostLPMResume(uint32_t ui32Base)
void USBDevLPMDisable(uint32_t ui32Base)
void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint)
void USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime, uint32_t ui32Config)
uint32_t USBDevAddrGet(uint32_t ui32Base)
void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, uint32_t ui32Flags)
void USBULPIDisable(uint32_t ui32Base)
uint32_t USBControllerVersion(uint32_t ui32Base)
void USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel, uint32_t ui32Endpoint, uint32_t ui32Config)
void USBIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
void USBDevDisconnect(uint32_t ui32Base)
void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, uint32_t ui32Flags)
void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address)
uint32_t USBIntStatusControl(uint32_t ui32Base)
void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32MaxPacketSize, uint32_t ui32NAKPollInterval, uint32_t ui32TargetEndpoint, uint32_t ui32Flags)
void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Config)
void USBPHYPowerOff(uint32_t ui32Base)
uint32_t USBDMAChannelIntStatus(uint32_t ui32Base)