usb.c

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//*****************************************************************************
//
// usb.c - Driver for the USB Interface.
//
// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************

#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_usb.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/sysctl.h"
#include "driverlib/udma.h"
#include "driverlib/usb.h"

//*****************************************************************************
//
// Amount to shift the RX interrupt sources by in the flags used in the
// interrupt calls.
//
//*****************************************************************************
#define USB_INTEP_RX_SHIFT      16

//*****************************************************************************
//
// Amount to shift the RX endpoint status sources by in the flags used in the
// calls.
//
//*****************************************************************************
#define USB_RX_EPSTATUS_SHIFT   16

//*****************************************************************************
//
// Converts from an endpoint specifier to the offset of the endpoint's
// control/status registers.
//
//*****************************************************************************
#define EP_OFFSET(Endpoint)     (Endpoint - 0x10)

//*****************************************************************************
//
// Sets one of the indexed registers.
//
// \param ui32Base specifies the USB module base address.
// \param ui32Endpoint is the endpoint index to target for this write.
// \param ui32IndexedReg is the indexed register to write to.
// \param ui8Value is the value to write to the register.
//
// This function is used to access the indexed registers for each endpoint.
// The only registers that are indexed are the FIFO configuration registers,
// which are not used after configuration.
//
// \return None.
//
//*****************************************************************************
static void
_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint,
               uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size)
{
    uint32_t ui32Index;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) ||
           (ui32Endpoint == 3));
    ASSERT((ui32Size == 1) || (ui32Size == 2));

    //
    // Save the old index in case it was in use.
    //
    ui32Index = HWREGB(ui32Base + USB_O_EPIDX);

    //
    // Set the index.
    //
    HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint;

    //
    // Determine the size of the register value.
    //
    if(ui32Size == 1)
    {
        //
        // Set the value.
        //
        HWREGB(ui32Base + ui32IndexedReg) = ui32Value;
    }
    else
    {
        //
        // Set the value.
        //
        HWREGH(ui32Base + ui32IndexedReg) = ui32Value;
    }

    //
    // Restore the old index in case it was in use.
    //
    HWREGB(ui32Base + USB_O_EPIDX) = ui32Index;
}

//*****************************************************************************
//
// Reads one of the indexed registers.
//
// \param ui32Base specifies the USB module base address.
// \param ui32Endpoint is the endpoint index to target for this write.
// \param ui32IndexedReg is the indexed register to write to.
//
// This function is used internally to access the indexed registers for each
// endpoint.  The only registers that are indexed are the FIFO configuration
// registers, which are not used after configuration.
//
// \return The value in the register requested.
//
//*****************************************************************************
static uint32_t
_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint,
              uint32_t ui32IndexedReg, uint32_t ui32Size)
{
    uint8_t ui8Index;
    uint8_t ui8Value;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) ||
           (ui32Endpoint == 3));
    ASSERT((ui32Size == 1) || (ui32Size == 2));

    //
    // Save the old index in case it was in use.
    //
    ui8Index = HWREGB(ui32Base + USB_O_EPIDX);

    //
    // Set the index.
    //
    HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint;

    //
    // Determine the size of the register value.
    //
    if(ui32Size == 1)
    {
        //
        // Get the value.
        //
        ui8Value = HWREGB(ui32Base + ui32IndexedReg);
    }
    else
    {
        //
        // Get the value.
        //
        ui8Value = HWREGH(ui32Base + ui32IndexedReg);
    }

    //
    // Restore the old index in case it was in use.
    //
    HWREGB(ui32Base + USB_O_EPIDX) = ui8Index;

    //
    // Return the register's value.
    //
    return(ui8Value);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostSuspend(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Send the suspend signaling to the USB bus.
    //
    HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostReset(uint32_t ui32Base, bool bStart)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Send a reset signal to the bus.
    //
    if(bStart)
    {
        HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET;
    }
    else
    {
        HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHighSpeed(uint32_t ui32Base, bool bEnable)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    if(bEnable)
    {
        //
        // Enable high speed mode negotiations in hosts or device mode.
        //
        HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_HSENAB;
    }
    else
    {
        //
        // Enable high speed mode negotiations in hosts or device mode.
        //
        HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_HSENAB;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostResume(uint32_t ui32Base, bool bStart)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Send a resume signal to the bus.
    //
    if(bStart)
    {
        HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME;
    }
    else
    {
        HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBHostSpeedGet(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // If the Full Speed device bit is set, then this is a full speed device.
    //
    if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE)
    {
        return(USB_HIGH_SPEED);
    }

    //
    // If the Full Speed device bit is set, then this is a full speed device.
    //
    if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV)
    {
        return(USB_FULL_SPEED);
    }

    //
    // If the Low Speed device bit is set, then this is a low speed device.
    //
    if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV)
    {
        return(USB_LOW_SPEED);
    }

    //
    // The device speed is not known.
    //
    return(USB_UNDEF_SPEED);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBDevSpeedGet(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // If the Full Speed device bit is set, then this is a full speed device.
    //
    if(HWREGB(ui32Base + USB_O_POWER) & USB_POWER_HSMODE)
    {
        return(USB_HIGH_SPEED);
    }

    return(USB_FULL_SPEED);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0);

    //
    // If any general interrupts were disabled then write the general interrupt
    // settings out to the hardware.
    //
    if(ui32Flags & USB_INTCTRL_STATUS)
    {
        HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS);
    }

    //
    // Disable the power fault interrupt.
    //
    if(ui32Flags & USB_INTCTRL_POWER_FAULT)
    {
        HWREG(ui32Base + USB_O_EPCIM) = 0;
    }

    //
    // Disable the ID pin detect interrupt.
    //
    if(ui32Flags & USB_INTCTRL_MODE_DETECT)
    {
        HWREG(USB0_BASE + USB_O_IDVIM) = 0;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0);

    //
    // If any general interrupts were enabled, then write the general
    // interrupt settings out to the hardware.
    //
    if(ui32Flags & USB_INTCTRL_STATUS)
    {
        HWREGB(ui32Base + USB_O_IE) |= ui32Flags;
    }

    //
    // Enable the power fault interrupt.
    //
    if(ui32Flags & USB_INTCTRL_POWER_FAULT)
    {
        HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF;
    }

    //
    // Enable the ID pin detect interrupt.
    //
    if(ui32Flags & USB_INTCTRL_MODE_DETECT)
    {
        HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBIntStatusControl(uint32_t ui32Base)
{
    uint32_t ui32Status;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Get the general interrupt status, these bits go into the upper 8 bits
    // of the returned value.
    //
    ui32Status = HWREGB(ui32Base + USB_O_IS);

    //
    // Add the power fault status.
    //
    if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF)
    {
        //
        // Indicate a power fault was detected.
        //
        ui32Status |= USB_INTCTRL_POWER_FAULT;

        //
        // Clear the power fault interrupt.
        //
        HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF;
    }

    if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
    {
        //
        // Indicate an id detection.
        //
        ui32Status |= USB_INTCTRL_MODE_DETECT;

        //
        // Clear the id detection interrupt.
        //
        HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
    }

    //
    // Return the combined interrupt status.
    //
    return(ui32Status);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // If any transmit interrupts were disabled, then write the transmit
    // interrupt settings out to the hardware.
    //
    HWREGH(ui32Base + USB_O_TXIE) &=
        ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));

    //
    // If any receive interrupts were disabled, then write the receive
    // interrupt settings out to the hardware.
    //
    HWREGH(ui32Base + USB_O_RXIE) &=
        ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
          USB_INTEP_RX_SHIFT);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Enable any transmit endpoint interrupts.
    //
    HWREGH(ui32Base + USB_O_TXIE) |=
        ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);

    //
    // Enable any receive endpoint interrupts.
    //
    HWREGH(ui32Base + USB_O_RXIE) |=
        ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
         USB_INTEP_RX_SHIFT);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBIntStatusEndpoint(uint32_t ui32Base)
{
    uint32_t ui32Status;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Get the transmit interrupt status.
    //
    ui32Status = HWREGH(ui32Base + USB_O_TXIS);
    ui32Status |= (HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT);

    //
    // Return the combined interrupt status.
    //
    return(ui32Status);
}

//*****************************************************************************
//
//
//*****************************************************************************
static uint32_t
_USBIntNumberGet(uint32_t ui32Base)
{
    uint32_t ui32Int;

    if(CLASS_IS_TM4C123)
    {
        ui32Int = INT_USB0_TM4C123;
    }
    else if(CLASS_IS_TM4C129)
    {
        ui32Int = INT_USB0_TM4C129;
    }
    else
    {
        ui32Int = 0;
    }
    return(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
{
    uint32_t ui32Int;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    ui32Int = _USBIntNumberGet(ui32Base);

    ASSERT(ui32Int != 0);

    //
    // Register the interrupt handler.
    //
    IntRegister(ui32Int, pfnHandler);

    //
    // Enable the USB interrupt.
    //
    IntEnable(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBIntUnregister(uint32_t ui32Base)
{
    uint32_t ui32Int;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    ui32Int = _USBIntNumberGet(ui32Base);

    ASSERT(ui32Int != 0);

    //
    // Disable the USB interrupt.
    //
    IntDisable(ui32Int);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint)
{
    uint32_t ui32Status;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Get the TX portion of the endpoint status.
    //
    ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1);

    //
    // Get the RX portion of the endpoint status.
    //
    ui32Status |=
        ((HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) <<
         USB_RX_EPSTATUS_SHIFT);

    //
    // Return the endpoint status.
    //
    return(ui32Status);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
                           uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Clear the specified flags for the endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags;
    }
    else
    {
        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~ui32Flags;
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
                          uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // If this is endpoint 0, then the bits have different meaning and map
    // into the TX memory location.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Set the Serviced RxPktRdy bit to clear the RxPktRdy.
        //
        if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY)
        {
            HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC;
        }

        //
        // Set the serviced Setup End bit to clear the SetupEnd status.
        //
        if(ui32Flags & USB_DEV_EP0_SETUP_END)
        {
            HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC;
        }

        //
        // Clear the Sent Stall status flag.
        //
        if(ui32Flags & USB_DEV_EP0_SENT_STALL)
        {
            HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL);
        }
    }
    else
    {
        //
        // Clear out any TX flags that were passed in.  Only
        // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared.
        //
        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));

        //
        // Clear out valid RX flags that were passed in.  Only
        // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN
        // must be cleared.
        //
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR |
                            USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint,
                          bool bDataToggle, uint32_t ui32Flags)
{
    uint32_t ui32DataToggle;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // The data toggle defaults to DATA0.
    //
    ui32DataToggle = 0;

    //
    // See if the data toggle must be set to DATA1.
    //
    if(bDataToggle)
    {
        //
        // Select the data toggle bit based on the endpoint.
        //
        if(ui32Endpoint == USB_EP_0)
        {
            ui32DataToggle = USB_CSRH0_DT;
        }
        else if(ui32Flags == USB_EP_HOST_IN)
        {
            ui32DataToggle = USB_RXCSRH1_DT;
        }
        else
        {
            ui32DataToggle = USB_TXCSRH1_DT;
        }
    }

    //
    // Set the data toggle based on the endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Set the write enable and the bit value for endpoint zero.
        //
        HWREGB(ui32Base + USB_O_CSRH0) =
            ((HWREGB(ui32Base + USB_O_CSRH0) &
              ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
             (ui32DataToggle | USB_CSRH0_DTWE));
    }
    else if(ui32Flags == USB_EP_HOST_IN)
    {
        //
        // Set the Write enable and the bit value for an IN endpoint.
        //
        HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) =
            ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) &
              ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
             (ui32DataToggle | USB_RXCSRH1_DTWE));
    }
    else
    {
        //
        // Set the Write enable and the bit value for an OUT endpoint.
        //
        HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) =
            ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) &
              ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
             (ui32DataToggle | USB_TXCSRH1_DTWE));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint,
                           uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
           (ui32Endpoint == USB_EP_7));

    //
    // See if the transmit or receive data toggle must be cleared.
    //
    if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
    {
        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
            USB_TXCSRL1_CLRDT;
    }
    else
    {
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
            USB_RXCSRL1_CLRDT;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostEndpointPing(uint32_t ui32Base, uint32_t ui32Endpoint, bool bEnable)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0));

    //
    // Handle the endpoint 0 case separately.
    //
    if(bEnable)
    {
        HWREGB(USB0_BASE + USB_O_CSRH0) &= ~USB_CSRH0_DISPING;
    }
    else
    {
        HWREGB(USB0_BASE + USB_O_CSRH0) |= USB_CSRH0_DISPING;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint,
                    uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Determine how to stall this endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Perform a stall on endpoint zero.
        //
        HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC;
    }
    else if(ui32Flags == USB_EP_DEV_IN)
    {
        //
        // Perform a stall on an IN endpoint.
        //
        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
            USB_TXCSRL1_STALL;
    }
    else
    {
        //
        // Perform a stall on an OUT endpoint.
        //
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
            USB_RXCSRL1_STALL;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint,
                         uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
    ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0);

    //
    // Determine how to clear the stall on this endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Clear the stall on endpoint zero.
        //
        HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED;
    }
    else if(ui32Flags == USB_EP_DEV_IN)
    {
        //
        // Clear the stall on an IN endpoint.
        //
        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);

        //
        // Reset the data toggle.
        //
        HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
            USB_TXCSRL1_CLRDT;
    }
    else
    {
        //
        // Clear the stall on an OUT endpoint.
        //
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);

        //
        // Reset the data toggle.
        //
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
            USB_RXCSRL1_CLRDT;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevConnect(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Enable connection to the USB bus.
    //
    HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevDisconnect(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Disable connection to the USB bus.
    //
    HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Set the function address in the correct location.
    //
    HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBDevAddrGet(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Return the function address.
    //
    return(HWREGB(ui32Base + USB_O_FADDR));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint,
                      uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval,
                      uint32_t ui32TargetEndpoint, uint32_t ui32Flags)
{
    uint32_t ui32Register;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
    ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT);

    //
    // Endpoint zero is configured differently than the other endpoints, so see
    // if this is endpoint zero.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Set the NAK timeout.
        //
        HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval;

        //
        // Set the transfer type information.
        //
        //
        // Set the speed of this endpoint.
        //
        if(ui32Flags & USB_EP_SPEED_HIGH)
        {
            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH;
        }
        else if(ui32Flags & USB_EP_SPEED_FULL)
        {
            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL;
        }
        else
        {
            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW;
        }
    }
    else
    {
        //
        // Start with the target endpoint.
        //
        ui32Register = ui32TargetEndpoint;

        //
        // Set the speed for the device using this endpoint.
        //
        if(ui32Flags & USB_EP_SPEED_HIGH)
        {
            ui32Register |= USB_TXTYPE1_SPEED_HIGH;
        }
        else if(ui32Flags & USB_EP_SPEED_FULL)
        {
            ui32Register |= USB_TXTYPE1_SPEED_FULL;
        }
        else
        {
            ui32Register |= USB_TXTYPE1_SPEED_LOW;
        }

        //
        // Set the protocol for the device using this endpoint.
        //
        switch(ui32Flags & USB_EP_MODE_MASK)
        {
            //
            // The bulk protocol is being used.
            //
            case USB_EP_MODE_BULK:
            {
                ui32Register |= USB_TXTYPE1_PROTO_BULK;
                break;
            }

            //
            // The isochronous protocol is being used.
            //
            case USB_EP_MODE_ISOC:
            {
                ui32Register |= USB_TXTYPE1_PROTO_ISOC;
                break;
            }

            //
            // The interrupt protocol is being used.
            //
            case USB_EP_MODE_INT:
            {
                ui32Register |= USB_TXTYPE1_PROTO_INT;
                break;
            }

            //
            // The control protocol is being used.
            //
            case USB_EP_MODE_CTRL:
            {
                ui32Register |= USB_TXTYPE1_PROTO_CTRL;
                break;
            }
        }

        //
        // See if the transmit or receive endpoint is being configured.
        //
        if(ui32Flags & USB_EP_HOST_OUT)
        {
            //
            // Set the transfer type information.
            //
            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) =
                ui32Register;

            //
            // Set the NAK timeout or polling interval.
            //
            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) =
                ui32NAKPollInterval;

            //
            // Set the Maximum Payload per transaction.
            //
            HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) =
                ui32MaxPayload;

            //
            // Set the transmit control value to zero.
            //
            ui32Register = 0;

            //
            // Allow auto setting of TxPktRdy when max packet size has been
            // loaded into the FIFO.
            //
            if(ui32Flags & USB_EP_AUTO_SET)
            {
                ui32Register |= USB_TXCSRH1_AUTOSET;
            }

            //
            // Configure the DMA Mode.
            //
            if(ui32Flags & USB_EP_DMA_MODE_1)
            {
                ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
            }
            else if(ui32Flags & USB_EP_DMA_MODE_0)
            {
                ui32Register |= USB_TXCSRH1_DMAEN;
            }

            //
            // Write out the transmit control value.
            //
            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
                (uint8_t)ui32Register;
        }
        else
        {
            //
            // Set the transfer type information.
            //
            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) =
                ui32Register;

            //
            // Set the NAK timeout or polling interval.
            //
            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) =
                ui32NAKPollInterval;

            //
            // Set the Maximum Payload per transaction.
            //
            HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) =
                ui32MaxPayload;

            //
            // Set the receive control value to zero.
            //
            ui32Register = 0;

            //
            // Allow auto clearing of RxPktRdy when packet of size max packet
            // has been unloaded from the FIFO.
            //
            if(ui32Flags & USB_EP_AUTO_CLEAR)
            {
                ui32Register |= USB_RXCSRH1_AUTOCL;
            }

            //
            // Allow auto generation of DMA requests.
            //
            if(ui32Flags & USB_EP_AUTO_REQUEST)
            {
                ui32Register |= USB_RXCSRH1_AUTORQ;
            }

            //
            // Configure the DMA Mode.
            //
            if(ui32Flags & USB_EP_DMA_MODE_1)
            {
                ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
            }
            else if(ui32Flags & USB_EP_DMA_MODE_0)
            {
                ui32Register |= USB_RXCSRH1_DMAEN;
            }

            //
            // Write out the receive control value.
            //
            HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
                (uint8_t)ui32Register;
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostEndpointSpeed(uint32_t ui32Base, uint32_t ui32Endpoint,
                     uint32_t ui32Flags)
{
    uint32_t ui32Reg;
    uint32_t ui32Speed;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Create the register speed value.
    //
    if(ui32Flags & USB_EP_SPEED_HIGH)
    {
        ui32Speed = USB_TYPE0_SPEED_HIGH;
    }
    else if(ui32Flags & USB_EP_SPEED_FULL)
    {
        ui32Speed = USB_TYPE0_SPEED_FULL;
    }
    else
    {
        ui32Speed = USB_TYPE0_SPEED_LOW;
    }

    //
    // Endpoint 0 is handled differently as it is bi-directional.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        HWREGB(ui32Base + USB_O_TYPE0) = ui32Speed;
    }
    else if(ui32Flags & USB_EP_HOST_OUT)
    {
        //
        // Clear the current speed and set the new speed.
        //
        ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) &
                   ~(USB_TXTYPE1_SPEED_M));
        ui32Reg |= ui32Speed;

        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) |= ui32Reg;
    }
    else
    {
        //
        // Clear the current speed and set the new speed.
        //
        ui32Reg = (HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) &
                   ~(USB_RXTYPE1_SPEED_M));
        ui32Reg |= ui32Speed;

        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) |= ui32Reg;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
                        uint32_t ui32MaxPacketSize, uint32_t ui32Flags)
{
    uint32_t ui32Register;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
           (ui32Endpoint == USB_EP_7));

    //
    // Determine if a transmit or receive endpoint is being configured.
    //
    if(ui32Flags & USB_EP_DEV_IN)
    {
        //
        // Set the maximum packet size.
        //
        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) =
            ui32MaxPacketSize;

        //
        // The transmit control value is zero unless options are enabled.
        //
        ui32Register = 0;

        //
        // Allow auto setting of TxPktRdy when max packet size has been loaded
        // into the FIFO.
        //
        if(ui32Flags & USB_EP_AUTO_SET)
        {
            ui32Register |= USB_TXCSRH1_AUTOSET;
        }

        //
        // Configure the DMA mode.
        //
        if(ui32Flags & USB_EP_DMA_MODE_1)
        {
            ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
        }
        else if(ui32Flags & USB_EP_DMA_MODE_0)
        {
            ui32Register |= USB_TXCSRH1_DMAEN;
        }

        //
        // Enable isochronous mode if requested.
        //
        if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
        {
            ui32Register |= USB_TXCSRH1_ISO;
        }

        //
        // Write the transmit control value.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
            (uint8_t)ui32Register;

        //
        // Reset the Data toggle to zero.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) =
            USB_TXCSRL1_CLRDT;
    }
    else
    {
        //
        // Set the MaxPacketSize.
        //
        HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) =
            ui32MaxPacketSize;

        //
        // The receive control value is zero unless options are enabled.
        //
        ui32Register = 0;

        //
        // Allow auto clearing of RxPktRdy when packet of size max packet
        // has been unloaded from the FIFO.
        //
        if(ui32Flags & USB_EP_AUTO_CLEAR)
        {
            ui32Register = USB_RXCSRH1_AUTOCL;
        }

        //
        // Configure the DMA mode.
        //
        if(ui32Flags & USB_EP_DMA_MODE_1)
        {
            ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
        }
        else if(ui32Flags & USB_EP_DMA_MODE_0)
        {
            ui32Register |= USB_RXCSRH1_DMAEN;
        }

        //
        // If requested, disable NYET responses for high-speed bulk and
        // interrupt endpoints.
        //
        if(ui32Flags & USB_EP_DIS_NYET)
        {
            ui32Register |= USB_RXCSRH1_DISNYET;
        }

        //
        // Enable isochronous mode if requested.
        //
        if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
        {
            ui32Register |= USB_RXCSRH1_ISO;
        }

        //
        // Write the receive control value.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
            (uint8_t)ui32Register;

        //
        // Reset the Data toggle to zero.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) =
            USB_RXCSRL1_CLRDT;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
                        uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags)
{
    uint32_t ui32Register;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(pui32MaxPacketSize && pui32Flags);
    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
           (ui32Endpoint == USB_EP_7));

    //
    // Determine if a transmit or receive endpoint is being queried.
    //
    if(*pui32Flags & USB_EP_DEV_IN)
    {
        //
        // Clear the flags other than the direction bit.
        //
        *pui32Flags = USB_EP_DEV_IN;

        //
        // Get the maximum packet size.
        //
        *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base +
                                               EP_OFFSET(ui32Endpoint) +
                                               USB_O_TXMAXP1);

        //
        // Get the current transmit control register value.
        //
        ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) +
                                        USB_O_TXCSRH1);

        //
        // Are we allowing auto setting of TxPktRdy when max packet size has
        // been loaded into the FIFO?
        //
        if(ui32Register & USB_TXCSRH1_AUTOSET)
        {
            *pui32Flags |= USB_EP_AUTO_SET;
        }

        //
        // Get the DMA mode.
        //
        if(ui32Register & USB_TXCSRH1_DMAEN)
        {
            if(ui32Register & USB_TXCSRH1_DMAMOD)
            {
                *pui32Flags |= USB_EP_DMA_MODE_1;
            }
            else
            {
                *pui32Flags |= USB_EP_DMA_MODE_0;
            }
        }

        //
        // Are we in isochronous mode?
        //
        if(ui32Register & USB_TXCSRH1_ISO)
        {
            *pui32Flags |= USB_EP_MODE_ISOC;
        }
        else
        {
            //
            // The hardware doesn't differentiate between bulk, interrupt
            // and control mode for the endpoint so we just set something
            // that isn't isochronous.  This protocol ensures that anyone
            // modifying the returned flags in preparation for a call to
            // USBDevEndpointConfigSet do not see an unexpected mode change.
            // If they decode the returned mode, however, they may be in for
            // a surprise.
            //
            *pui32Flags |= USB_EP_MODE_BULK;
        }
    }
    else
    {
        //
        // Clear the flags other than the direction bit.
        //
        *pui32Flags = USB_EP_DEV_OUT;

        //
        // Get the MaxPacketSize.
        //
        *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base +
                                               EP_OFFSET(ui32Endpoint) +
                                               USB_O_RXMAXP1);

        //
        // Get the current receive control register value.
        //
        ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) +
                                        USB_O_RXCSRH1);

        //
        // Are we allowing auto clearing of RxPktRdy when packet of size max
        // packet has been unloaded from the FIFO?
        //
        if(ui32Register & USB_RXCSRH1_AUTOCL)
        {
            *pui32Flags |= USB_EP_AUTO_CLEAR;
        }

        //
        // Get the DMA mode.
        //
        if(ui32Register & USB_RXCSRH1_DMAEN)
        {
            if(ui32Register & USB_RXCSRH1_DMAMOD)
            {
                *pui32Flags |= USB_EP_DMA_MODE_1;
            }
            else
            {
                *pui32Flags |= USB_EP_DMA_MODE_0;
            }
        }

        //
        // Are we in isochronous mode?
        //
        if(ui32Register & USB_RXCSRH1_ISO)
        {
            *pui32Flags |= USB_EP_MODE_ISOC;
        }
        else
        {
            //
            // The hardware doesn't differentiate between bulk, interrupt
            // and control mode for the endpoint so we just set something
            // that isn't isochronous.  This protocol ensures that anyone
            // modifying the returned flags in preparation for a call to
            // USBDevEndpointConfigSet do not see an unexpected mode change.
            // If they decode the returned mode, however, they may be in for
            // a surprise.
            //
            *pui32Flags |= USB_EP_MODE_BULK;
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
                 uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize,
                 uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
           (ui32Endpoint == USB_EP_7));

    //
    // See if the transmit or receive FIFO is being configured.
    //
    if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
    {
        //
        // Set the transmit FIFO location and size for this endpoint.
        //
        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ,
                       ui32FIFOSize, 1);
        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD,
                       ui32FIFOAddress >> 3, 2);
    }
    else
    {
        //
        // Set the receive FIFO location and size for this endpoint.
        //
        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ,
                       ui32FIFOSize, 1);
        _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD,
                       ui32FIFOAddress >> 3, 2);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
                 uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize,
                 uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
           (ui32Endpoint == USB_EP_7));

    //
    // See if the transmit or receive FIFO is being configured.
    //
    if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
    {
        //
        // Get the transmit FIFO location and size for this endpoint.
        //
        *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4,
                                           (uint32_t)USB_O_TXFIFOADD,
                                           2)) << 3;
        *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4,
                                       (uint32_t)USB_O_TXFIFOSZ, 1);
    }
    else
    {
        //
        // Get the receive FIFO location and size for this endpoint.
        //
        *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4,
                                           (uint32_t)USB_O_RXFIFOADD,
                                           2)) << 3;
        *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4,
                                       (uint32_t)USB_O_RXFIFOSZ, 1);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
                        uint32_t ui32Config)
{
    uint32_t ui32NewConfig;

    if(ui32Config & USB_EP_HOST_OUT)
    {
        //
        // Clear mode and DMA enable.
        //
        ui32NewConfig =
            (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &
             ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET));

        if(ui32Config & USB_EP_DMA_MODE_1)
        {
            ui32NewConfig |= USB_TXCSRH1_DMAMOD;
        }

        if(ui32Config & USB_EP_AUTO_SET)
        {
            ui32NewConfig |= USB_TXCSRH1_AUTOSET;
        }

        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
            ui32NewConfig;
    }
    else
    {
        ui32NewConfig =
            (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &
             ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD));

        if(ui32Config & USB_EP_DMA_MODE_1)
        {
            ui32NewConfig |= USB_RXCSRH1_DMAMOD;
        }

        if(ui32Config & USB_EP_AUTO_CLEAR)
        {
            ui32NewConfig |= USB_RXCSRH1_AUTOCL;
        }
        if(ui32Config & USB_EP_AUTO_REQUEST)
        {
            ui32NewConfig |= USB_RXCSRH1_AUTORQ;
        }
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
            ui32NewConfig;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint,
                     uint32_t ui32Flags)
{
    //
    // See if the transmit DMA is being enabled.
    //
    if(ui32Flags & USB_EP_DEV_IN)
    {
        //
        // Enable DMA on the transmit endpoint.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |=
            USB_TXCSRH1_DMAEN;
    }
    else
    {
        //
        // Enable DMA on the receive endpoint.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |=
            USB_RXCSRH1_DMAEN;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint,
                      uint32_t ui32Flags)
{
    //
    // If this was a request to disable DMA on the IN portion of the endpoint
    // then handle it.
    //
    if(ui32Flags & USB_EP_DEV_IN)
    {
        //
        // Just disable DMA leave the mode setting.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &=
            ~USB_TXCSRH1_DMAEN;
    }
    else
    {
        //
        // Just disable DMA leave the mode setting.
        //
        HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &=
            ~USB_RXCSRH1_DMAEN;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint)
{
    uint32_t ui32Register;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Get the address of the receive status register to use, based on the
    // endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        ui32Register = USB_O_CSRL0;
    }
    else
    {
        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
    }

    //
    // Is there a packet ready in the FIFO?
    //
    if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0)
    {
        return(0);
    }

    //
    // Return the byte count in the FIFO.
    //
    return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint));
}

//*****************************************************************************
//
//
//*****************************************************************************
int32_t
USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint,
                   uint8_t *pui8Data, uint32_t *pui32Size)
{
    uint32_t ui32Register, ui32ByteCount, ui32FIFO;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Get the address of the receive status register to use, based on the
    // endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        ui32Register = USB_O_CSRL0;
    }
    else
    {
        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
    }

    //
    // Don't allow reading of data if the RxPktRdy bit is not set.
    //
    if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0)
    {
        //
        // Can't read the data because none is available.
        //
        *pui32Size = 0;

        //
        // Return a failure since there is no data to read.
        //
        return(-1);
    }

    //
    // Get the byte count in the FIFO.
    //
    ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint);

    //
    // Determine how many bytes are copied.
    //
    ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size;

    //
    // Return the number of bytes we are going to read.
    //
    *pui32Size = ui32ByteCount;

    //
    // Calculate the FIFO address.
    //
    ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2);

    //
    // Read the data out of the FIFO.
    //
    for(; ui32ByteCount > 0; ui32ByteCount--)
    {
        //
        // Read a byte at a time from the FIFO.
        //
        *pui8Data++ = HWREGB(ui32FIFO);
    }

    //
    // Success.
    //
    return(0);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint,
                      bool bIsLastPacket)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Determine which endpoint is being acked.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Clear RxPktRdy, and optionally DataEnd, on endpoint zero.
        //
        HWREGB(ui32Base + USB_O_CSRL0) =
            USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0);
    }
    else
    {
        //
        // Clear RxPktRdy on all other endpoints.
        //
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~(USB_RXCSRL1_RXRDY);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Clear RxPktRdy.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY;
    }
    else
    {
        HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
            ~(USB_RXCSRL1_RXRDY);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
int32_t
USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint,
                   uint8_t *pui8Data, uint32_t ui32Size)
{
    uint32_t ui32FIFO;
    uint8_t ui8TxPktRdy;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Get the bit position of TxPktRdy based on the endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        ui8TxPktRdy = USB_CSRL0_TXRDY;
    }
    else
    {
        ui8TxPktRdy = USB_TXCSRL1_TXRDY;
    }

    //
    // Don't allow transmit of data if the TxPktRdy bit is already set.
    //
    if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy)
    {
        return(-1);
    }

    //
    // Calculate the FIFO address.
    //
    ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2);

    //
    // Write the data to the FIFO.
    //
    for(; ui32Size > 0; ui32Size--)
    {
        HWREGB(ui32FIFO) = *pui8Data++;
    }

    //
    // Success.
    //
    return(0);
}

//*****************************************************************************
//
//
//*****************************************************************************
int32_t
USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint,
                    uint32_t ui32TransType)
{
    uint32_t ui32TxPktRdy;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Get the bit position of TxPktRdy based on the endpoint.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Don't allow transmit of data if the TxPktRdy bit is already set.
        //
        if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY)
        {
            return(-1);
        }

        ui32TxPktRdy = ui32TransType & 0xff;
    }
    else
    {
        //
        // Don't allow transmit of data if the TxPktRdy bit is already set.
        //
        if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY)
        {
            return(-1);
        }

        ui32TxPktRdy = (ui32TransType >> 8) & 0xff;
    }

    //
    // Set TxPktRdy in order to send the data.
    //
    HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy;

    //
    // Success.
    //
    return(0);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Endpoint zero has a different register set for FIFO flushing.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        //
        // Nothing in the FIFO if neither of these bits are set.
        //
        if((HWREGB(ui32Base + USB_O_CSRL0) &
            (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
        {
            //
            // Hit the Flush FIFO bit.
            //
            HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH;
        }
    }
    else
    {
        //
        // Only reset the IN or OUT FIFO.
        //
        if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
        {
            //
            // Make sure the FIFO is not empty.
            //
            if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &
               USB_TXCSRL1_TXRDY)
            {
                //
                // Hit the Flush FIFO bit.
                //
                HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
                    USB_TXCSRL1_FLUSH;
            }
        }
        else
        {
            //
            // Make sure that the FIFO is not empty.
            //
            if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &
               USB_RXCSRL1_RXRDY)
            {
                //
                // Hit the Flush FIFO bit.
                //
                HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
                    USB_RXCSRL1_FLUSH;
            }
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint)
{
    uint32_t ui32Register;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Endpoint zero uses a different offset than the other endpoints.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        ui32Register = USB_O_CSRL0;
    }
    else
    {
        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
    }

    //
    // Set the request for an IN transaction.
    //
    HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint)
{
    uint32_t ui32Register;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // Endpoint zero uses a different offset than the other endpoints.
    //
    if(ui32Endpoint == USB_EP_0)
    {
        ui32Register = USB_O_CSRL0;
    }
    else
    {
        ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
    }

    //
    // Clear the request for an IN transaction.
    //
    HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostRequestStatus(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Set the request for a status IN transaction.
    //
    HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr,
               uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // See if the transmit or receive address is set.
    //
    if(ui32Flags & USB_EP_HOST_OUT)
    {
        //
        // Set the transmit address.
        //
        HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr;
    }
    else
    {
        //
        // Set the receive address.
        //
        HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) =
            ui32Addr;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // See if the transmit or receive address is returned.
    //
    if(ui32Flags & USB_EP_HOST_OUT)
    {
        //
        // Return this endpoint's transmit address.
        //
        return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)));
    }
    else
    {
        //
        // Return this endpoint's receive address.
        //
        return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr,
                  uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // See if the hub transmit or receive address is being set.
    //
    if(ui32Flags & USB_EP_HOST_OUT)
    {
        //
        // Set the hub transmit address and port number for this endpoint.
        //
        HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr;
    }
    else
    {
        //
        // Set the hub receive address and port number for this endpoint.
        //
        HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) =
            ui32Addr;
    }

    //
    // Set the speed of communication for endpoint 0.  This configuration is
    // done here because it changes on a transaction-by-transaction basis for
    // EP0.  For other endpoints, this is set in USBHostEndpointConfig().
    //
    if(ui32Endpoint == USB_EP_0)
    {
        if(ui32Flags & USB_EP_SPEED_FULL)
        {
            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL;
        }
        else if(ui32Flags & USB_EP_SPEED_HIGH)
        {
            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_HIGH;
        }
        else
        {
            HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW;
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
           (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
           (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
           (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));

    //
    // See if the hub transmit or receive address is returned.
    //
    if(ui32Flags & USB_EP_HOST_OUT)
    {
        //
        // Return the hub transmit address for this endpoint.
        //
        return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)));
    }
    else
    {
        //
        // Return the hub receive address for this endpoint.
        //
        return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M |
                          USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH |
                          USB_EPC_EPEN_M)) == 0);

    //
    // If requested, enable VBUS droop detection on parts that support this
    // feature.
    //
    HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16;

    //
    // Set the power fault configuration as specified.  This configuration
    // does not change whether fault detection is enabled or not.
    //
    HWREGH(ui32Base + USB_O_EPC) =
        (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) &
                      ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
                        USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostPwrFaultEnable(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Enable power fault input.
    //
    HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostPwrFaultDisable(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Enable power fault input.
    //
    HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostPwrEnable(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Enable the external power supply enable signal.
    //
    HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostPwrDisable(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Disable the external power supply enable signal.
    //
    HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBFrameNumberGet(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Return the most recent frame number.
    //
    return(HWREGH(ui32Base + USB_O_FRAME));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBOTGSessionRequest(uint32_t ui32Base, bool bStart)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Start or end the session as directed.
    //
    if(bStart)
    {
        HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION;
    }
    else
    {
        HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint)
{
    //
    // Return the FIFO address for this endpoint.
    //
    return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBModeGet(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Checks the current mode in the USB_O_DEVCTL and returns the current
    // mode.
    //
    // USB_OTG_MODE_ASIDE_HOST:  USB_DEVCTL_HOST | USB_DEVCTL_SESSION
    // USB_OTG_MODE_ASIDE_DEV:   USB_DEVCTL_SESSION
    // USB_OTG_MODE_BSIDE_HOST:  USB_DEVCTL_DEV | USB_DEVCTL_SESSION |
    //                           USB_DEVCTL_HOST
    // USB_OTG_MODE_BSIDE_DEV:   USB_DEVCTL_DEV | USB_DEVCTL_SESSION
    // USB_OTG_MODE_NONE:        USB_DEVCTL_DEV
    //
    return(HWREGB(ui32Base + USB_O_DEVCTL) &
           (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION |
            USB_DEVCTL_VBUS_M));
}

//*****************************************************************************
//
//*****************************************************************************
void
USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint,
                      uint32_t ui32Channel)
{
    uint32_t ui32Mask;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);
    ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
           (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
           (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
           (ui32Endpoint == USB_EP_7));
    ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX);

    //
    // The input select mask must be shifted into the correct position
    // based on the channel.
    //
    ui32Mask = 0xf << (ui32Channel * 4);

    //
    // Clear out the current selection for the channel.
    //
    ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask);

    //
    // The input select is now shifted into the correct position based on the
    // channel.
    //
    ui32Mask |= (USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4);

    //
    // Write the value out to the register.
    //
    HWREG(ui32Base + USB_O_DMASEL) = ui32Mask;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostMode(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Force mode in OTG parts that support forcing USB controller mode.
    // This bit is not writable in USB controllers that do not support
    // forcing the mode.  Not setting the USB_GPCS_DEVMOD bit makes this a
    // force of host mode.
    //
    HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevMode(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Set the USB controller mode to device.
    //
    HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBOTGMode(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    //
    // Disable the override of the USB controller mode when running on an OTG
    // device.
    //
    HWREGB(ui32Base + USB_O_GPCS) = 0;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBModeConfig(uint32_t ui32Base, uint32_t ui32Mode)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == USB0_BASE);

    HWREG(ui32Base + USB_O_GPCS) = ui32Mode;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBPHYPowerOff(uint32_t ui32Base)
{
    //
    // Set the PWRDNPHY bit in the PHY, putting it into its low power mode.
    //
    HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBPHYPowerOn(uint32_t ui32Base)
{
    //
    // Clear the PWRDNPHY bit in the PHY, putting it into normal operating
    // mode.
    //
    HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint,
                          uint32_t ui32Count)
{
    HWREG(ui32Base + USB_O_RQPKTCOUNT1 +
          (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBNumEndpointsGet(uint32_t ui32Base)
{
    //
    // Read the number of endpoints from the hardware.  The number of TX and
    // RX endpoints are always the same.
    //
    return(HWREGB(ui32Base + USB_O_EPINFO) & USB_EPINFO_TXEP_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBControllerVersion(uint32_t ui32Base)
{
    //
    // Return the type field of the peripheral properties.  This returns
    // zero for all parts that did not have a peripheral property.
    //
    return(HWREG(ui32Base + USB_O_PP) & USB_PP_TYPE_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBClockEnable(uint32_t ui32Base, uint32_t ui32Div, uint32_t ui32Flags)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Configure and enable the USB clock input.
    //
    HWREG(ui32Base + USB_O_CC) = (ui32Div - 1) | ui32Flags;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBClockDisable(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Disable the USB clock input.
    //
    HWREG(ui32Base + USB_O_CC) = 0;
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelIntEnable(uint32_t ui32Base, uint32_t ui32Channel)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Enable the specified DMA channel interrupts.
    //
    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |= USB_DMACTL0_IE;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelIntDisable(uint32_t ui32Base, uint32_t ui32Channel)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Enable the specified DMA channel interrupts.
    //
    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~USB_DMACTL0_IE;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBDMAChannelIntStatus(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    return(HWREG(ui32Base + USB_O_DMAINTR));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelEnable(uint32_t ui32Base, uint32_t ui32Channel)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Enable the USB DMA channel.
    //
    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) |=
        USB_DMACTL0_ENABLE;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelDisable(uint32_t ui32Base, uint32_t ui32Channel)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Disable the USB DMA channel.
    //
    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &=
        ~USB_DMACTL0_ENABLE;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelConfigSet(uint32_t ui32Base, uint32_t ui32Channel,
                       uint32_t ui32Endpoint, uint32_t ui32Config)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);
    ASSERT((ui32Endpoint & ~USB_EP_7) == 0);

    //
    // Reset this USB DMA channel.
    //
    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) = 0;

    //
    // Set the configuration of the requested channel.
    //
    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) =
        ui32Config | ui32Endpoint;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBDMAChannelStatus(uint32_t ui32Base, uint32_t ui32Channel)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Return a non-zero value if there is a pending error condition.
    //
    return(HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &
           USB_DMACTL0_ERR);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelStatusClear(uint32_t ui32Base, uint32_t ui32Channel,
                         uint32_t ui32Status)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // The only status is the error bit.
    //
    ui32Status &= USB_DMACTL0_ERR;

    //
    // Clear the specified error condition.
    //
    HWREG(ui32Base + USB_O_DMACTL0 + (0x10 * ui32Channel)) &= ~ui32Status;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelAddressSet(uint32_t ui32Base, uint32_t ui32Channel,
                        void *pvAddress)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Set the DMA address.
    //
    HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel)) =
        (uint32_t)pvAddress;
}

//*****************************************************************************
//
//
//*****************************************************************************
void *
USBDMAChannelAddressGet(uint32_t ui32Base, uint32_t ui32Channel)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Return the current DMA address.
    //
    return((void *)HWREG(ui32Base + USB_O_DMAADDR0 + (0x10 * ui32Channel)));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDMAChannelCountSet(uint32_t ui32Base, uint32_t ui32Channel,
                      uint32_t ui32Count)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Set the USB DMA count for the channel.
    //
    HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel)) = ui32Count;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBDMAChannelCountGet(uint32_t ui32Base, uint32_t ui32Channel)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Channel < 8);

    //
    // Return the current DMA count.
    //
    return(HWREG(ui32Base + USB_O_DMACOUNT0 + (0x10 * ui32Channel)));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBDMANumChannels(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Return the number of DMA channels for the integrated DMA controller.
    //
    return(HWREG(ui32Base + USB_O_RAMINFO) >> USB_RAMINFO_DMACHAN_S);
}
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************
void
USBULPIConfig(uint32_t ui32Base, uint32_t ui32Config)
{
    HWREGB(ui32Base + USB_O_ULPIVBUSCTL) = (uint8_t)ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBULPIEnable(uint32_t ui32Base)
{
    HWREG(ui32Base + USB_O_PC) |= USB_PC_ULPIEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBULPIDisable(uint32_t ui32Base)
{
    HWREG(ui32Base + USB_O_PC) &= ~USB_PC_ULPIEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint8_t
USBULPIRegRead(uint32_t ui32Base, uint8_t ui8Reg)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Set the register address and initiate a read access.
    //
    HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg;
    HWREGB(ui32Base + USB_O_ULPIREGCTL) =
        USB_ULPIREGCTL_RDWR | USB_ULPIREGCTL_REGACC;

    //
    // Wait for the access to complete.
    //
    while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0)
    {
    }

    //
    // Clear the register access complete flag.
    //
    HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0;

    return(HWREGB(ui32Base + USB_O_ULPIREGDATA));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBULPIRegWrite(uint32_t ui32Base, uint8_t ui8Reg, uint8_t ui8Data)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Set the register address and initiate a read access.
    //
    HWREGB(ui32Base + USB_O_ULPIREGADDR) = ui8Reg;
    HWREGB(ui32Base + USB_O_ULPIREGDATA) = ui8Data;
    HWREGB(ui32Base + USB_O_ULPIREGCTL) = USB_ULPIREGCTL_REGACC;

    //
    // Wait for the access to complete.
    //
    while((HWREGB(ui32Base + USB_O_ULPIREGCTL) & USB_ULPIREGCTL_REGCMPLT) == 0)
    {
    }

    //
    // Clear the register access complete flag.
    //
    HWREGB(ui32Base + USB_O_ULPIREGCTL) = 0;
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostLPMSend(uint32_t ui32Base, uint32_t ui32Address, uint32_t ui32Endpoint)
{
    uint32_t ui32Reg;

    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32Address < 127);

    //
    // Set the address and endpoint.
    //
    HWREGB(ui32Base + USB_O_LPMFADDR) = ui32Address;

    ui32Reg = HWREGH(ui32Base + USB_O_LPMATTR) & ~USB_LPMATTR_ENDPT_M;
    ui32Reg |= (USBEPToIndex(ui32Endpoint) << USB_LPMATTR_ENDPT_S);

    HWREGH(ui32Base + USB_O_LPMATTR) = ui32Reg;

    //
    // Send the LPM transaction.
    //
    HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_TXLPM;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostLPMConfig(uint32_t ui32Base, uint32_t ui32ResumeTime,
                 uint32_t ui32Config)
{
    ASSERT(ui32Base == USB0_BASE);
    ASSERT(ui32ResumeTime <= 1175);
    ASSERT(ui32ResumeTime >= 50);

    //
    // Set the Host Initiated Resume Duration, Remote wake and Suspend mode.
    //
    HWREGH(ui32Base + USB_O_LPMATTR) =
        ui32Config | ((ui32ResumeTime - 50) / 75) << USB_LPMATTR_HIRD_S;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBHostLPMResume(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Send Resume signaling.
    //
    HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevLPMRemoteWake(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Send remote wake signaling.
    //
    HWREGB(ui32Base + USB_O_LPMCNTRL) |= USB_LPMCNTRL_RES;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevLPMConfig(uint32_t ui32Base, uint32_t ui32Config)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Set the device LPM configuration.
    //
    HWREGB(ui32Base + USB_O_LPMCNTRL) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevLPMEnable(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Enable L1 mode on the next LPM transaction.
    //
    HWREGB(ui32Base + USB_O_LPMCNTRL) |=
        USB_LPMCNTRL_EN_LPMEXT | USB_LPMCNTRL_TXLPM;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBDevLPMDisable(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Disable auto entering L1 mode on LPM transactions.
    //
    HWREGB(ui32Base + USB_O_LPMCNTRL) &= ~USB_LPMCNTRL_TXLPM;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBLPMLinkStateGet(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    return(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_LS_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBLPMEndpointGet(uint32_t ui32Base)
{
    uint32_t ui32Endpoint;

    ASSERT(ui32Base == USB0_BASE);

    ui32Endpoint = (HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_ENDPT_M) >>
                   USB_LPMATTR_ENDPT_S;

    return(IndexToUSBEP(ui32Endpoint));
}

//*****************************************************************************
//
//
//*****************************************************************************
bool
USBLPMRemoteWakeEnabled(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    if(HWREGH(ui32Base + USB_O_LPMATTR) & USB_LPMATTR_RMTWAK)
    {
        return(true);
    }
    return(false);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
USBLPMIntStatus(uint32_t ui32Base)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Return the current raw interrupt status.
    //
    return(HWREGB(ui32Base + USB_O_LPMRIS));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBLPMIntEnable(uint32_t ui32Base, uint32_t ui32Ints)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Enable the requested interrupts.
    //
    HWREGB(ui32Base + USB_O_LPMIM) |= ui32Ints;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
USBLPMIntDisable(uint32_t ui32Base, uint32_t ui32Ints)
{
    ASSERT(ui32Base == USB0_BASE);

    //
    // Disable the requested interrupts.
    //
    HWREGB(ui32Base + USB_O_LPMIM) &= ~ui32Ints;
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************