EE445M RTOS
Taken at the University of Texas Spring 2015
mpu.c
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1 //*****************************************************************************
2 //
3 // mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
4 //
5 // Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved.
6 // Software License Agreement
7 //
8 // Redistribution and use in source and binary forms, with or without
9 // modification, are permitted provided that the following conditions
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11 //
12 // Redistributions of source code must retain the above copyright
13 // notice, this list of conditions and the following disclaimer.
14 //
15 // Redistributions in binary form must reproduce the above copyright
16 // notice, this list of conditions and the following disclaimer in the
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18 // distribution.
19 //
20 // Neither the name of Texas Instruments Incorporated nor the names of
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22 // from this software without specific prior written permission.
23 //
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 //
36 // This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
37 //
38 //*****************************************************************************
39 
40 //*****************************************************************************
41 //
44 //
45 //*****************************************************************************
46 
47 #include <stdbool.h>
48 #include <stdint.h>
49 #include "inc/hw_ints.h"
50 #include "inc/hw_nvic.h"
51 #include "inc/hw_types.h"
52 #include "driverlib/debug.h"
53 #include "driverlib/interrupt.h"
54 #include "driverlib/mpu.h"
55 
56 //*****************************************************************************
57 //
86 //
87 //*****************************************************************************
88 void
89 MPUEnable(uint32_t ui32MPUConfig)
90 {
91  //
92  // Check the arguments.
93  //
94  ASSERT(!(ui32MPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
96 
97  //
98  // Set the MPU control bits according to the flags passed by the user,
99  // and also set the enable bit.
100  //
101  HWREG(NVIC_MPU_CTRL) = ui32MPUConfig | NVIC_MPU_CTRL_ENABLE;
102 }
103 
104 //*****************************************************************************
105 //
113 //
114 //*****************************************************************************
115 void
117 {
118  //
119  // Turn off the MPU enable bit.
120  //
122 }
123 
124 //*****************************************************************************
125 //
133 //
134 //*****************************************************************************
135 uint32_t
137 {
138  //
139  // Read the DREGION field of the MPU type register and mask off
140  // the bits of interest to get the count of regions.
141  //
144 }
145 
146 //*****************************************************************************
147 //
158 //
159 //*****************************************************************************
160 void
161 MPURegionEnable(uint32_t ui32Region)
162 {
163  //
164  // Check the arguments.
165  //
166  ASSERT(ui32Region < 8);
167 
168  //
169  // Select the region to modify.
170  //
171  HWREG(NVIC_MPU_NUMBER) = ui32Region;
172 
173  //
174  // Modify the enable bit in the region attributes.
175  //
177 }
178 
179 //*****************************************************************************
180 //
191 //
192 //*****************************************************************************
193 void
194 MPURegionDisable(uint32_t ui32Region)
195 {
196  //
197  // Check the arguments.
198  //
199  ASSERT(ui32Region < 8);
200 
201  //
202  // Select the region to modify.
203  //
204  HWREG(NVIC_MPU_NUMBER) = ui32Region;
205 
206  //
207  // Modify the enable bit in the region attributes.
208  //
210 }
211 
212 //*****************************************************************************
213 //
318 //
319 //*****************************************************************************
320 void
321 MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags)
322 {
323  //
324  // Check the arguments.
325  //
326  ASSERT(ui32Region < 8);
327  ASSERT(ui32Addr ==
328  (ui32Addr & ~0 << (((ui32Flags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1)));
329 
330  //
331  // Program the base address, use the region field to select the
332  // region at the same time.
333  //
334  HWREG(NVIC_MPU_BASE) = ui32Addr | ui32Region | NVIC_MPU_BASE_VALID;
335 
336  //
337  // Program the region attributes. Set the TEX field and the S, C,
338  // and B bits to fixed values that are suitable for all Tiva C and
339  // E Series memory.
340  //
341  HWREG(NVIC_MPU_ATTR) = ((ui32Flags & ~(NVIC_MPU_ATTR_TEX_M |
344 }
345 
346 //*****************************************************************************
347 //
363 //
364 //*****************************************************************************
365 void
366 MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags)
367 {
368  //
369  // Check the arguments.
370  //
371  ASSERT(ui32Region < 8);
372  ASSERT(pui32Addr);
373  ASSERT(pui32Flags);
374 
375  //
376  // Select the region to get.
377  //
378  HWREG(NVIC_MPU_NUMBER) = ui32Region;
379 
380  //
381  // Read and store the base address for the region.
382  //
383  *pui32Addr = HWREG(NVIC_MPU_BASE) & NVIC_MPU_BASE_ADDR_M;
384 
385  //
386  // Read and store the region attributes.
387  //
388  *pui32Flags = HWREG(NVIC_MPU_ATTR);
389 }
390 
391 //*****************************************************************************
392 //
406 //
407 //*****************************************************************************
408 void
409 MPUIntRegister(void (*pfnHandler)(void))
410 {
411  //
412  // Check the arguments.
413  //
414  ASSERT(pfnHandler);
415 
416  //
417  // Register the interrupt handler.
418  //
419  IntRegister(FAULT_MPU, pfnHandler);
420 
421  //
422  // Enable the memory management fault.
423  //
425 }
426 
427 //*****************************************************************************
428 //
438 //
439 //*****************************************************************************
440 void
442 {
443  //
444  // Disable the interrupt.
445  //
447 
448  //
449  // Unregister the interrupt handler.
450  //
452 }
453 
454 //*****************************************************************************
455 //
456 // Close the Doxygen group.
458 //
459 //*****************************************************************************
#define NVIC_MPU_TYPE
Definition: hw_nvic.h:130
#define NVIC_MPU_NUMBER
Definition: hw_nvic.h:132
void MPURegionGet(uint32_t ui32Region, uint32_t *pui32Addr, uint32_t *pui32Flags)
Definition: mpu.c:366
void MPURegionDisable(uint32_t ui32Region)
Definition: mpu.c:194
void MPUDisable(void)
Definition: mpu.c:116
#define HWREG(x)
Definition: hw_types.h:48
void MPUIntUnregister(void)
Definition: mpu.c:441
#define NVIC_MPU_ATTR_TEX_M
Definition: hw_nvic.h:1158
uint32_t MPURegionCountGet(void)
Definition: mpu.c:136
#define ASSERT(expr)
Definition: debug.h:67
#define NVIC_MPU_CTRL
Definition: hw_nvic.h:131
void MPURegionSet(uint32_t ui32Region, uint32_t ui32Addr, uint32_t ui32Flags)
Definition: mpu.c:321
#define FAULT_MPU
Definition: hw_ints.h:51
#define NVIC_MPU_ATTR_SHAREABLE
Definition: hw_nvic.h:1159
#define NVIC_MPU_ATTR
Definition: hw_nvic.h:134
#define MPU_CONFIG_PRIV_DEFAULT
Definition: mpu.h:59
void MPUEnable(uint32_t ui32MPUConfig)
Definition: mpu.c:89
#define NVIC_MPU_ATTR_SIZE_M
Definition: hw_nvic.h:1171
#define NVIC_MPU_ATTR_ENABLE
Definition: hw_nvic.h:1200
#define NVIC_MPU_CTRL_ENABLE
Definition: hw_nvic.h:1123
#define NVIC_MPU_ATTR_BUFFRABLE
Definition: hw_nvic.h:1161
#define NVIC_MPU_BASE
Definition: hw_nvic.h:133
#define MPU_CONFIG_HARDFLT_NMI
Definition: mpu.h:60
#define NVIC_MPU_BASE_VALID
Definition: hw_nvic.h:1140
void IntUnregister(uint32_t ui32Interrupt)
Definition: interrupt.c:381
#define NVIC_MPU_TYPE_DREGION_M
Definition: hw_nvic.h:1111
#define NVIC_MPU_TYPE_DREGION_S
Definition: hw_nvic.h:1114
#define NVIC_MPU_BASE_ADDR_M
Definition: hw_nvic.h:1139
#define NVIC_MPU_ATTR_CACHEABLE
Definition: hw_nvic.h:1160
void MPUIntRegister(void(*pfnHandler)(void))
Definition: mpu.c:409
void MPURegionEnable(uint32_t ui32Region)
Definition: mpu.c:161
void IntDisable(uint32_t ui32Interrupt)
Definition: interrupt.c:684
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Definition: interrupt.c:309
void IntEnable(uint32_t ui32Interrupt)
Definition: interrupt.c:610