EE445M RTOS
Taken at the University of Texas Spring 2015
Interrupt_api

Macros

#define NUM_INTERRUPTS   155
 

Functions

static void _IntDefaultHandler (void)
 
static __attribute__ ((section("vtable")))
 
bool IntMasterDisable (void)
 
void IntRegister (uint32_t ui32Interrupt, void(*pfnHandler)(void))
 
void IntUnregister (uint32_t ui32Interrupt)
 
void IntPriorityGroupingSet (uint32_t ui32Bits)
 
uint32_t IntPriorityGroupingGet (void)
 
void IntPrioritySet (uint32_t ui32Interrupt, uint8_t ui8Priority)
 
int32_t IntPriorityGet (uint32_t ui32Interrupt)
 
void IntEnable (uint32_t ui32Interrupt)
 
void IntDisable (uint32_t ui32Interrupt)
 
uint32_t IntIsEnabled (uint32_t ui32Interrupt)
 
void IntPendSet (uint32_t ui32Interrupt)
 
void IntPendClear (uint32_t ui32Interrupt)
 
void IntPriorityMaskSet (uint32_t ui32PriorityMask)
 
uint32_t IntPriorityMaskGet (void)
 
void IntTrigger (uint32_t ui32Interrupt)
 

Variables

static const uint32_t g_pui32Priority []
 
static const uint32_t g_pui32Regs []
 
static const uint32_t g_pui32EnRegs []
 
static const uint32_t g_pui32Dii16Regs []
 
static const uint32_t g_pui32PendRegs []
 
static const uint32_t g_pui32UnpendRegs []
 

Detailed Description

Macro Definition Documentation

#define NUM_INTERRUPTS   155

Function Documentation

static __attribute__ ( (section("vtable"))  )
static

Enables the processor interrupt.

This function allows the processor to respond to interrupts. This function does not affect the set of interrupts enabled in the interrupt controller; it just gates the single interrupt from the controller to the processor.

Example: Enable interrupts to the processor.

//! //
//! // Enable interrupts to the processor.
//! //
//! IntMasterEnable();
//!
//! 
\return Returns \b true if interrupts were disabled when the function was
called or \b false if they were initially enabled.  

Definition at line 184 of file interrupt.c.

References CPUcpsie().

212 {
213  //
214  // Enable processor interrupts.
215  //
216  return(CPUcpsie());
217 }
uint32_t CPUcpsie(void)

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static void _IntDefaultHandler ( void  )
static

Definition at line 147 of file interrupt.c.

Referenced by IntUnregister().

148 {
149  //
150  // Go into an infinite loop.
151  //
152  while(1)
153  {
154  }
155 }

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void IntDisable ( uint32_t  ui32Interrupt)

Disables an interrupt.

Parameters
ui32Interruptspecifies the interrupt to be disabled.

The specified interrupt is disabled in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. Other enables for the interrupt (such as at the peripheral level) are unaffected by this function.

Example: Disable the UART 0 interrupt.

//! //
//! // Disable the UART 0 interrupt in the interrupt controller.
//! //
//! IntDisable(INT_UART0);
//!
//! 
\return None.  

Definition at line 684 of file interrupt.c.

References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, g_pui32Dii16Regs, HWREG, NUM_INTERRUPTS, NVIC_ST_CTRL, NVIC_ST_CTRL_INTEN, NVIC_SYS_HND_CTRL, NVIC_SYS_HND_CTRL_BUS, NVIC_SYS_HND_CTRL_MEM, and NVIC_SYS_HND_CTRL_USAGE.

Referenced by ADCIntUnregister(), AESIntUnregister(), button_set_interrupt(), CANIntUnregister(), ComparatorIntUnregister(), DESIntUnregister(), EMACIntUnregister(), EPIIntUnregister(), FlashIntUnregister(), GPIOIntUnregister(), HibernateIntUnregister(), I2CIntUnregister(), LCDIntUnregister(), MPUIntUnregister(), PWMFaultIntUnregister(), PWMGenIntUnregister(), QEIIntUnregister(), SHAMD5IntUnregister(), SSIIntUnregister(), SysCtlIntUnregister(), SysExcIntUnregister(), TimerIntUnregister(), UARTIntUnregister(), uDMAIntUnregister(), USBIntUnregister(), and WatchdogIntUnregister().

685 {
686  //
687  // Check the arguments.
688  //
689  ASSERT(ui32Interrupt < NUM_INTERRUPTS);
690 
691  //
692  // Determine the interrupt to disable.
693  //
694  if(ui32Interrupt == FAULT_MPU)
695  {
696  //
697  // Disable the MemManage interrupt.
698  //
700  }
701  else if(ui32Interrupt == FAULT_BUS)
702  {
703  //
704  // Disable the bus fault interrupt.
705  //
707  }
708  else if(ui32Interrupt == FAULT_USAGE)
709  {
710  //
711  // Disable the usage fault interrupt.
712  //
714  }
715  else if(ui32Interrupt == FAULT_SYSTICK)
716  {
717  //
718  // Disable the System Tick interrupt.
719  //
721  }
722  else if(ui32Interrupt >= 16)
723  {
724  //
725  // Disable the general interrupt.
726  //
727  HWREG(g_pui32Dii16Regs[(ui32Interrupt - 16) / 32]) =
728  1 << ((ui32Interrupt - 16) & 31);
729  }
730 }
#define HWREG(x)
Definition: hw_types.h:48
#define FAULT_SYSTICK
Definition: hw_ints.h:57
#define NVIC_ST_CTRL
Definition: hw_nvic.h:49
#define ASSERT(expr)
Definition: debug.h:67
#define FAULT_MPU
Definition: hw_ints.h:51
#define FAULT_BUS
Definition: hw_ints.h:52
#define NVIC_SYS_HND_CTRL_BUS
Definition: hw_nvic.h:1004
#define NVIC_SYS_HND_CTRL_USAGE
Definition: hw_nvic.h:1003
#define NVIC_SYS_HND_CTRL
Definition: hw_nvic.h:123
#define NVIC_ST_CTRL_INTEN
Definition: hw_nvic.h:174
static const uint32_t g_pui32Dii16Regs[]
Definition: interrupt.c:105
#define NUM_INTERRUPTS
Definition: interrupt.c:172
#define NVIC_SYS_HND_CTRL_MEM
Definition: hw_nvic.h:1005
#define FAULT_USAGE
Definition: hw_ints.h:53

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void IntEnable ( uint32_t  ui32Interrupt)

Enables an interrupt.

Parameters
ui32Interruptspecifies the interrupt to be enabled.

The specified interrupt is enabled in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. Other enables for the interrupt (such as at the peripheral level) are unaffected by this function.

Example: Enable the UART 0 interrupt.

//! //
//! // Enable the UART 0 interrupt in the interrupt controller.
//! //
//! IntEnable(INT_UART0);
//!
//! 
\return None.  

Definition at line 610 of file interrupt.c.

References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, g_pui32EnRegs, HWREG, NUM_INTERRUPTS, NVIC_ST_CTRL, NVIC_ST_CTRL_INTEN, NVIC_SYS_HND_CTRL, NVIC_SYS_HND_CTRL_BUS, NVIC_SYS_HND_CTRL_MEM, and NVIC_SYS_HND_CTRL_USAGE.

Referenced by adc_interrupt_init(), ADCIntRegister(), AESIntRegister(), button_set_interrupt(), CANIntRegister(), ComparatorIntRegister(), DESIntRegister(), EMACIntRegister(), EPIIntRegister(), FlashIntRegister(), GPIOIntRegister(), HibernateIntRegister(), I2CIntRegister(), LCDIntRegister(), main(), MPUIntRegister(), PWMFaultIntRegister(), PWMGenIntRegister(), QEIIntRegister(), SHAMD5IntRegister(), SSIIntRegister(), SysCtlIntRegister(), SysExcIntRegister(), timer_add_interrupt(), TimerIntRegister(), uart_init(), UARTIntRegister(), uDMAIntRegister(), USBIntRegister(), and WatchdogIntRegister().

611 {
612  //
613  // Check the arguments.
614  //
615  ASSERT(ui32Interrupt < NUM_INTERRUPTS);
616 
617  //
618  // Determine the interrupt to enable.
619  //
620  if(ui32Interrupt == FAULT_MPU)
621  {
622  //
623  // Enable the MemManage interrupt.
624  //
626  }
627  else if(ui32Interrupt == FAULT_BUS)
628  {
629  //
630  // Enable the bus fault interrupt.
631  //
633  }
634  else if(ui32Interrupt == FAULT_USAGE)
635  {
636  //
637  // Enable the usage fault interrupt.
638  //
640  }
641  else if(ui32Interrupt == FAULT_SYSTICK)
642  {
643  //
644  // Enable the System Tick interrupt.
645  //
647  }
648  else if(ui32Interrupt >= 16)
649  {
650  //
651  // Enable the general interrupt.
652  //
653  HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) =
654  1 << ((ui32Interrupt - 16) & 31);
655  }
656 }
#define HWREG(x)
Definition: hw_types.h:48
#define FAULT_SYSTICK
Definition: hw_ints.h:57
#define NVIC_ST_CTRL
Definition: hw_nvic.h:49
#define ASSERT(expr)
Definition: debug.h:67
#define FAULT_MPU
Definition: hw_ints.h:51
#define FAULT_BUS
Definition: hw_ints.h:52
#define NVIC_SYS_HND_CTRL_BUS
Definition: hw_nvic.h:1004
#define NVIC_SYS_HND_CTRL_USAGE
Definition: hw_nvic.h:1003
#define NVIC_SYS_HND_CTRL
Definition: hw_nvic.h:123
#define NVIC_ST_CTRL_INTEN
Definition: hw_nvic.h:174
#define NUM_INTERRUPTS
Definition: interrupt.c:172
#define NVIC_SYS_HND_CTRL_MEM
Definition: hw_nvic.h:1005
static const uint32_t g_pui32EnRegs[]
Definition: interrupt.c:93
#define FAULT_USAGE
Definition: hw_ints.h:53

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uint32_t IntIsEnabled ( uint32_t  ui32Interrupt)

Returns if a peripheral interrupt is enabled.

Parameters
ui32Interruptspecifies the interrupt to check.

This function checks if the specified interrupt is enabled in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file.

Example: Disable the UART 0 interrupt if it is enabled.

//! //
//! // Disable the UART 0 interrupt if it is enabled.
//! //
//! if(IntIsEnabled(INT_UART0))
//! {
//!     IntDisable(INT_UART0);
//! }
//! 
\return A non-zero value if the interrupt is enabled.  

Definition at line 759 of file interrupt.c.

References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, g_pui32EnRegs, HWREG, NUM_INTERRUPTS, NVIC_ST_CTRL, NVIC_ST_CTRL_INTEN, NVIC_SYS_HND_CTRL, NVIC_SYS_HND_CTRL_BUS, NVIC_SYS_HND_CTRL_MEM, and NVIC_SYS_HND_CTRL_USAGE.

760 {
761  uint32_t ui32Ret;
762 
763  //
764  // Check the arguments.
765  //
766  ASSERT(ui32Interrupt < NUM_INTERRUPTS);
767 
768  //
769  // Initialize the return value.
770  //
771  ui32Ret = 0;
772 
773  //
774  // Determine the interrupt to disable.
775  //
776  if(ui32Interrupt == FAULT_MPU)
777  {
778  //
779  // Check the MemManage interrupt.
780  //
782  }
783  else if(ui32Interrupt == FAULT_BUS)
784  {
785  //
786  // Check the bus fault interrupt.
787  //
789  }
790  else if(ui32Interrupt == FAULT_USAGE)
791  {
792  //
793  // Check the usage fault interrupt.
794  //
796  }
797  else if(ui32Interrupt == FAULT_SYSTICK)
798  {
799  //
800  // Check the System Tick interrupt.
801  //
803  }
804  else if(ui32Interrupt >= 16)
805  {
806  //
807  // Check the general interrupt.
808  //
809  ui32Ret = HWREG(g_pui32EnRegs[(ui32Interrupt - 16) / 32]) &
810  (1 << ((ui32Interrupt - 16) & 31));
811  }
812  return(ui32Ret);
813 }
#define HWREG(x)
Definition: hw_types.h:48
#define FAULT_SYSTICK
Definition: hw_ints.h:57
#define NVIC_ST_CTRL
Definition: hw_nvic.h:49
#define ASSERT(expr)
Definition: debug.h:67
#define FAULT_MPU
Definition: hw_ints.h:51
#define FAULT_BUS
Definition: hw_ints.h:52
#define NVIC_SYS_HND_CTRL_BUS
Definition: hw_nvic.h:1004
#define NVIC_SYS_HND_CTRL_USAGE
Definition: hw_nvic.h:1003
#define NVIC_SYS_HND_CTRL
Definition: hw_nvic.h:123
#define NVIC_ST_CTRL_INTEN
Definition: hw_nvic.h:174
#define NUM_INTERRUPTS
Definition: interrupt.c:172
#define NVIC_SYS_HND_CTRL_MEM
Definition: hw_nvic.h:1005
static const uint32_t g_pui32EnRegs[]
Definition: interrupt.c:93
#define FAULT_USAGE
Definition: hw_ints.h:53
bool IntMasterDisable ( void  )

Disables the processor interrupt.

This function prevents the processor from receiving interrupts. This function does not affect the set of interrupts enabled in the interrupt controller; it just gates the single interrupt from the controller to the processor.

Note
Previously, this function had no return value. As such, it was possible to include interrupt.h and call this function without having included hw_types.h. Now that the return is a bool, a compiler error occurs in this case. The solution is to include hw_types.h before including interrupt.h.

Example: Disable interrupts to the processor.

//! //
//! // Disable interrupts to the processor.
//! //
//! IntMasterDisable();
//!
//! 
\return Returns \b true if interrupts were already disabled when the
function was called or \b false if they were initially enabled.  

Definition at line 249 of file interrupt.c.

References CPUcpsid().

Referenced by main().

250 {
251  //
252  // Disable processor interrupts.
253  //
254  return(CPUcpsid());
255 }
uint32_t CPUcpsid(void)

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void IntPendClear ( uint32_t  ui32Interrupt)

Un-pends an interrupt.

Parameters
ui32Interruptspecifies the interrupt to be un-pended. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file.

The specified interrupt is un-pended in the interrupt controller. This causes any previously generated interrupts that have not been handled yet (due to higher priority interrupts or the interrupt not having been enabled yet) to be discarded.

Example: Un-pend a UART 0 interrupt.

//! //
//! // Un-pend a UART 0 interrupt.
//! //
//! IntPendClear(INT_UART0);
//! 
\return None.  

Definition at line 912 of file interrupt.c.

References ASSERT, FAULT_PENDSV, FAULT_SYSTICK, g_pui32UnpendRegs, HWREG, NUM_INTERRUPTS, NVIC_INT_CTRL, NVIC_INT_CTRL_PENDSTCLR, and NVIC_INT_CTRL_UNPEND_SV.

913 {
914  //
915  // Check the arguments.
916  //
917  ASSERT(ui32Interrupt < NUM_INTERRUPTS);
918 
919  //
920  // Determine the interrupt to unpend.
921  //
922  if(ui32Interrupt == FAULT_PENDSV)
923  {
924  //
925  // Unpend the PendSV interrupt.
926  //
928  }
929  else if(ui32Interrupt == FAULT_SYSTICK)
930  {
931  //
932  // Unpend the SysTick interrupt.
933  //
935  }
936  else if(ui32Interrupt >= 16)
937  {
938  //
939  // Unpend the general interrupt.
940  //
941  HWREG(g_pui32UnpendRegs[(ui32Interrupt - 16) / 32]) =
942  1 << ((ui32Interrupt - 16) & 31);
943  }
944 }
#define NVIC_INT_CTRL
Definition: hw_nvic.h:114
#define HWREG(x)
Definition: hw_types.h:48
#define FAULT_SYSTICK
Definition: hw_ints.h:57
#define NVIC_INT_CTRL_UNPEND_SV
Definition: hw_nvic.h:887
#define ASSERT(expr)
Definition: debug.h:67
#define NUM_INTERRUPTS
Definition: interrupt.c:172
#define NVIC_INT_CTRL_PENDSTCLR
Definition: hw_nvic.h:889
static const uint32_t g_pui32UnpendRegs[]
Definition: interrupt.c:128
#define FAULT_PENDSV
Definition: hw_ints.h:56
void IntPendSet ( uint32_t  ui32Interrupt)

Pends an interrupt.

Parameters
ui32Interruptspecifies the interrupt to be pended.

The specified interrupt is pended in the interrupt controller. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. Pending an interrupt causes the interrupt controller to execute the corresponding interrupt handler at the next available time, based on the current interrupt state priorities. For example, if called by a higher priority interrupt handler, the specified interrupt handler is not called until after the current interrupt handler has completed execution. The interrupt must have been enabled for it to be called.

Example: Pend a UART 0 interrupt.

//! //
//! // Pend a UART 0 interrupt.
//! //
//! IntPendSet(INT_UART0);
//! 
\return None.  

Definition at line 844 of file interrupt.c.

References ASSERT, FAULT_NMI, FAULT_PENDSV, FAULT_SYSTICK, g_pui32PendRegs, HWREG, NUM_INTERRUPTS, NVIC_INT_CTRL, NVIC_INT_CTRL_NMI_SET, NVIC_INT_CTRL_PEND_SV, and NVIC_INT_CTRL_PENDSTSET.

Referenced by scheduler_reschedule(), and Task1().

845 {
846  //
847  // Check the arguments.
848  //
849  ASSERT(ui32Interrupt < NUM_INTERRUPTS);
850 
851  //
852  // Determine the interrupt to pend.
853  //
854  if(ui32Interrupt == FAULT_NMI)
855  {
856  //
857  // Pend the NMI interrupt.
858  //
860  }
861  else if(ui32Interrupt == FAULT_PENDSV)
862  {
863  //
864  // Pend the PendSV interrupt.
865  //
867  }
868  else if(ui32Interrupt == FAULT_SYSTICK)
869  {
870  //
871  // Pend the SysTick interrupt.
872  //
874  }
875  else if(ui32Interrupt >= 16)
876  {
877  //
878  // Pend the general interrupt.
879  //
880  HWREG(g_pui32PendRegs[(ui32Interrupt - 16) / 32]) =
881  1 << ((ui32Interrupt - 16) & 31);
882  }
883 }
#define NVIC_INT_CTRL
Definition: hw_nvic.h:114
#define NVIC_INT_CTRL_NMI_SET
Definition: hw_nvic.h:885
#define FAULT_NMI
Definition: hw_ints.h:49
#define HWREG(x)
Definition: hw_types.h:48
#define FAULT_SYSTICK
Definition: hw_ints.h:57
#define NVIC_INT_CTRL_PENDSTSET
Definition: hw_nvic.h:888
#define ASSERT(expr)
Definition: debug.h:67
static const uint32_t g_pui32PendRegs[]
Definition: interrupt.c:116
#define NVIC_INT_CTRL_PEND_SV
Definition: hw_nvic.h:886
#define NUM_INTERRUPTS
Definition: interrupt.c:172
#define FAULT_PENDSV
Definition: hw_ints.h:56

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int32_t IntPriorityGet ( uint32_t  ui32Interrupt)

Gets the priority of an interrupt.

Parameters
ui32Interruptspecifies the interrupt in question.

This function gets the priority of an interrupt. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. See IntPrioritySet() for a full definition of the priority value.

Example: Get the current UART 0 interrupt priority.

//! //
//! // Get the current UART 0 interrupt priority.
//! //
//! IntPriorityGet(INT_UART0);
//!
//! 
\return Returns the interrupt priority for the given interrupt.  

Definition at line 570 of file interrupt.c.

References ASSERT, g_pui32Regs, HWREG, and NUM_INTERRUPTS.

571 {
572  //
573  // Check the arguments.
574  //
575  ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
576 
577  //
578  // Return the interrupt priority.
579  //
580  return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >>
581  (8 * (ui32Interrupt & 3))) & 0xFF);
582 }
static const uint32_t g_pui32Regs[]
Definition: interrupt.c:75
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define NUM_INTERRUPTS
Definition: interrupt.c:172
uint32_t IntPriorityGroupingGet ( void  )

Gets the priority grouping of the interrupt controller.

This function returns the split between preemptable priority levels and sub-priority levels in the interrupt priority specification.

Example: Get the priority grouping for the interrupt controller.

//! //
//! // Get the priority grouping for the interrupt controller.
//! //
//! IntPriorityGroupingGet();
//!
//! 
\return The number of bits of preemptable priority.  

Definition at line 455 of file interrupt.c.

References g_pui32Priority, HWREG, NUM_PRIORITY, NVIC_APINT, and NVIC_APINT_PRIGROUP_M.

456 {
457  uint32_t ui32Loop, ui32Value;
458 
459  //
460  // Read the priority grouping.
461  //
462  ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
463 
464  //
465  // Loop through the priority grouping values.
466  //
467  for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++)
468  {
469  //
470  // Stop looping if this value matches.
471  //
472  if(ui32Value == g_pui32Priority[ui32Loop])
473  {
474  break;
475  }
476  }
477 
478  //
479  // Return the number of priority bits.
480  //
481  return(ui32Loop);
482 }
#define NVIC_APINT
Definition: hw_nvic.h:116
#define NUM_PRIORITY
Definition: hw_ints.h:488
#define HWREG(x)
Definition: hw_types.h:48
#define NVIC_APINT_PRIGROUP_M
Definition: hw_nvic.h:929
static const uint32_t g_pui32Priority[]
Definition: interrupt.c:62
void IntPriorityGroupingSet ( uint32_t  ui32Bits)

Sets the priority grouping of the interrupt controller.

Parameters
ui32Bitsspecifies the number of bits of preemptable priority.

This function specifies the split between preemptable priority levels and sub-priority levels in the interrupt priority specification. The range of the grouping values are dependent upon the hardware implementation; on the Tiva C and E Series family, three bits are available for hardware interrupt prioritization and therefore priority grouping values of three through seven have the same effect.

Example: Set the priority grouping for the interrupt controller.

//! //
//! // Set the priority grouping for the interrupt controller to 2 bits.
//! //
//! IntPriorityGroupingSet(2);
//!
//! 
\return None.  

Definition at line 421 of file interrupt.c.

References ASSERT, g_pui32Priority, HWREG, NUM_PRIORITY, NVIC_APINT, and NVIC_APINT_VECTKEY.

422 {
423  //
424  // Check the arguments.
425  //
426  ASSERT(ui32Bits < NUM_PRIORITY);
427 
428  //
429  // Set the priority grouping.
430  //
432 }
#define NVIC_APINT
Definition: hw_nvic.h:116
#define NUM_PRIORITY
Definition: hw_ints.h:488
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define NVIC_APINT_VECTKEY
Definition: hw_nvic.h:927
static const uint32_t g_pui32Priority[]
Definition: interrupt.c:62
uint32_t IntPriorityMaskGet ( void  )

Gets the priority masking level

This function gets the current setting of the interrupt priority masking level. The value returned is the priority level such that all interrupts of that and lesser priority are masked. A value of 0 means that priority masking is disabled.

Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 allows interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater are blocked.

The hardware priority mechanism only looks at the upper 3 bits of the priority level, so any prioritization must be performed in those bits.

Example: Get the current interrupt priority mask.

//! //
//! // Get the current interrupt priority mask.
//! //
//! IntPriorityMaskGet();
//! 
\return Returns the value of the interrupt priority level mask.  

Definition at line 1015 of file interrupt.c.

References CPUbasepriGet().

1016 {
1017  //
1018  // Return the current priority mask.
1019  //
1020  return(CPUbasepriGet());
1021 }
uint32_t CPUbasepriGet(void)

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void IntPriorityMaskSet ( uint32_t  ui32PriorityMask)

Sets the priority masking level

Parameters
ui32PriorityMaskis the priority level that is masked.

This function sets the interrupt priority masking level so that all interrupts at the specified or lesser priority level are masked. Masking interrupts can be used to globally disable a set of interrupts with priority below a predetermined threshold. A value of 0 disables priority masking.

Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 allows interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater are blocked.

Note
The hardware priority mechanism only looks at the upper 3 bits of the priority level, so any prioritization must be performed in those bits.

Example: Mask of interrupt priorities greater than or equal to 0x80.

//! //
//! // Mask of interrupt priorities greater than or equal to 0x80.
//! //
//! IntPriorityMaskSet(0x80);
//! 
\return None.  

Definition at line 978 of file interrupt.c.

References CPUbasepriSet().

979 {
980  //
981  // Set the priority mask.
982  //
983  CPUbasepriSet(ui32PriorityMask);
984 }
void CPUbasepriSet(uint32_t ui32NewBasepri)

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void IntPrioritySet ( uint32_t  ui32Interrupt,
uint8_t  ui8Priority 
)

Sets the priority of an interrupt.

Parameters
ui32Interruptspecifies the interrupt in question.
ui8Priorityspecifies the priority of the interrupt.

This function is used to set the priority of an interrupt. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. The ui8Priority parameter specifies the interrupts hardware priority level of the interrupt in the interrupt controller. When multiple interrupts are asserted simultaneously, the ones with the highest priority are processed before the lower priority interrupts. Smaller numbers correspond to higher interrupt priorities; priority 0 is the highest interrupt priority.

Note
The hardware priority mechanism only looks at the upper 3 bits of the priority level, so any prioritization must be performed in those bits. The remaining bits can be used to sub-prioritize the interrupt sources, and may be used by the hardware priority mechanism on a future part. This arrangement allows priorities to migrate to different NVIC implementations without changing the gross prioritization of the interrupts.

Example: Set priorities for UART 0 and USB interrupts.

//! //
//! // Set the UART 0 interrupt priority to the lowest priority.
//! //
//! IntPrioritySet(INT_UART0, 0xE0);
//!
//! //
//! // Set the USB 0 interrupt priority to the highest priority.
//! //
//! IntPrioritySet(INT_USB0, 0);
//!
//! 
\return None.  

Definition at line 527 of file interrupt.c.

References ASSERT, g_pui32Regs, HWREG, and NUM_INTERRUPTS.

528 {
529  uint32_t ui32Temp;
530 
531  //
532  // Check the arguments.
533  //
534  ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
535 
536  //
537  // Set the interrupt priority.
538  //
539  ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]);
540  ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3)));
541  ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3));
542  HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp;
543 }
static const uint32_t g_pui32Regs[]
Definition: interrupt.c:75
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define NUM_INTERRUPTS
Definition: interrupt.c:172
void IntRegister ( uint32_t  ui32Interrupt,
void(*)(void)  pfnHandler 
)

Registers a function to be called when an interrupt occurs.

Parameters
ui32Interruptspecifies the interrupt in question.
pfnHandleris a pointer to the function to be called.

This function is used to specify the handler function to be called when the given interrupt is asserted to the processor. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. When the interrupt occurs, if it is enabled (via IntEnable()), the handler function is called in interrupt context. Because the handler function can preempt other code, care must be taken to protect memory or peripherals that are accessed by the handler and other non-handler code.

Note
The use of this function (directly or indirectly via a peripheral driver interrupt register function) moves the interrupt vector table from flash to SRAM. Therefore, care must be taken when linking the application to ensure that the SRAM vector table is located at the beginning of SRAM; otherwise the NVIC does not look in the correct portion of memory for the vector table (it requires the vector table be on a 1 kB memory alignment). Normally, the SRAM vector table is so placed via the use of linker scripts. See the discussion of compile-time versus run-time interrupt handler registration in the introduction to this chapter.

Example: Set the UART 0 interrupt handler.

//!
//! //
//! // UART 0 interrupt handler.
//! //
//! void
//! UART0Handler(void)
//! {
//!     //
//!     // Handle interrupt.
//!     //
//! }
//!
//! //
//! // Set the UART 0 interrupt handler.
//! //
//! IntRegister(INT_UART0, UART0Handler);
//!
//! 
\return None.  

Definition at line 309 of file interrupt.c.

References ASSERT, HWREG, NUM_INTERRUPTS, and NVIC_VTABLE.

Referenced by ADCIntRegister(), AESIntRegister(), CANIntRegister(), ComparatorIntRegister(), DESIntRegister(), EMACIntRegister(), EPIIntRegister(), FlashIntRegister(), GPIOIntRegister(), HibernateIntRegister(), I2CIntRegister(), LCDIntRegister(), MPUIntRegister(), PWMFaultIntRegister(), PWMGenIntRegister(), QEIIntRegister(), SHAMD5IntRegister(), SSIIntRegister(), SysCtlIntRegister(), SysExcIntRegister(), SysTickIntRegister(), TimerIntRegister(), UARTIntRegister(), uDMAIntRegister(), USBIntRegister(), and WatchdogIntRegister().

310 {
311  uint32_t ui32Idx, ui32Value;
312 
313  //
314  // Check the arguments.
315  //
316  ASSERT(ui32Interrupt < NUM_INTERRUPTS);
317 
318  //
319  // Make sure that the RAM vector table is correctly aligned.
320  //
321  ASSERT(((uint32_t)g_pfnRAMVectors & 0x000003ff) == 0);
322 
323  //
324  // See if the RAM vector table has been initialized.
325  //
326  if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors)
327  {
328  //
329  // Copy the vector table from the beginning of FLASH to the RAM vector
330  // table.
331  //
332  ui32Value = HWREG(NVIC_VTABLE);
333  for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++)
334  {
335  g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) +
336  ui32Value);
337  }
338 
339  //
340  // Point the NVIC at the RAM vector table.
341  //
342  HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors;
343  }
344 
345  //
346  // Save the interrupt handler.
347  //
348  g_pfnRAMVectors[ui32Interrupt] = pfnHandler;
349 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define NVIC_VTABLE
Definition: hw_nvic.h:115
#define NUM_INTERRUPTS
Definition: interrupt.c:172

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void IntTrigger ( uint32_t  ui32Interrupt)

Triggers an interrupt.

Parameters
ui32Interruptspecifies the interrupt to be triggered.

This function performs a software trigger of an interrupt. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. The interrupt controller behaves as if the corresponding interrupt line was asserted, and the interrupt is handled in the same manner (meaning that it must be enabled in order to be processed, and the processing is based on its priority with respect to other unhandled interrupts).

Returns
None.

Definition at line 1042 of file interrupt.c.

References ASSERT, HWREG, NUM_INTERRUPTS, and NVIC_SW_TRIG.

1043 {
1044  //
1045  // Check the arguments.
1046  //
1047  ASSERT((ui32Interrupt >= 16) && (ui32Interrupt < NUM_INTERRUPTS));
1048 
1049  //
1050  // Trigger this interrupt.
1051  //
1052  HWREG(NVIC_SW_TRIG) = ui32Interrupt - 16;
1053 }
#define HWREG(x)
Definition: hw_types.h:48
#define NVIC_SW_TRIG
Definition: hw_nvic.h:148
#define ASSERT(expr)
Definition: debug.h:67
#define NUM_INTERRUPTS
Definition: interrupt.c:172
void IntUnregister ( uint32_t  ui32Interrupt)

Unregisters the function to be called when an interrupt occurs.

Parameters
ui32Interruptspecifies the interrupt in question.

This function is used to indicate that no handler is called when the given interrupt is asserted to the processor. The ui32Interrupt parameter must be one of the valid INT_* values listed in Peripheral Driver Library User's Guide and defined in the inc/hw_ints.h header file. The interrupt source is automatically disabled (via IntDisable()) if necessary.

See also
IntRegister() for important information about registering interrupt handlers.

Example: Reset the UART 0 interrupt handler to the default handler.

//! //
//! // Reset the UART 0 interrupt handler to the default handler.
//! //
//! IntUnregister(INT_UART0);
//!
//! 
\return None.  

Definition at line 381 of file interrupt.c.

References _IntDefaultHandler(), ASSERT, and NUM_INTERRUPTS.

Referenced by ADCIntUnregister(), AESIntUnregister(), CANIntUnregister(), ComparatorIntUnregister(), DESIntUnregister(), EMACIntUnregister(), EPIIntUnregister(), FlashIntUnregister(), GPIOIntUnregister(), HibernateIntUnregister(), I2CIntUnregister(), LCDIntUnregister(), MPUIntUnregister(), PWMFaultIntUnregister(), PWMGenIntUnregister(), QEIIntUnregister(), SHAMD5IntUnregister(), SSIIntUnregister(), SysCtlIntUnregister(), SysExcIntUnregister(), SysTickIntUnregister(), TimerIntUnregister(), UARTIntUnregister(), uDMAIntUnregister(), USBIntUnregister(), and WatchdogIntUnregister().

382 {
383  //
384  // Check the arguments.
385  //
386  ASSERT(ui32Interrupt < NUM_INTERRUPTS);
387 
388  //
389  // Reset the interrupt handler.
390  //
391  g_pfnRAMVectors[ui32Interrupt] = _IntDefaultHandler;
392 }
static void _IntDefaultHandler(void)
Definition: interrupt.c:147
#define ASSERT(expr)
Definition: debug.h:67
#define NUM_INTERRUPTS
Definition: interrupt.c:172

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Variable Documentation

const uint32_t g_pui32Dii16Regs[]
static
Initial value:
=
{
}
#define NVIC_DIS1
Definition: hw_nvic.h:59
#define NVIC_DIS4
Definition: hw_nvic.h:62
#define NVIC_DIS2
Definition: hw_nvic.h:60
#define NVIC_DIS3
Definition: hw_nvic.h:61
#define NVIC_DIS0
Definition: hw_nvic.h:58

Definition at line 105 of file interrupt.c.

Referenced by IntDisable().

const uint32_t g_pui32EnRegs[]
static
Initial value:
=
{
}
#define NVIC_EN2
Definition: hw_nvic.h:55
#define NVIC_EN3
Definition: hw_nvic.h:56
#define NVIC_EN0
Definition: hw_nvic.h:53
#define NVIC_EN4
Definition: hw_nvic.h:57
#define NVIC_EN1
Definition: hw_nvic.h:54

Definition at line 93 of file interrupt.c.

Referenced by IntEnable(), and IntIsEnabled().

const uint32_t g_pui32PendRegs[]
static
Initial value:
=
{
}
#define NVIC_PEND1
Definition: hw_nvic.h:64
#define NVIC_PEND0
Definition: hw_nvic.h:63
#define NVIC_PEND3
Definition: hw_nvic.h:66
#define NVIC_PEND4
Definition: hw_nvic.h:67
#define NVIC_PEND2
Definition: hw_nvic.h:65

Definition at line 116 of file interrupt.c.

Referenced by IntPendSet().

const uint32_t g_pui32Priority[]
static
Initial value:
=
{
}
#define NVIC_APINT_PRIGROUP_3_5
Definition: hw_nvic.h:934
#define NVIC_APINT_PRIGROUP_4_4
Definition: hw_nvic.h:933
#define NVIC_APINT_PRIGROUP_5_3
Definition: hw_nvic.h:932
#define NVIC_APINT_PRIGROUP_0_8
Definition: hw_nvic.h:937
#define NVIC_APINT_PRIGROUP_6_2
Definition: hw_nvic.h:931
#define NVIC_APINT_PRIGROUP_1_7
Definition: hw_nvic.h:936
#define NVIC_APINT_PRIGROUP_2_6
Definition: hw_nvic.h:935
#define NVIC_APINT_PRIGROUP_7_1
Definition: hw_nvic.h:930

Definition at line 62 of file interrupt.c.

Referenced by IntPriorityGroupingGet(), and IntPriorityGroupingSet().

const uint32_t g_pui32Regs[]
static
Initial value:
=
{
}
#define NVIC_PRI32
Definition: hw_nvic.h:110
#define NVIC_PRI15
Definition: hw_nvic.h:93
#define NVIC_PRI18
Definition: hw_nvic.h:96
#define NVIC_PRI22
Definition: hw_nvic.h:100
#define NVIC_PRI24
Definition: hw_nvic.h:102
#define NVIC_SYS_PRI3
Definition: hw_nvic.h:122
#define NVIC_PRI19
Definition: hw_nvic.h:97
#define NVIC_PRI3
Definition: hw_nvic.h:81
#define NVIC_PRI6
Definition: hw_nvic.h:84
#define NVIC_PRI27
Definition: hw_nvic.h:105
#define NVIC_PRI25
Definition: hw_nvic.h:103
#define NVIC_PRI34
Definition: hw_nvic.h:112
#define NVIC_PRI5
Definition: hw_nvic.h:83
#define NVIC_PRI20
Definition: hw_nvic.h:98
#define NVIC_SYS_PRI1
Definition: hw_nvic.h:120
#define NVIC_PRI29
Definition: hw_nvic.h:107
#define NVIC_PRI13
Definition: hw_nvic.h:91
#define NVIC_PRI9
Definition: hw_nvic.h:87
#define NVIC_PRI7
Definition: hw_nvic.h:85
#define NVIC_PRI21
Definition: hw_nvic.h:99
#define NVIC_PRI17
Definition: hw_nvic.h:95
#define NVIC_SYS_PRI2
Definition: hw_nvic.h:121
#define NVIC_PRI28
Definition: hw_nvic.h:106
#define NVIC_PRI0
Definition: hw_nvic.h:78
#define NVIC_PRI2
Definition: hw_nvic.h:80
#define NVIC_PRI1
Definition: hw_nvic.h:79
#define NVIC_PRI12
Definition: hw_nvic.h:90
#define NVIC_PRI30
Definition: hw_nvic.h:108
#define NVIC_PRI33
Definition: hw_nvic.h:111
#define NVIC_PRI31
Definition: hw_nvic.h:109
#define NVIC_PRI10
Definition: hw_nvic.h:88
#define NVIC_PRI16
Definition: hw_nvic.h:94
#define NVIC_PRI8
Definition: hw_nvic.h:86
#define NVIC_PRI11
Definition: hw_nvic.h:89
#define NVIC_PRI26
Definition: hw_nvic.h:104
#define NVIC_PRI14
Definition: hw_nvic.h:92
#define NVIC_PRI4
Definition: hw_nvic.h:82
#define NVIC_PRI23
Definition: hw_nvic.h:101

Definition at line 75 of file interrupt.c.

Referenced by IntPriorityGet(), and IntPrioritySet().

const uint32_t g_pui32UnpendRegs[]
static
Initial value:
=
{
}
#define NVIC_UNPEND3
Definition: hw_nvic.h:71
#define NVIC_UNPEND0
Definition: hw_nvic.h:68
#define NVIC_UNPEND1
Definition: hw_nvic.h:69
#define NVIC_UNPEND2
Definition: hw_nvic.h:70
#define NVIC_UNPEND4
Definition: hw_nvic.h:72

Definition at line 128 of file interrupt.c.

Referenced by IntPendClear().