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#define | FAULT_NMI 2 |
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#define | FAULT_HARD 3 |
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#define | FAULT_MPU 4 |
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#define | FAULT_BUS 5 |
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#define | FAULT_USAGE 6 |
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#define | FAULT_SVCALL 11 |
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#define | FAULT_DEBUG 12 |
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#define | FAULT_PENDSV 14 |
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#define | FAULT_SYSTICK 15 |
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#define | INT_GPIOA_TM4C123 16 |
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#define | INT_GPIOB_TM4C123 17 |
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#define | INT_GPIOC_TM4C123 18 |
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#define | INT_GPIOD_TM4C123 19 |
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#define | INT_GPIOE_TM4C123 20 |
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#define | INT_UART0_TM4C123 21 |
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#define | INT_UART1_TM4C123 22 |
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#define | INT_SSI0_TM4C123 23 |
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#define | INT_I2C0_TM4C123 24 |
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#define | INT_PWM0_FAULT_TM4C123 25 |
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#define | INT_PWM0_0_TM4C123 26 |
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#define | INT_PWM0_1_TM4C123 27 |
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#define | INT_PWM0_2_TM4C123 28 |
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#define | INT_QEI0_TM4C123 29 |
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#define | INT_ADC0SS0_TM4C123 30 |
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#define | INT_ADC0SS1_TM4C123 31 |
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#define | INT_ADC0SS2_TM4C123 32 |
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#define | INT_ADC0SS3_TM4C123 33 |
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#define | INT_WATCHDOG_TM4C123 34 |
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#define | INT_TIMER0A_TM4C123 35 |
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#define | INT_TIMER0B_TM4C123 36 |
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#define | INT_TIMER1A_TM4C123 37 |
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#define | INT_TIMER1B_TM4C123 38 |
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#define | INT_TIMER2A_TM4C123 39 |
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#define | INT_TIMER2B_TM4C123 40 |
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#define | INT_COMP0_TM4C123 41 |
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#define | INT_COMP1_TM4C123 42 |
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#define | INT_COMP2_TM4C123 43 |
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#define | INT_SYSCTL_TM4C123 44 |
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#define | INT_FLASH_TM4C123 45 |
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#define | INT_GPIOF_TM4C123 46 |
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#define | INT_GPIOG_TM4C123 47 |
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#define | INT_GPIOH_TM4C123 48 |
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#define | INT_UART2_TM4C123 49 |
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#define | INT_SSI1_TM4C123 50 |
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#define | INT_TIMER3A_TM4C123 51 |
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#define | INT_TIMER3B_TM4C123 52 |
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#define | INT_I2C1_TM4C123 53 |
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#define | INT_QEI1_TM4C123 54 |
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#define | INT_CAN0_TM4C123 55 |
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#define | INT_CAN1_TM4C123 56 |
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#define | INT_HIBERNATE_TM4C123 59 |
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#define | INT_USB0_TM4C123 60 |
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#define | INT_PWM0_3_TM4C123 61 |
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#define | INT_UDMA_TM4C123 62 |
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#define | INT_UDMAERR_TM4C123 63 |
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#define | INT_ADC1SS0_TM4C123 64 |
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#define | INT_ADC1SS1_TM4C123 65 |
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#define | INT_ADC1SS2_TM4C123 66 |
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#define | INT_ADC1SS3_TM4C123 67 |
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#define | INT_GPIOJ_TM4C123 70 |
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#define | INT_GPIOK_TM4C123 71 |
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#define | INT_GPIOL_TM4C123 72 |
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#define | INT_SSI2_TM4C123 73 |
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#define | INT_SSI3_TM4C123 74 |
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#define | INT_UART3_TM4C123 75 |
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#define | INT_UART4_TM4C123 76 |
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#define | INT_UART5_TM4C123 77 |
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#define | INT_UART6_TM4C123 78 |
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#define | INT_UART7_TM4C123 79 |
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#define | INT_I2C2_TM4C123 84 |
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#define | INT_I2C3_TM4C123 85 |
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#define | INT_TIMER4A_TM4C123 86 |
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#define | INT_TIMER4B_TM4C123 87 |
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#define | INT_TIMER5A_TM4C123 108 |
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#define | INT_TIMER5B_TM4C123 109 |
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#define | INT_WTIMER0A_TM4C123 110 |
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#define | INT_WTIMER0B_TM4C123 111 |
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#define | INT_WTIMER1A_TM4C123 112 |
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#define | INT_WTIMER1B_TM4C123 113 |
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#define | INT_WTIMER2A_TM4C123 114 |
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#define | INT_WTIMER2B_TM4C123 115 |
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#define | INT_WTIMER3A_TM4C123 116 |
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#define | INT_WTIMER3B_TM4C123 117 |
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#define | INT_WTIMER4A_TM4C123 118 |
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#define | INT_WTIMER4B_TM4C123 119 |
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#define | INT_WTIMER5A_TM4C123 120 |
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#define | INT_WTIMER5B_TM4C123 121 |
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#define | INT_SYSEXC_TM4C123 122 |
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#define | INT_I2C4_TM4C123 125 |
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#define | INT_I2C5_TM4C123 126 |
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#define | INT_GPIOM_TM4C123 127 |
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#define | INT_GPION_TM4C123 128 |
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#define | INT_GPIOP0_TM4C123 132 |
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#define | INT_GPIOP1_TM4C123 133 |
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#define | INT_GPIOP2_TM4C123 134 |
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#define | INT_GPIOP3_TM4C123 135 |
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#define | INT_GPIOP4_TM4C123 136 |
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#define | INT_GPIOP5_TM4C123 137 |
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#define | INT_GPIOP6_TM4C123 138 |
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#define | INT_GPIOP7_TM4C123 139 |
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#define | INT_GPIOQ0_TM4C123 140 |
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#define | INT_GPIOQ1_TM4C123 141 |
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#define | INT_GPIOQ2_TM4C123 142 |
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#define | INT_GPIOQ3_TM4C123 143 |
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#define | INT_GPIOQ4_TM4C123 144 |
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#define | INT_GPIOQ5_TM4C123 145 |
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#define | INT_GPIOQ6_TM4C123 146 |
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#define | INT_GPIOQ7_TM4C123 147 |
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#define | INT_PWM1_0_TM4C123 150 |
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#define | INT_PWM1_1_TM4C123 151 |
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#define | INT_PWM1_2_TM4C123 152 |
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#define | INT_PWM1_3_TM4C123 153 |
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#define | INT_PWM1_FAULT_TM4C123 154 |
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#define | NUM_INTERRUPTS_TM4C123 155 |
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#define | INT_GPIOA_TM4C129 16 |
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#define | INT_GPIOB_TM4C129 17 |
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#define | INT_GPIOC_TM4C129 18 |
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#define | INT_GPIOD_TM4C129 19 |
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#define | INT_GPIOE_TM4C129 20 |
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#define | INT_UART0_TM4C129 21 |
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#define | INT_UART1_TM4C129 22 |
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#define | INT_SSI0_TM4C129 23 |
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#define | INT_I2C0_TM4C129 24 |
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#define | INT_PWM0_FAULT_TM4C129 25 |
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#define | INT_PWM0_0_TM4C129 26 |
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#define | INT_PWM0_1_TM4C129 27 |
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#define | INT_PWM0_2_TM4C129 28 |
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#define | INT_QEI0_TM4C129 29 |
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#define | INT_ADC0SS0_TM4C129 30 |
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#define | INT_ADC0SS1_TM4C129 31 |
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#define | INT_ADC0SS2_TM4C129 32 |
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#define | INT_ADC0SS3_TM4C129 33 |
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#define | INT_WATCHDOG_TM4C129 34 |
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#define | INT_TIMER0A_TM4C129 35 |
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#define | INT_TIMER0B_TM4C129 36 |
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#define | INT_TIMER1A_TM4C129 37 |
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#define | INT_TIMER1B_TM4C129 38 |
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#define | INT_TIMER2A_TM4C129 39 |
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#define | INT_TIMER2B_TM4C129 40 |
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#define | INT_COMP0_TM4C129 41 |
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#define | INT_COMP1_TM4C129 42 |
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#define | INT_COMP2_TM4C129 43 |
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#define | INT_SYSCTL_TM4C129 44 |
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#define | INT_FLASH_TM4C129 45 |
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#define | INT_GPIOF_TM4C129 46 |
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#define | INT_GPIOG_TM4C129 47 |
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#define | INT_GPIOH_TM4C129 48 |
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#define | INT_UART2_TM4C129 49 |
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#define | INT_SSI1_TM4C129 50 |
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#define | INT_TIMER3A_TM4C129 51 |
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#define | INT_TIMER3B_TM4C129 52 |
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#define | INT_I2C1_TM4C129 53 |
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#define | INT_CAN0_TM4C129 54 |
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#define | INT_CAN1_TM4C129 55 |
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#define | INT_EMAC0_TM4C129 56 |
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#define | INT_HIBERNATE_TM4C129 57 |
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#define | INT_USB0_TM4C129 58 |
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#define | INT_PWM0_3_TM4C129 59 |
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#define | INT_UDMA_TM4C129 60 |
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#define | INT_UDMAERR_TM4C129 61 |
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#define | INT_ADC1SS0_TM4C129 62 |
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#define | INT_ADC1SS1_TM4C129 63 |
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#define | INT_ADC1SS2_TM4C129 64 |
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#define | INT_ADC1SS3_TM4C129 65 |
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#define | INT_EPI0_TM4C129 66 |
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#define | INT_GPIOJ_TM4C129 67 |
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#define | INT_GPIOK_TM4C129 68 |
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#define | INT_GPIOL_TM4C129 69 |
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#define | INT_SSI2_TM4C129 70 |
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#define | INT_SSI3_TM4C129 71 |
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#define | INT_UART3_TM4C129 72 |
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#define | INT_UART4_TM4C129 73 |
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#define | INT_UART5_TM4C129 74 |
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#define | INT_UART6_TM4C129 75 |
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#define | INT_UART7_TM4C129 76 |
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#define | INT_I2C2_TM4C129 77 |
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#define | INT_I2C3_TM4C129 78 |
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#define | INT_TIMER4A_TM4C129 79 |
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#define | INT_TIMER4B_TM4C129 80 |
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#define | INT_TIMER5A_TM4C129 81 |
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#define | INT_TIMER5B_TM4C129 82 |
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#define | INT_SYSEXC_TM4C129 83 |
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#define | INT_I2C4_TM4C129 86 |
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#define | INT_I2C5_TM4C129 87 |
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#define | INT_GPIOM_TM4C129 88 |
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#define | INT_GPION_TM4C129 89 |
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#define | INT_TAMPER0_TM4C129 91 |
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#define | INT_GPIOP0_TM4C129 92 |
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#define | INT_GPIOP1_TM4C129 93 |
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#define | INT_GPIOP2_TM4C129 94 |
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#define | INT_GPIOP3_TM4C129 95 |
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#define | INT_GPIOP4_TM4C129 96 |
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#define | INT_GPIOP5_TM4C129 97 |
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#define | INT_GPIOP6_TM4C129 98 |
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#define | INT_GPIOP7_TM4C129 99 |
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#define | INT_GPIOQ0_TM4C129 100 |
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#define | INT_GPIOQ1_TM4C129 101 |
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#define | INT_GPIOQ2_TM4C129 102 |
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#define | INT_GPIOQ3_TM4C129 103 |
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#define | INT_GPIOQ4_TM4C129 104 |
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#define | INT_GPIOQ5_TM4C129 105 |
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#define | INT_GPIOQ6_TM4C129 106 |
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#define | INT_GPIOQ7_TM4C129 107 |
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#define | INT_GPIOR_TM4C129 108 |
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#define | INT_GPIOS_TM4C129 109 |
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#define | INT_SHA0_TM4C129 110 |
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#define | INT_AES0_TM4C129 111 |
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#define | INT_DES0_TM4C129 112 |
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#define | INT_LCD0_TM4C129 113 |
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#define | INT_TIMER6A_TM4C129 114 |
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#define | INT_TIMER6B_TM4C129 115 |
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#define | INT_TIMER7A_TM4C129 116 |
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#define | INT_TIMER7B_TM4C129 117 |
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#define | INT_I2C6_TM4C129 118 |
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#define | INT_I2C7_TM4C129 119 |
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#define | INT_ONEWIRE0_TM4C129 121 |
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#define | INT_I2C8_TM4C129 125 |
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#define | INT_I2C9_TM4C129 126 |
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#define | INT_GPIOT_TM4C129 127 |
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#define | NUM_INTERRUPTS_TM4C129 129 |
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#define | INT_DEVICE_CLASS "UNKNOWN" |
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#define | INT_CONCAT(intname, class) INT_RESOLVE(intname, class) |
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#define | INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) |
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#define | INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) |
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#define | INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) |
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#define | INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) |
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#define | INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) |
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#define | INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) |
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#define | INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) |
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#define | INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) |
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#define | INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) |
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#define | INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) |
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#define | INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) |
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#define | INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) |
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#define | INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) |
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#define | INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) |
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#define | INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) |
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#define | INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) |
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#define | INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) |
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#define | INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) |
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#define | INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) |
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#define | INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) |
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#define | INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) |
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#define | INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) |
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#define | INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) |
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#define | INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) |
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#define | INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) |
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#define | INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) |
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#define | INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) |
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#define | INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) |
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#define | INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) |
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#define | INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) |
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#define | INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) |
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#define | INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) |
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#define | INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) |
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#define | INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) |
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#define | INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) |
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#define | INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) |
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#define | INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) |
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#define | INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) |
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#define | INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) |
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#define | INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) |
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#define | INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) |
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#define | INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) |
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#define | INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) |
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#define | INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) |
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#define | INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) |
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#define | INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) |
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#define | INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) |
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#define | INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) |
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#define | INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) |
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#define | INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) |
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#define | INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) |
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#define | INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) |
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#define | INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) |
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#define | INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) |
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#define | INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) |
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#define | INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) |
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#define | INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) |
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#define | INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) |
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#define | INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) |
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#define | INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) |
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#define | INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) |
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#define | INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) |
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#define | INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) |
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#define | INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) |
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#define | INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) |
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#define | INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) |
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#define | INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) |
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#define | INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) |
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#define | INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) |
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#define | INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) |
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#define | INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) |
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#define | INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) |
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#define | INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) |
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#define | INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) |
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#define | INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) |
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#define | INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) |
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#define | INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) |
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#define | INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) |
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#define | INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) |
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#define | INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) |
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#define | INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) |
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#define | INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) |
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#define | INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) |
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#define | INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) |
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#define | INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) |
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#define | INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) |
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#define | INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) |
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#define | INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) |
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#define | INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) |
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#define | INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) |
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#define | INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) |
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#define | NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) |
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#define | NUM_PRIORITY 8 |
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#define | NUM_PRIORITY_BITS 3 |
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