EE445M RTOS
Taken at the University of Texas Spring 2015
udma.c
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1 //*****************************************************************************
2 //
3 // udma.c - Driver for the micro-DMA controller.
4 //
5 // Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved.
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35 //
36 // This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
37 //
38 //*****************************************************************************
39 
40 //*****************************************************************************
41 //
44 //
45 //*****************************************************************************
46 
47 #include <stdbool.h>
48 #include <stdint.h>
49 #include "inc/hw_sysctl.h"
50 #include "inc/hw_types.h"
51 #include "inc/hw_udma.h"
52 #include "driverlib/debug.h"
53 #include "driverlib/interrupt.h"
54 #include "driverlib/udma.h"
55 
56 //*****************************************************************************
57 //
64 //
65 //*****************************************************************************
66 void
68 {
69  //
70  // Set the master enable bit in the config register.
71  //
73 }
74 
75 //*****************************************************************************
76 //
83 //
84 //*****************************************************************************
85 void
87 {
88  //
89  // Clear the master enable bit in the config register.
90  //
91  HWREG(UDMA_CFG) = 0;
92 }
93 
94 //*****************************************************************************
95 //
103 //
104 //*****************************************************************************
105 uint32_t
107 {
108  //
109  // Return the uDMA error status.
110  //
111  return(HWREG(UDMA_ERRCLR));
112 }
113 
114 //*****************************************************************************
115 //
123 //
124 //*****************************************************************************
125 void
127 {
128  //
129  // Clear the uDMA error interrupt.
130  //
131  HWREG(UDMA_ERRCLR) = 1;
132 }
133 
134 //*****************************************************************************
135 //
149 //
150 //*****************************************************************************
151 void
152 uDMAChannelEnable(uint32_t ui32ChannelNum)
153 {
154  //
155  // Check the arguments.
156  //
157  ASSERT((ui32ChannelNum & 0xffff) < 32);
158 
159  //
160  // Set the bit for this channel in the enable set register.
161  //
162  HWREG(UDMA_ENASET) = 1 << (ui32ChannelNum & 0x1f);
163 }
164 
165 //*****************************************************************************
166 //
176 //
177 //*****************************************************************************
178 void
179 uDMAChannelDisable(uint32_t ui32ChannelNum)
180 {
181  //
182  // Check the arguments.
183  //
184  ASSERT((ui32ChannelNum & 0xffff) < 32);
185 
186  //
187  // Set the bit for this channel in the enable clear register.
188  //
189  HWREG(UDMA_ENACLR) = 1 << (ui32ChannelNum & 0x1f);
190 }
191 
192 //*****************************************************************************
193 //
203 //
204 //*****************************************************************************
205 bool
206 uDMAChannelIsEnabled(uint32_t ui32ChannelNum)
207 {
208  //
209  // Check the arguments.
210  //
211  ASSERT((ui32ChannelNum & 0xffff) < 32);
212 
213  //
214  // AND the specified channel bit with the enable register and return the
215  // result.
216  //
217  return((HWREG(UDMA_ENASET) & (1 << (ui32ChannelNum & 0x1f))) ? true :
218  false);
219 }
220 
221 //*****************************************************************************
222 //
239 //
240 //*****************************************************************************
241 void
242 uDMAControlBaseSet(void *psControlTable)
243 {
244  //
245  // Check the arguments.
246  //
247  ASSERT(((uint32_t)psControlTable & ~0x3FF) ==
248  (uint32_t)psControlTable);
249  ASSERT((uint32_t)psControlTable >= 0x20000000);
250 
251  //
252  // Program the base address into the register.
253  //
254  HWREG(UDMA_CTLBASE) = (uint32_t)psControlTable;
255 }
256 
257 //*****************************************************************************
258 //
266 //
267 //*****************************************************************************
268 void *
270 {
271  //
272  // Read the current value of the control base register and return it to
273  // the caller.
274  //
275  return((void *)HWREG(UDMA_CTLBASE));
276 }
277 
278 //*****************************************************************************
279 //
287 //
288 //*****************************************************************************
289 void *
291 {
292  //
293  // Read the current value of the control base register and return it to
294  // the caller.
295  //
296  return((void *)HWREG(UDMA_ALTBASE));
297 }
298 
299 //*****************************************************************************
300 //
317 //
318 //*****************************************************************************
319 void
320 uDMAChannelRequest(uint32_t ui32ChannelNum)
321 {
322  //
323  // Check the arguments.
324  //
325  ASSERT((ui32ChannelNum & 0xffff) < 32);
326 
327  //
328  // Set the bit for this channel in the software uDMA request register.
329  //
330  HWREG(UDMA_SWREQ) = 1 << (ui32ChannelNum & 0x1f);
331 }
332 
333 //*****************************************************************************
334 //
353 //
354 //*****************************************************************************
355 void
356 uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
357 {
358  //
359  // Check the arguments.
360  //
361  ASSERT((ui32ChannelNum & 0xffff) < 32);
364 
365  //
366  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
367  // passed as the ui32ChannelNum parameter, extract just the channel number
368  // from this parameter.
369  //
370  ui32ChannelNum &= 0x1f;
371 
372  //
373  // Set the useburst bit for this channel if set in ui32Config.
374  //
375  if(ui32Attr & UDMA_ATTR_USEBURST)
376  {
377  HWREG(UDMA_USEBURSTSET) = 1 << ui32ChannelNum;
378  }
379 
380  //
381  // Set the alternate control select bit for this channel,
382  // if set in ui32Config.
383  //
384  if(ui32Attr & UDMA_ATTR_ALTSELECT)
385  {
386  HWREG(UDMA_ALTSET) = 1 << ui32ChannelNum;
387  }
388 
389  //
390  // Set the high priority bit for this channel, if set in ui32Config.
391  //
392  if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
393  {
394  HWREG(UDMA_PRIOSET) = 1 << ui32ChannelNum;
395  }
396 
397  //
398  // Set the request mask bit for this channel, if set in ui32Config.
399  //
400  if(ui32Attr & UDMA_ATTR_REQMASK)
401  {
402  HWREG(UDMA_REQMASKSET) = 1 << ui32ChannelNum;
403  }
404 }
405 
406 //*****************************************************************************
407 //
426 //
427 //*****************************************************************************
428 void
429 uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
430 {
431  //
432  // Check the arguments.
433  //
434  ASSERT((ui32ChannelNum & 0xffff) < 32);
437 
438  //
439  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
440  // passed as the ui32ChannelNum parameter, extract just the channel number
441  // from this parameter.
442  //
443  ui32ChannelNum &= 0x1f;
444 
445  //
446  // Clear the useburst bit for this channel if set in ui32Config.
447  //
448  if(ui32Attr & UDMA_ATTR_USEBURST)
449  {
450  HWREG(UDMA_USEBURSTCLR) = 1 << ui32ChannelNum;
451  }
452 
453  //
454  // Clear the alternate control select bit for this channel, if set in
455  // ui32Config.
456  //
457  if(ui32Attr & UDMA_ATTR_ALTSELECT)
458  {
459  HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum;
460  }
461 
462  //
463  // Clear the high priority bit for this channel, if set in ui32Config.
464  //
465  if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
466  {
467  HWREG(UDMA_PRIOCLR) = 1 << ui32ChannelNum;
468  }
469 
470  //
471  // Clear the request mask bit for this channel, if set in ui32Config.
472  //
473  if(ui32Attr & UDMA_ATTR_REQMASK)
474  {
475  HWREG(UDMA_REQMASKCLR) = 1 << ui32ChannelNum;
476  }
477 }
478 
479 //*****************************************************************************
480 //
497 //
498 //*****************************************************************************
499 uint32_t
500 uDMAChannelAttributeGet(uint32_t ui32ChannelNum)
501 {
502  uint32_t ui32Attr = 0;
503 
504  //
505  // Check the arguments.
506  //
507  ASSERT((ui32ChannelNum & 0xffff) < 32);
508 
509  //
510  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
511  // passed as the ui32ChannelNum parameter, extract just the channel number
512  // from this parameter.
513  //
514  ui32ChannelNum &= 0x1f;
515 
516  //
517  // Check to see if useburst bit is set for this channel.
518  //
519  if(HWREG(UDMA_USEBURSTSET) & (1 << ui32ChannelNum))
520  {
521  ui32Attr |= UDMA_ATTR_USEBURST;
522  }
523 
524  //
525  // Check to see if the alternate control bit is set for this channel.
526  //
527  if(HWREG(UDMA_ALTSET) & (1 << ui32ChannelNum))
528  {
529  ui32Attr |= UDMA_ATTR_ALTSELECT;
530  }
531 
532  //
533  // Check to see if the high priority bit is set for this channel.
534  //
535  if(HWREG(UDMA_PRIOSET) & (1 << ui32ChannelNum))
536  {
537  ui32Attr |= UDMA_ATTR_HIGH_PRIORITY;
538  }
539 
540  //
541  // Check to see if the request mask bit is set for this channel.
542  //
543  if(HWREG(UDMA_REQMASKSET) & (1 << ui32ChannelNum))
544  {
545  ui32Attr |= UDMA_ATTR_REQMASK;
546  }
547 
548  //
549  // Return the configuration flags.
550  //
551  return(ui32Attr);
552 }
553 
554 //*****************************************************************************
555 //
600 //
601 //*****************************************************************************
602 void
603 uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control)
604 {
605  tDMAControlTable *psCtl;
606 
607  //
608  // Check the arguments.
609  //
610  ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
611  ASSERT(HWREG(UDMA_CTLBASE) != 0);
612 
613  //
614  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
615  // passed as the ui32ChannelStructIndex parameter, extract just the channel
616  // index from this parameter.
617  //
618  ui32ChannelStructIndex &= 0x3f;
619 
620  //
621  // Get the base address of the control table.
622  //
623  psCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
624 
625  //
626  // Get the current control word value and mask off the fields to be
627  // changed, then OR in the new settings.
628  //
629  psCtl[ui32ChannelStructIndex].ui32Control =
630  ((psCtl[ui32ChannelStructIndex].ui32Control &
637  ui32Control);
638 }
639 
640 //*****************************************************************************
641 //
707 //
708 //*****************************************************************************
709 void
710 uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode,
711  void *pvSrcAddr, void *pvDstAddr,
712  uint32_t ui32TransferSize)
713 {
714  tDMAControlTable *psControlTable;
715  uint32_t ui32Control;
716  uint32_t ui32Inc;
717  uint32_t ui32BufferBytes;
718 
719  //
720  // Check the arguments.
721  //
722  ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
723  ASSERT(HWREG(UDMA_CTLBASE) != 0);
725  ASSERT((uint32_t)pvSrcAddr >= 0x20000000);
726  ASSERT((uint32_t)pvDstAddr >= 0x20000000);
727  ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= 1024));
728 
729  //
730  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
731  // passed as the ui32ChannelStructIndex parameter, extract just the channel
732  // index from this parameter.
733  //
734  ui32ChannelStructIndex &= 0x3f;
735 
736  //
737  // Get the base address of the control table.
738  //
739  psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
740 
741  //
742  // Get the current control word value and mask off the mode and size
743  // fields.
744  //
745  ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
747 
748  //
749  // Adjust the mode if the alt control structure is selected.
750  //
751  if(ui32ChannelStructIndex & UDMA_ALT_SELECT)
752  {
753  if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
754  (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
755  {
756  ui32Mode |= UDMA_MODE_ALT_SELECT;
757  }
758  }
759 
760  //
761  // Set the transfer size and mode in the control word (but don't write the
762  // control word yet as it could kick off a transfer).
763  //
764  ui32Control |= ui32Mode | ((ui32TransferSize - 1) << 4);
765 
766  //
767  // Get the address increment value for the source, from the control word.
768  //
769  ui32Inc = (ui32Control & UDMA_CHCTL_SRCINC_M);
770 
771  //
772  // Compute the ending source address of the transfer. If the source
773  // increment is set to none, then the ending address is the same as the
774  // beginning.
775  //
776  if(ui32Inc != UDMA_SRC_INC_NONE)
777  {
778  ui32Inc = ui32Inc >> 26;
779  ui32BufferBytes = ui32TransferSize << ui32Inc;
780  pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1);
781  }
782 
783  //
784  // Load the source ending address into the control block.
785  //
786  psControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr;
787 
788  //
789  // Get the address increment value for the destination, from the control
790  // word.
791  //
792  ui32Inc = ui32Control & UDMA_CHCTL_DSTINC_M;
793 
794  //
795  // Compute the ending destination address of the transfer. If the
796  // destination increment is set to none, then the ending address is the
797  // same as the beginning.
798  //
799  if(ui32Inc != UDMA_DST_INC_NONE)
800  {
801  //
802  // There is a special case if this is setting up a scatter-gather
803  // transfer. The destination pointer must point to the end of
804  // the alternate structure for this channel instead of calculating
805  // the end of the buffer in the normal way.
806  //
807  if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
808  (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
809  {
810  pvDstAddr =
811  (void *)&psControlTable[ui32ChannelStructIndex |
812  UDMA_ALT_SELECT].ui32Spare;
813  }
814  //
815  // Not a scatter-gather transfer, calculate end pointer normally.
816  //
817  else
818  {
819  ui32Inc = ui32Inc >> 30;
820  ui32BufferBytes = ui32TransferSize << ui32Inc;
821  pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1);
822  }
823  }
824 
825  //
826  // Load the destination ending address into the control block.
827  //
828  psControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr;
829 
830  //
831  // Write the new control word value.
832  //
833  psControlTable[ui32ChannelStructIndex].ui32Control = ui32Control;
834 }
835 
836 //*****************************************************************************
837 //
858 //
859 //*****************************************************************************
860 void
861 uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount,
862  void *pvTaskList, uint32_t ui32IsPeriphSG)
863 {
864  tDMAControlTable *psControlTable;
865  tDMAControlTable *psTaskTable;
866 
867  //
868  // Check the parameters
869  //
870  ASSERT((ui32ChannelNum & 0xffff) < 32);
871  ASSERT(HWREG(UDMA_CTLBASE) != 0);
872  ASSERT(pvTaskList != 0);
873  ASSERT(ui32TaskCount <= 1024);
874  ASSERT(ui32TaskCount != 0);
875 
876  //
877  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
878  // passed as the ui32ChannelNum parameter, extract just the channel number
879  // from this parameter.
880  //
881  ui32ChannelNum &= 0x1f;
882 
883  //
884  // Get the base address of the control table.
885  //
886  psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
887 
888  //
889  // Get a handy pointer to the task list
890  //
891  psTaskTable = (tDMAControlTable *)pvTaskList;
892 
893  //
894  // Compute the ending address for the source pointer. This address is the
895  // last element of the last task in the task table
896  //
897  psControlTable[ui32ChannelNum].pvSrcEndAddr =
898  &psTaskTable[ui32TaskCount - 1].ui32Spare;
899 
900  //
901  // Compute the ending address for the destination pointer. This address
902  // is the end of the alternate structure for this channel.
903  //
904  psControlTable[ui32ChannelNum].pvDstEndAddr =
905  &psControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare;
906 
907  //
908  // Compute the control word. Most configurable items are fixed for
909  // scatter-gather. Item and increment sizes are all 32-bit and arb
910  // size must be 4. The count is the number of items in the task list
911  // times 4 (4 words per task).
912  //
913  psControlTable[ui32ChannelNum].ui32Control =
917  (((ui32TaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) |
918  (ui32IsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG :
920 
921  //
922  // Scatter-gather operations can leave the alt bit set. So if doing
923  // back to back scatter-gather transfers, the second attempt may not
924  // work correctly because the alt bit is set. Therefore, clear the
925  // alt bit here to ensure that it is always cleared before a new SG
926  // transfer is started.
927  //
928  HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum;
929 }
930 
931 //*****************************************************************************
932 //
945 //
946 //*****************************************************************************
947 uint32_t
948 uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex)
949 {
950  tDMAControlTable *psControlTable;
951  uint32_t ui32Control;
952 
953  //
954  // Check the arguments.
955  //
956  ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
957  ASSERT(HWREG(UDMA_CTLBASE) != 0);
958 
959  //
960  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
961  // passed as the ui32ChannelStructIndex parameter, extract just the channel
962  // index from this parameter.
963  //
964  ui32ChannelStructIndex &= 0x3f;
965 
966  //
967  // Get the base address of the control table.
968  //
969  psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
970 
971  //
972  // Get the current control word value and mask off all but the size field
973  // and the mode field.
974  //
975  ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
977 
978  //
979  // If the size field and mode field are 0 then the transfer is finished
980  // and there are no more items to transfer
981  //
982  if(ui32Control == 0)
983  {
984  return(0);
985  }
986 
987  //
988  // Otherwise, if either the size field or more field is non-zero, then
989  // not all the items have been transferred.
990  //
991  else
992  {
993  //
994  // Shift the size field and add one, then return to user.
995  //
996  return((ui32Control >> 4) + 1);
997  }
998 }
999 
1000 //*****************************************************************************
1001 //
1015 //
1016 //*****************************************************************************
1017 uint32_t
1018 uDMAChannelModeGet(uint32_t ui32ChannelStructIndex)
1019 {
1020  tDMAControlTable *psControlTable;
1021  uint32_t ui32Control;
1022 
1023  //
1024  // Check the arguments.
1025  //
1026  ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
1027  ASSERT(HWREG(UDMA_CTLBASE) != 0);
1028 
1029  //
1030  // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
1031  // passed as the ui32ChannelStructIndex parameter, extract just the channel
1032  // index from this parameter.
1033  //
1034  ui32ChannelStructIndex &= 0x3f;
1035 
1036  //
1037  // Get the base address of the control table.
1038  //
1039  psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
1040 
1041  //
1042  // Get the current control word value and mask off all but the mode field.
1043  //
1044  ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
1046 
1047  //
1048  // Check if scatter/gather mode, and if so, mask off the alt bit.
1049  //
1050  if(((ui32Control & ~UDMA_MODE_ALT_SELECT) ==
1052  ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER))
1053  {
1054  ui32Control &= ~UDMA_MODE_ALT_SELECT;
1055  }
1056 
1057  //
1058  // Return the mode to the caller.
1059  //
1060  return(ui32Control);
1061 }
1062 
1063 //*****************************************************************************
1064 //
1089 //
1090 //*****************************************************************************
1091 void
1092 uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void))
1093 {
1094  //
1095  // Check the arguments.
1096  //
1097  ASSERT(pfnHandler);
1098  ASSERT((ui32IntChannel == UDMA_INT_SW) ||
1099  (ui32IntChannel == UDMA_INT_ERR));
1100 
1101  //
1102  // Register the interrupt handler.
1103  //
1104  IntRegister(ui32IntChannel, pfnHandler);
1105 
1106  //
1107  // Enable the memory management fault.
1108  //
1109  IntEnable(ui32IntChannel);
1110 }
1111 
1112 //*****************************************************************************
1113 //
1127 //
1128 //*****************************************************************************
1129 void
1130 uDMAIntUnregister(uint32_t ui32IntChannel)
1131 {
1132  //
1133  // Disable the interrupt.
1134  //
1135  IntDisable(ui32IntChannel);
1136 
1137  //
1138  // Unregister the interrupt handler.
1139  //
1140  IntUnregister(ui32IntChannel);
1141 }
1142 
1143 //*****************************************************************************
1144 //
1160 //
1161 //*****************************************************************************
1162 uint32_t
1164 {
1165  //
1166  // Return the value of the uDMA interrupt status register
1167  //
1168  return(HWREG(UDMA_CHIS));
1169 }
1170 
1171 //*****************************************************************************
1172 //
1188 //
1189 //*****************************************************************************
1190 void
1191 uDMAIntClear(uint32_t ui32ChanMask)
1192 {
1193  //
1194  // Clear the requested bits in the uDMA interrupt status register
1195  //
1196  HWREG(UDMA_CHIS) = ui32ChanMask;
1197 }
1198 
1199 //*****************************************************************************
1200 //
1221 //
1222 //*****************************************************************************
1223 void
1224 uDMAChannelAssign(uint32_t ui32Mapping)
1225 {
1226  uint32_t ui32MapReg;
1227  uint_fast8_t ui8MapShift;
1228  uint_fast8_t ui8ChannelNum;
1229 
1230  //
1231  // Check the parameters
1232  //
1233  ASSERT((ui32Mapping & 0xffffff00) < 0x00050000);
1234 
1235  //
1236  // Extract the channel number and map encoding value from the parameter.
1237  //
1238  ui8ChannelNum = ui32Mapping & 0xff;
1239  ui32Mapping = ui32Mapping >> 16;
1240 
1241  //
1242  // Find the uDMA channel mapping register and shift value to use for this
1243  // channel
1244  //
1245  ui32MapReg = UDMA_CHMAP0 + (uint32_t)((ui8ChannelNum / 8) * 4);
1246  ui8MapShift = (ui8ChannelNum % 8) * 4;
1247 
1248  //
1249  // Set the channel map encoding for this channel
1250  //
1251  HWREG(ui32MapReg) = (HWREG(ui32MapReg) & ~(0xf << ui8MapShift)) |
1252  ui32Mapping << ui8MapShift;
1253 }
1254 
1255 //*****************************************************************************
1256 //
1257 // The following functions are deprecated. Use uDMAChannelAssign() instead
1258 // to accomplish the same end.
1259 //
1260 //*****************************************************************************
1261 #ifndef DEPRECATED
1262 //*****************************************************************************
1263 //
1310 //
1311 //*****************************************************************************
1312 void
1313 uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs)
1314 {
1315  //
1316  // Select the secondary peripheral for the specified channels.
1317  //
1318  HWREG(UDMA_CHASGN) |= ui32SecPeriphs;
1319 }
1320 
1321 //*****************************************************************************
1322 //
1367 //
1368 //*****************************************************************************
1369 void
1370 uDMAChannelSelectDefault(uint32_t ui32DefPeriphs)
1371 {
1372  //
1373  // Select the default peripheral for the specified channels.
1374  //
1375  HWREG(UDMA_CHASGN) &= ~ui32DefPeriphs;
1376 }
1377 #endif
1378 
1379 //*****************************************************************************
1380 //
1381 // Close the Doxygen group.
1383 //
1384 //*****************************************************************************
uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex)
Definition: udma.c:1018
#define UDMA_CFG_MASTEN
Definition: hw_udma.h:108
#define UDMA_CHCTL_DSTINC_32
Definition: hw_udma.h:363
volatile void * pvSrcEndAddr
Definition: udma.h:73
void uDMAEnable(void)
Definition: udma.c:67
void uDMAChannelAssign(uint32_t ui32Mapping)
Definition: udma.c:1224
#define UDMA_CHCTL_NXTUSEBURST
Definition: hw_udma.h:393
#define UDMA_ALTSET
Definition: hw_udma.h:63
uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex)
Definition: udma.c:948
void uDMAIntUnregister(uint32_t ui32IntChannel)
Definition: udma.c:1130
#define UDMA_DST_INC_NONE
Definition: udma.h:227
#define UDMA_MODE_PER_SCATTER_GATHER
Definition: udma.h:215
#define HWREG(x)
Definition: hw_types.h:48
void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)
Definition: udma.c:710
void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs)
Definition: udma.c:1370
#define UDMA_CHCTL_SRCSIZE_M
Definition: hw_udma.h:374
uint32_t uDMAIntStatus(void)
Definition: udma.c:1163
#define UDMA_CHCTL_XFERSIZE_M
Definition: hw_udma.h:392
#define UDMA_ATTR_USEBURST
Definition: udma.h:197
#define ASSERT(expr)
Definition: debug.h:67
#define UDMA_ALT_SELECT
Definition: udma.h:291
void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
Definition: udma.c:356
#define UDMA_CHIS
Definition: hw_udma.h:71
#define UDMA_SWREQ
Definition: hw_udma.h:56
void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs)
Definition: udma.c:1313
void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control)
Definition: udma.c:603
#define UDMA_CFG
Definition: hw_udma.h:50
#define UDMA_ALTCLR
Definition: hw_udma.h:65
#define UDMA_ENACLR
Definition: hw_udma.h:62
#define UDMA_CHCTL_DSTSIZE_32
Definition: hw_udma.h:368
#define UDMA_SRC_INC_NONE
Definition: udma.h:231
bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum)
Definition: udma.c:206
#define UDMA_ENASET
Definition: hw_udma.h:61
volatile uint32_t ui32Spare
Definition: udma.h:88
uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum)
Definition: udma.c:500
void * uDMAControlAlternateBaseGet(void)
Definition: udma.c:290
void uDMAChannelRequest(uint32_t ui32ChannelNum)
Definition: udma.c:320
#define UDMA_ATTR_HIGH_PRIORITY
Definition: udma.h:199
#define UDMA_CHCTL_SRCSIZE_32
Definition: hw_udma.h:377
#define UDMA_ERRCLR
Definition: hw_udma.h:69
#define UDMA_CHCTL_SRCINC_32
Definition: hw_udma.h:372
#define UDMA_CHCTL_XFERMODE_PER_SG
Definition: hw_udma.h:407
void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)
Definition: udma.c:861
void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
Definition: udma.c:429
volatile uint32_t ui32Control
Definition: udma.h:83
volatile void * pvDstEndAddr
Definition: udma.h:78
void uDMADisable(void)
Definition: udma.c:86
#define UDMA_CHCTL_ARBSIZE_M
Definition: hw_udma.h:380
#define UDMA_CTLBASE
Definition: hw_udma.h:51
#define UDMA_CHCTL_DSTINC_M
Definition: hw_udma.h:360
#define UDMA_ATTR_ALTSELECT
Definition: udma.h:198
#define UDMA_CHASGN
Definition: hw_udma.h:70
void uDMAChannelDisable(uint32_t ui32ChannelNum)
Definition: udma.c:179
#define UDMA_CHCTL_SRCINC_M
Definition: hw_udma.h:369
#define UDMA_INT_SW
Definition: udma.h:299
#define UDMA_PRIOSET
Definition: hw_udma.h:67
void IntUnregister(uint32_t ui32Interrupt)
Definition: interrupt.c:381
#define UDMA_REQMASKCLR
Definition: hw_udma.h:60
#define UDMA_CHMAP0
Definition: hw_udma.h:72
#define UDMA_USEBURSTCLR
Definition: hw_udma.h:58
void uDMAIntClear(uint32_t ui32ChanMask)
Definition: udma.c:1191
#define UDMA_ALTBASE
Definition: hw_udma.h:52
#define UDMA_PRIOCLR
Definition: hw_udma.h:68
#define UDMA_ATTR_REQMASK
Definition: udma.h:200
#define UDMA_CHCTL_XFERMODE_M
Definition: hw_udma.h:394
void * uDMAControlBaseGet(void)
Definition: udma.c:269
void uDMAIntRegister(uint32_t ui32IntChannel, void(*pfnHandler)(void))
Definition: udma.c:1092
#define UDMA_INT_ERR
Definition: udma.h:300
uint32_t uDMAErrorStatusGet(void)
Definition: udma.c:106
#define UDMA_REQMASKSET
Definition: hw_udma.h:59
#define UDMA_CHCTL_ARBSIZE_4
Definition: hw_udma.h:383
#define UDMA_CHCTL_XFERMODE_MEM_SG
Definition: hw_udma.h:403
#define UDMA_USEBURSTSET
Definition: hw_udma.h:57
void uDMAErrorStatusClear(void)
Definition: udma.c:126
#define UDMA_CHCTL_XFERSIZE_S
Definition: hw_udma.h:412
#define UDMA_MODE_MEM_SCATTER_GATHER
Definition: udma.h:213
void IntDisable(uint32_t ui32Interrupt)
Definition: interrupt.c:684
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Definition: interrupt.c:309
void uDMAControlBaseSet(void *psControlTable)
Definition: udma.c:242
void IntEnable(uint32_t ui32Interrupt)
Definition: interrupt.c:610
#define UDMA_CHCTL_DSTSIZE_M
Definition: hw_udma.h:365
#define UDMA_MODE_ALT_SELECT
Definition: udma.h:217
void uDMAChannelEnable(uint32_t ui32ChannelNum)
Definition: udma.c:152