hibernate.c

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//*****************************************************************************
//
// hibernate.c - Driver for the Hibernation module
//
// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************

#include <stdbool.h>
#include <stdint.h>
#include <time.h>
#include "inc/hw_hibernate.h"
#include "inc/hw_ints.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/hibernate.h"
#include "driverlib/interrupt.h"
#include "driverlib/sysctl.h"

//*****************************************************************************
//
// The delay in microseconds for writing to the Hibernation module registers.
//
//*****************************************************************************
#define DELAY_USECS             95

//*****************************************************************************
//
// The number of processor cycles to execute one pass of the delay loop.
//
//*****************************************************************************
#define LOOP_CYCLES             3

//*****************************************************************************
//
// A macro used to determine whether the target part supports Wake from IO
// pins.
//
//*****************************************************************************
#define HIBERNATE_WAKE_IO       CLASS_IS_TM4C129

//*****************************************************************************
//
// A macro used to determine whether the target part supports Wake from IO
// pins.
//
//*****************************************************************************
#define HIBERNATE_CLOCK_OUTPUT  CLASS_IS_TM4C129

//*****************************************************************************
//
//
//*****************************************************************************
static void
_HibernateWriteComplete(void)
{
    //
    // Spin until the write complete bit is set.
    //
    while(!(HWREG(HIB_CTL) & HIB_CTL_WRC))
    {
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateEnableExpClk(uint32_t ui32HibClk)
{
    //
    // Turn on the clock enable bit.
    //
    HWREG(HIB_CTL) |= HIB_CTL_CLK32EN;

    //
    // Wait for write complete following register load (above).
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateDisable(void)
{
    //
    // Turn off the clock enable bit.
    //
    HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateClockConfig(uint32_t ui32Config)
{
    uint32_t ui32HIBCtl;

    ASSERT((ui32Config & ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE |
                           HIBERNATE_OSC_DISABLE)) == 0);

    ui32HIBCtl = HWREG(HIB_CTL);

    //
    // Clear the current configuration bits.
    //
    ui32HIBCtl &= ~(HIBERNATE_OSC_HIGHDRIVE | HIBERNATE_OSC_LOWDRIVE |
                    HIBERNATE_OSC_LFIOSC | HIBERNATE_OSC_DISABLE);

    //
    // Set the new configuration bits.
    //
    ui32HIBCtl |= ui32Config & (HIBERNATE_OSC_HIGHDRIVE |
                                HIBERNATE_OSC_LOWDRIVE |
                                HIBERNATE_OSC_LFIOSC |
                                HIBERNATE_OSC_DISABLE);

    //
    // Must be sure that the 32KHz clock is enabled if the hibernate is about
    // to switch to it.
    //
    if(ui32Config & HIBERNATE_OSC_LFIOSC)
    {
        ui32HIBCtl |= HIB_CTL_CLK32EN;
    }

    //
    // Set the hibernation clocking configuration.
    //
    HWREG(HIB_CTL) = ui32HIBCtl;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();

    //
    // Write the output clock configuration for devices that support
    // controlling the output clocks from the hibernate module.
    //
    if(HIBERNATE_CLOCK_OUTPUT)
    {
        HWREG(HIB_CC) = ui32Config & (HIBERNATE_OUT_SYSCLK |
                                      HIBERNATE_OUT_ALT1CLK);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateRTCEnable(void)
{
    //
    // Turn on the RTC enable bit.
    //
    HWREG(HIB_CTL) |= HIB_CTL_RTCEN;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateRTCDisable(void)
{
    //
    // Turn off the RTC enable bit.
    //
    HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateBatCheckStart(void)
{
    //
    // Initiated a forced battery check.
    //
    HWREG(HIB_CTL) |= HIB_CTL_BATCHK;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateBatCheckDone(void)
{
    //
    // Read the current state of the battery check.
    //
    return(HWREG(HIB_CTL) & HIB_CTL_BATCHK);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateWakeSet(uint32_t ui32WakeFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(!(ui32WakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC |
                               HIBERNATE_WAKE_GPIO | HIBERNATE_WAKE_RESET |
                               HIBERNATE_WAKE_LOW_BAT)));

    //
    // Set the specified wake flags in the control register.
    //
    HWREG(HIB_CTL) = (ui32WakeFlags | (HWREG(HIB_CTL) &
                                       ~(HIBERNATE_WAKE_PIN |
                                         HIBERNATE_WAKE_RTC |
                                         HIBERNATE_WAKE_LOW_BAT)));

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();

    //
    // Write the hibernate IO register if requested.
    //
    if(HIBERNATE_WAKE_IO)
    {
        //
        // If the reset or GPIOs are begin used as a wake source then the
        // the VDD3ON needs to be set to allow the pads to remained
        // powered.
        //
        if((ui32WakeFlags & (HIBERNATE_WAKE_RESET | HIBERNATE_WAKE_GPIO)) &&
           ((HWREG(HIB_CTL) & HIB_CTL_VDD3ON) == 0))
        {
            //
            // Make sure that VDD3ON mode is enabled so that the pads can
            // retain their state.
            //
            HWREG(HIB_CTL) |= HIB_CTL_VDD3ON;

            //
            // Wait for write completion
            //
            _HibernateWriteComplete();
        }

        //
        // Set the requested flags.
        //
        HWREG(HIB_IO) = (ui32WakeFlags >> 16) | HIB_IO_WUUNLK;

        //
        // Spin until the write complete bit is set.
        //
        while((HWREG(HIB_IO) & HIB_IO_IOWRC) == 0)
        {
        }

        //
        // Clear the write unlock bit.
        //
        HWREG(HIB_IO) &= ~HIB_IO_WUUNLK;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateWakeGet(void)
{
    uint32_t ui32Ctrl;

    //
    // Read the wake bits from the control register and return those bits to
    // the caller.
    //
    if(HIBERNATE_WAKE_IO)
    {
        ui32Ctrl = HWREG(HIB_CTL);
        return((ui32Ctrl & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC |
                            HIBERNATE_WAKE_LOW_BAT)) |
               ((HWREG(HIB_IO) << 16) & (HIBERNATE_WAKE_RESET |
                                         HIBERNATE_WAKE_GPIO)));
    }
    else
    {
        return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC |
                                 HIBERNATE_WAKE_LOW_BAT));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateLowBatSet(uint32_t ui32LowBatFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(!(ui32LowBatFlags &
             ~(HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT)));

    //
    // Set the low-battery detect and abort bits in the control register,
    // according to the parameter.
    //
    HWREG(HIB_CTL) = (ui32LowBatFlags |
                      (HWREG(HIB_CTL) & ~(HIB_CTL_VBATSEL_M |
                                          HIBERNATE_LOW_BAT_ABORT)));

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateLowBatGet(void)
{
    //
    // Read the supported low bat bits from the control register and return
    // those bits to the caller.
    //
    return(HWREG(HIB_CTL) & (HIB_CTL_VBATSEL_M | HIBERNATE_LOW_BAT_ABORT));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateRTCSet(uint32_t ui32RTCValue)
{
    //
    // Load register requires unlock.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Write the new RTC value to the RTC load register.
    //
    HWREG(HIB_RTCLD) = ui32RTCValue;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();

    //
    // Unlock.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateRTCGet(void)
{
    //
    // Return the value of the RTC counter register to the caller.
    //
    return(HWREG(HIB_RTCC));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateRTCMatchSet(uint32_t ui32Match, uint32_t ui32Value)
{
    ASSERT(ui32Match == 0);

    //
    // Write the new match value to the match register.
    //
    HWREG(HIB_RTCM0) = ui32Value;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateRTCMatchGet(uint32_t ui32Match)
{
    ASSERT(ui32Match == 0);

    //
    // Return the value of the match register to the caller.
    //
    return(HWREG(HIB_RTCM0));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateRTCSSMatchSet(uint32_t ui32Match, uint32_t ui32Value)
{
    ASSERT(ui32Match == 0);

    //
    // Write the new sub second match value to the sub second match register.
    //
    HWREG(HIB_RTCSS) = ui32Value << HIB_RTCSS_RTCSSM_S;

    //
    // Wait for write complete to be signaled on later devices.
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateRTCSSMatchGet(uint32_t ui32Match)
{
    ASSERT(ui32Match == 0);

    //
    // Read the current second RTC count.
    //
    return(HWREG(HIB_RTCSS) >> HIB_RTCSS_RTCSSM_S);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateRTCSSGet(void)
{
    //
    // Read the current second RTC count.
    //
    return(HWREG(HIB_RTCSS) & HIB_RTCSS_RTCSSC_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateRTCTrimSet(uint32_t ui32Trim)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Trim < 0x10000);

    //
    // Write the new trim value to the trim register.
    //
    HWREG(HIB_RTCT) = ui32Trim;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateRTCTrimGet(void)
{
    //
    // Return the value of the trim register to the caller.
    //
    return(HWREG(HIB_RTCT));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateDataSet(uint32_t *pui32Data, uint32_t ui32Count)
{
    uint32_t ui32Idx;

    //
    // Check the arguments.
    //
    ASSERT(ui32Count <= 64);
    ASSERT(pui32Data != 0);

    //
    // Loop through all the words to be stored, storing one at a time.
    //
    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
    {
        //
        // Write a word to the battery-backed storage area.
        //
        HWREG(HIB_DATA + (ui32Idx * 4)) = pui32Data[ui32Idx];

        //
        // Wait for write completion
        //
        _HibernateWriteComplete();
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateDataGet(uint32_t *pui32Data, uint32_t ui32Count)
{
    uint32_t ui32Idx;

    //
    // Check the arguments.
    //
    ASSERT(ui32Count <= 64);
    ASSERT(pui32Data != 0);

    //
    // Loop through all the words to be restored, reading one at a time.
    //
    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
    {
        //
        // Read a word from the battery-backed storage area.  No delay is
        // required between reads.
        //
        pui32Data[ui32Idx] = HWREG(HIB_DATA + (ui32Idx * 4));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateRequest(void)
{
    //
    // Set the bit in the control register to cut main power to the processor.
    //
    HWREG(HIB_CTL) |= HIB_CTL_HIBREQ;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateIntEnable(uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
                              HIBERNATE_INT_VDDFAIL |
                              HIBERNATE_INT_RESET_WAKE |
                              HIBERNATE_INT_GPIO_WAKE |
                              HIBERNATE_INT_RTC_MATCH_0 |
                              HIBERNATE_INT_WR_COMPLETE)));

    //
    // Set the specified interrupt mask bits.
    //
    HWREG(HIB_IM) |= ui32IntFlags;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateIntDisable(uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
                              HIBERNATE_INT_VDDFAIL |
                              HIBERNATE_INT_RESET_WAKE |
                              HIBERNATE_INT_GPIO_WAKE |
                              HIBERNATE_INT_RTC_MATCH_0 |
                              HIBERNATE_INT_WR_COMPLETE)));

    //
    // Clear the specified interrupt mask bits.
    //
    HWREG(HIB_IM) &= ~ui32IntFlags;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
static uint32_t
_HibernateIntNumberGet(void)
{
    uint32_t ui32Int;

    //
    // Find the valid interrupt number for the hibernate module.
    //
    if(CLASS_IS_TM4C129)
    {
        ui32Int = INT_HIBERNATE_TM4C129;
    }
    else
    {
        ui32Int = INT_HIBERNATE_TM4C123;
    }

    return(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateIntRegister(void (*pfnHandler)(void))
{
    uint32_t ui32Int;

    //
    // Get the interrupt number for the Hibernate module.
    //
    ui32Int = _HibernateIntNumberGet();

    ASSERT(ui32Int != 0);

    //
    // Register the interrupt handler.
    //
    IntRegister(ui32Int, pfnHandler);

    //
    // Enable the hibernate module interrupt.
    //
    IntEnable(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateIntUnregister(void)
{
    uint32_t ui32Int;

    //
    // Get the interrupt number for the Hibernate module.
    //
    ui32Int = _HibernateIntNumberGet();

    ASSERT(ui32Int != 0);

    //
    // Disable the hibernate interrupt.
    //
    IntDisable(ui32Int);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(ui32Int);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateIntStatus(bool bMasked)
{
    //
    // Read and return the Hibernation module raw or masked interrupt status.
    //
    if(bMasked == true)
    {
        return(HWREG(HIB_MIS));
    }
    else
    {
        return(HWREG(HIB_RIS));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateIntClear(uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(!(ui32IntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
                              HIBERNATE_INT_VDDFAIL |
                              HIBERNATE_INT_RESET_WAKE |
                              HIBERNATE_INT_GPIO_WAKE |
                              HIBERNATE_INT_RTC_MATCH_0 |
                              HIBERNATE_INT_WR_COMPLETE)));

    //
    // Write the specified interrupt bits into the interrupt clear register.
    //
    HWREG(HIB_IC) |= ui32IntFlags;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateIsActive(void)
{
    //
    // Read the control register, and return true if the module is enabled.
    //
    return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateGPIORetentionEnable(void)
{
    //
    // Enable power to the pads and enable GPIO retention during hibernate.
    //
    HWREG(HIB_CTL) |= HIB_CTL_VDD3ON | HIB_CTL_RETCLR;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateGPIORetentionDisable(void)
{
    //
    // Reset the GPIO configuration after waking from hibernate and disable
    // the hibernate power to the pads.
    //
    HWREG(HIB_CTL) &= ~(HIB_CTL_RETCLR | HIB_CTL_VDD3ON);

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
bool
HibernateGPIORetentionGet(void)
{
    //
    // Read the current GPIO retention configuration.
    //
    if((HWREG(HIB_CTL) & (HIB_CTL_RETCLR | HIB_CTL_VDD3ON)) ==
       (HIB_CTL_RETCLR | HIB_CTL_VDD3ON))
    {
        return(true);
    }
    return(false);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateCounterMode(uint32_t ui32Config)
{
    //
    // Set the requested configuration.
    //
    HWREG(HIB_CALCTL) = ui32Config;

    //
    // Wait for write completion
    //
    _HibernateWriteComplete();
}

//*****************************************************************************
//
// Internal function to parse the time structure to set the calendar fields.
//
//*****************************************************************************
static void
_HibernateCalendarSet(uint32_t ui32Reg, struct tm *psTime)
{
    uint32_t ui32Time, ui32Date;

    ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN);

    //
    // Minutes and seconds are consistent in all modes.
    //
    ui32Time = (((psTime->tm_min << HIB_CALLD0_MIN_S) & HIB_CALLD0_MIN_M) |
                ((psTime->tm_sec << HIB_CALLD0_SEC_S) & HIB_CALLD0_SEC_M));

    //
    // 24 Hour time is used directly for Calendar set.
    //
    if(HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24)
    {
        ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S);

        //
        // for Calendar match, if it is every hour, AMPM bit should be clear
        //
        if((ui32Reg == HIB_CALM0) && (psTime->tm_hour == 0xFF) )
        {
            //
            // clear AMPM bit
            //
            ui32Time &= ~HIB_CAL0_AMPM;
        }
    }
    else
    {
        //
        // In AM/PM time hours have to be capped at 12.
        // If the hours are all 1s, it means the match for the hour is
        // always true.  We need to set 1F in the hw field.
        //
        if(psTime->tm_hour == 0xFF)
        {
            //
            // Match every hour.
            //
            ui32Time |= HIB_CALLD0_HR_M;
        }
        else if(psTime->tm_hour >= 12)
        {
            //
            // Need to set the PM bit if it is noon or later.
            //
            ui32Time |= (((psTime->tm_hour - 12) << HIB_CALLD0_HR_S) |
                         HIB_CAL0_AMPM);
        }
        else
        {
            //
            // All other times are normal and AM.
            //
            ui32Time |= (psTime->tm_hour << HIB_CALLD0_HR_S);
        }
    }

    //
    // Create the date in the correct register format.
    //
    if(ui32Reg == HIB_CAL0)
    {
        //
        // We must add 1 to the month, since the time structure lists
        // the month from 0 to 11 and the HIB lists it from 1 to 12.
        //
        ui32Date = ((psTime->tm_mday << HIB_CAL1_DOM_S) |
                    ((psTime->tm_mon + 1) << HIB_CAL1_MON_S) |
                    (psTime->tm_wday << HIB_CAL1_DOW_S) |
                    ((psTime->tm_year - 100) << HIB_CAL1_YEAR_S));
    }
    else
    {
        //
        // Wday, month and year are not included in the match
        // Functionality.
        //
        if(psTime->tm_mday == 0xFF)
        {
            //
            // program 0 to match every day
            //
            ui32Date = 0 << HIB_CAL1_DOM_M;
        }
        else
        {
            ui32Date = (psTime->tm_mday << HIB_CAL1_DOM_S);
        }
    }

    //
    // Load register requires unlock.
    //
    if(ui32Reg == HIB_CAL0)
    {
        //
        // Unlock the hibernate counter load registers.
        //
        HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
        _HibernateWriteComplete();
    }

    //
    // Set the requested time and date.
    //
    if(ui32Reg == HIB_CAL0)
    {
        HWREG(HIB_CALLD0) = ui32Time;
        _HibernateWriteComplete();
        HWREG(HIB_CALLD1) = ui32Date;
        _HibernateWriteComplete();
    }
    else
    {
        HWREG(HIB_CALM0) = ui32Time;
        _HibernateWriteComplete();
        HWREG(HIB_CALM1) = ui32Date;
        _HibernateWriteComplete();
    }

    //
    // Load register requires unlock.
    //
    if(ui32Reg == HIB_CAL0)
    {
        //
        // Lock the hibernate counter load registers.
        //
        HWREG(HIB_LOCK) = 0;
        _HibernateWriteComplete();
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateCalendarSet(struct tm *psTime)
{
    //
    // Load a new date/time.
    //
    _HibernateCalendarSet(HIB_CAL0, psTime);
}

//*****************************************************************************
//
//
//*****************************************************************************
int
HibernateCalendarGet(struct tm *psTime)
{
    uint32_t ui32Date, ui32Time;

    ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN);

    //
    // Wait for the value to be valid, this should never be more than a few
    // loops and should never hang.
    //
    do
    {
        ui32Date = HWREG(HIB_CAL1);
    }
    while((ui32Date & HIB_CAL1_VALID) == 0);

    //
    // Wait for the value to be valid, this should never be more than a few
    // loops and should never hang.
    //
    do
    {
        ui32Time = HWREG(HIB_CAL0);
    }
    while((ui32Time & HIB_CAL0_VALID) == 0);

    //
    // The date changed after reading the time so fail this call and let the
    // application call again since it knows how int32_t to wait until another
    // second passes.
    //
    if(ui32Date != HWREG(HIB_CAL1))
    {
        return(-1);
    }

    //
    // Populate the date and time fields in the psTime structure.
    // We must subtract 1 from the month, since the time structure lists
    // the month from 0 to 11 and the HIB lists it from 1 to 12.
    //
    psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S;
    psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S;
    psTime->tm_mon = (((ui32Date & HIB_CAL1_MON_M) >> HIB_CAL1_MON_S) - 1);
    psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S;
    psTime->tm_wday = (ui32Date & HIB_CAL1_DOW_M) >> HIB_CAL1_DOW_S;
    psTime->tm_year = ((ui32Date & HIB_CAL1_YEAR_M) >> HIB_CAL1_YEAR_S) + 100;
    psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S;

    //
    // Fix up the hour in the non-24-hour mode and the time is in PM.
    //
    if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) &&
       (ui32Time & HIB_CAL0_AMPM))
    {
        psTime->tm_hour += 12;
    }

    return(0);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateCalendarMatchSet(uint32_t ui32Index, struct tm *psTime)
{
    //
    // Set the Match value.
    //
    _HibernateCalendarSet(HIB_CALM0, psTime);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateCalendarMatchGet(uint32_t ui32Index, struct tm *psTime)
{
    uint32_t ui32Date, ui32Time;

    ASSERT(HWREG(HIB_CALCTL) & HIB_CALCTL_CALEN);

    //
    // Get the date field.
    //
    ui32Date = HWREG(HIB_CALM1);

    //
    // Get the time field.
    //
    ui32Time = HWREG(HIB_CALM0);

    //
    // Populate the date and time fields in the psTime structure.
    //
    if((ui32Time & HIB_CAL0_MIN_M) == HIB_CAL0_MIN_M)
    {
        //
        // Match every minute
        //
        psTime->tm_min = 0xFF;
    }
    else
    {
        psTime->tm_min = (ui32Time & HIB_CAL0_MIN_M) >> HIB_CAL0_MIN_S;
    }

    if((ui32Time & HIB_CAL0_SEC_M) == HIB_CAL0_SEC_M)
    {
        //
        // Match every second
        //
        psTime->tm_sec = 0xFF;
    }
    else
    {
        psTime->tm_sec = (ui32Time & HIB_CAL0_SEC_M) >> HIB_CAL0_SEC_S;
    }

    if((ui32Time & HIB_CAL0_HR_M) == HIB_CAL0_HR_M)
    {
        //
        // Match every hour
        //
        psTime->tm_hour = 0xFF;
    }
    else
    {
        psTime->tm_hour = (ui32Time & HIB_CAL0_HR_M) >> HIB_CAL0_HR_S;
    }

    if((ui32Date & HIB_CAL1_DOM_M) == 0)
    {
        //
        // Match every day
        //
        psTime->tm_mday = 0xFF;
    }
    else
    {
        psTime->tm_mday = (ui32Date & HIB_CAL1_DOM_M) >> HIB_CAL1_DOM_S;
    }

    //
    // Fix up the hour in the non-24-hour mode and the time is in PM.
    //
    if(((HWREG(HIB_CALCTL) & HIB_CALCTL_CAL24) == 0) &&
       (ui32Time & HIB_CAL0_AMPM))
    {
        psTime->tm_hour += 12;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperEventsConfig(uint32_t ui32Config)
{
    uint32_t ui32Temp;

    //
    // Mask out the on-event configuration options.
    //
    ui32Temp = (HWREG(HIB_TPCTL) & ~HIB_TPCTL_MEMCLR_M);

    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Set the on-event configuration.
    //
    HWREG(HIB_TPCTL) = (ui32Temp | ui32Config);

    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperEnable(void)
{
    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Set the tamper enable bit.
    //
    HWREG(HIB_TPCTL) |= HIB_TPCTL_TPEN;

    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperDisable(void)
{
    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Clear the tamper enable bit.
    //
    HWREG(HIB_TPCTL) &= ~HIB_TPCTL_TPEN;

    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config)
{
    uint32_t ui32Temp, ui32Mask;

    //
    // Verify parameters.
    //
    ASSERT(ui32Input < 4);

    //
    // Read the current tamper I/O configuration.
    //
    ui32Temp = HWREG(HIB_TPIO);

    //
    // Mask out configuration options for the requested input.
    //
    ui32Mask = (ui32Temp & (~((HIB_TPIO_GFLTR0 | HIB_TPIO_PUEN0 |
                               HIB_TPIO_LEV0 | HIB_TPIO_EN0) <<
                              (ui32Input << 3))));

    //
    // Set tamper I/O configuration for the requested input.
    //
    ui32Temp |= (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3)));

    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Write to the register.
    //
    HWREG(HIB_TPIO) = ui32Temp;

    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperIODisable(uint32_t ui32Input)
{
    //
    // Verify parameters.
    //
    ASSERT(ui32Input < 4);

    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Clear the I/O enable bit.
    //
    HWREG(HIB_TPIO) &= ((~HIB_TPIO_EN0) << (ui32Input << 3));

    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperEventsClear(void)
{
    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Set the tamper event clear bit.
    //
    HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR;

    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperEventsClearNoLock(void)
{
    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Set the tamper event clear bit.
    //
    HWREG(HIB_TPCTL) |= HIB_TPCTL_TPCLR;

}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperUnLock(void)
{
    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperLock(void)
{
    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
HibernateTamperStatusGet(void)
{
    uint32_t ui32Status, ui32Reg;

    //
    // Retrieve the raw register value.
    //
    ui32Reg = HWREG(HIB_TPSTAT);

    //
    // Setup the oscillator status indicators.
    //
    ui32Status = (ui32Reg & (HIB_TPSTAT_XOSCST | HIB_TPSTAT_XOSCFAIL));
    ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCST) ? 0 :
                   HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE);
    ui32Status |= ((ui32Reg & HIB_TPSTAT_XOSCFAIL) ? 0 :
                   HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID);

    //
    // Retrieve the tamper status indicators.
    //
    ui32Status |= ((ui32Reg & HIB_TPSTAT_STATE_M) << 3);

    //
    // The HW shows "disabled" with a zero value, use bit[0] as a flag
    // for this purpose.
    //
    if((ui32Reg & HIB_TPSTAT_STATE_M) == 0)
    {
        ui32Status |= HIBERNATE_TAMPER_STATUS_INACTIVE;
    }

    //
    // Return the API status flags.
    //
    return(ui32Status);
}

//*****************************************************************************
//
//
//*****************************************************************************
bool
HibernateTamperEventsGet(uint32_t ui32Index, uint32_t *pui32RTC,
                         uint32_t *pui32Event)
{
    uint32_t ui32Reg;

    //
    // Verify parameters.
    //
    ASSERT(pui32RTC);
    ASSERT(pui32Event);
    ASSERT(ui32Index < 4);

    //
    // Retrieve the event log data for the requested index if available.
    //
    ui32Reg = HWREG(HIB_TPLOG0 + ((ui32Index << 3) + 4));
    if(ui32Reg == 0)
    {
        //
        // No event data is available for this index.
        //
        return(false);
    }

    //
    // Store the event data in the provided location.
    //
    *pui32Event = ui32Reg;

    //
    // Retrieve the calendar information.
    //
    *pui32RTC = HWREG(HIB_TPLOG0 + (ui32Index << 3));

    //
    // Convert the hour to 24hr mode if the Calendar is enabled
    // and in 24hr mode.
    //
    if((HWREG(HIB_CALCTL) & (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24)) ==
       (HIB_CALCTL_CALEN | HIB_CALCTL_CAL24))
    {
        if(HWREG(HIB_CAL0) & HIB_CAL0_AMPM)
        {
            //
            // Add 12 hour since it is PM
            //
            ui32Reg = ((*pui32RTC & 0X0001f000) + (12<<12)) & 0X0001f000;
            *pui32RTC &= ~0X0001f000;
            *pui32RTC |= ui32Reg;
        }
    }

    //
    // Return success.
    //
    return(true);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
HibernateTamperExtOscRecover(void)
{
    //
    // Unlock the tamper registers.
    //
    HWREG(HIB_LOCK) = HIB_LOCK_HIBLOCK_KEY;
    _HibernateWriteComplete();

    //
    // Set the XOSCFAIL clear bit.
    //
    HWREG(HIB_TPSTAT) |= HIB_TPSTAT_XOSCFAIL;

    //
    // Wait for write completion.
    //
    _HibernateWriteComplete();

    //
    // Lock the tamper registers.
    //
    HWREG(HIB_LOCK) = 0;
    _HibernateWriteComplete();
}

//*****************************************************************************
//
//
//*****************************************************************************
bool
HibernateTamperExtOscValid(void)
{
    if(HibernateTamperStatusGet() & (HIBERNATE_TAMPER_STATUS_EXT_OSC_ACTIVE |
                                     HIBERNATE_TAMPER_STATUS_EXT_OSC_VALID))
    {
        return(true);
    }

    return(false);
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************