EE445M RTOS
Taken at the University of Texas Spring 2015
crc.c
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1 //*****************************************************************************
2 //
3 // crc.c - Driver for the CRC module.
4 //
5 // Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved.
6 // Software License Agreement
7 //
8 // Redistribution and use in source and binary forms, with or without
9 // modification, are permitted provided that the following conditions
10 // are met:
11 //
12 // Redistributions of source code must retain the above copyright
13 // notice, this list of conditions and the following disclaimer.
14 //
15 // Redistributions in binary form must reproduce the above copyright
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18 // distribution.
19 //
20 // Neither the name of Texas Instruments Incorporated nor the names of
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22 // from this software without specific prior written permission.
23 //
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 //
36 // This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
37 //
38 //*****************************************************************************
39 
40 //*****************************************************************************
41 //
44 //
45 //*****************************************************************************
46 
47 #include <stdbool.h>
48 #include <stdint.h>
49 #include "inc/hw_ccm.h"
50 #include "inc/hw_memmap.h"
51 #include "inc/hw_types.h"
52 #include "driverlib/crc.h"
53 #include "driverlib/debug.h"
54 
55 
56 //*****************************************************************************
57 //
95 //
96 //*****************************************************************************
97 void
98 CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
99 {
100  //
101  // Check the arguments.
102  //
103  ASSERT(ui32Base == CCM0_BASE);
104  ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
105  (ui32CRCConfig & CRC_CFG_INIT_0) ||
106  (ui32CRCConfig & CRC_CFG_INIT_1) ||
107  (ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
108  (ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
109  (ui32CRCConfig & CRC_CFG_RESINV) ||
110  (ui32CRCConfig & CRC_CFG_OBR) ||
111  (ui32CRCConfig & CRC_CFG_IBR) ||
112  (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
113  (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
114  (ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
115  (ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
116  (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
117  (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
118  (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
119 
120  //
121  // Write the control register with the configuration.
122  //
123  HWREG(ui32Base + CCM_O_CRCCTRL) = ui32CRCConfig;
124 }
125 
126 //*****************************************************************************
127 //
140 //
141 //*****************************************************************************
142 void
143 CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
144 {
145  //
146  // Check the arguments.
147  //
148  ASSERT(ui32Base == CCM0_BASE);
149 
150  //
151  // Write the seed value to the seed register.
152  //
153  HWREG(ui32Base + CCM_O_CRCSEED) = ui32Seed;
154 }
155 
156 //*****************************************************************************
157 //
173 //
174 //*****************************************************************************
175 void
176 CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
177 {
178  //
179  // Check the arguments.
180  //
181  ASSERT(ui32Base == CCM0_BASE);
182 
183  //
184  // Write the data
185  //
186  HWREG(ui32Base + CCM_O_CRCDIN) = ui32Data;
187 }
188 
189 //*****************************************************************************
190 //
203 //
204 //*****************************************************************************
205 uint32_t
206 CRCResultRead(uint32_t ui32Base, bool bPPResult)
207 {
208  //
209  // Check the arguments.
210  //
211  ASSERT(ui32Base == CCM0_BASE);
212 
213  //
214  // Depending on the value of bPPResult, read the appropriate register and
215  // return value.
216  //
217  if(bPPResult)
218  {
219  return(HWREG(ui32Base + CCM_O_CRCRSLTPP));
220  }
221  else
222  {
223  return(HWREG(ui32Base + CCM_O_CRCSEED));
224  }
225 }
226 
227 //*****************************************************************************
228 //
251 //
252 //*****************************************************************************
253 uint32_t
254 CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn,
255  uint32_t ui32DataLength, bool bPPResult)
256 {
257  uint8_t *pui8DataIn;
258 
259  //
260  // Check the arguments.
261  //
262  ASSERT(ui32Base == CCM0_BASE);
263 
264  //
265  // See if the CRC is operating in 8-bit or 32-bit mode.
266  //
267  if(HWREG(ui32Base + CCM_O_CRCCTRL) & CCM_CRCCTRL_SIZE)
268  {
269  //
270  // The CRC is operating in 8-bit mode, so create an 8-bit pointer to
271  // the data.
272  //
273  pui8DataIn = (uint8_t *)pui32DataIn;
274 
275  //
276  // Loop through the input data.
277  //
278  while(ui32DataLength--)
279  {
280  //
281  // Write the next data byte.
282  //
283  HWREG(ui32Base + CCM_O_CRCDIN) = *pui8DataIn++;
284  }
285  }
286  else
287  {
288  //
289  // The CRC is operating in 32-bit mode, so loop through the input data.
290  //
291  while(ui32DataLength--)
292  {
293  //
294  // Write the next data word.
295  //
296  HWREG(ui32Base + CCM_O_CRCDIN) = *pui32DataIn++;
297  }
298  }
299 
300  //
301  // Return the result.
302  //
303  return(CRCResultRead(ui32Base, bPPResult));
304 }
305 
306 //*****************************************************************************
307 //
308 // Close the Doxygen group.
310 //
311 //*****************************************************************************
void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
Definition: crc.c:98
#define CRC_CFG_ENDIAN_SHW
Definition: crc.h:69
#define HWREG(x)
Definition: hw_types.h:48
#define CRC_CFG_INIT_SEED
Definition: crc.h:60
#define CRC_CFG_RESINV
Definition: crc.h:65
#define ASSERT(expr)
Definition: debug.h:67
#define CRC_CFG_INIT_1
Definition: crc.h:62
#define CRC_CFG_TYPE_P1EDC6F41
Definition: crc.h:73
#define CCM_O_CRCCTRL
Definition: hw_ccm.h:48
#define CCM_O_CRCDIN
Definition: hw_ccm.h:50
uint32_t CRCDataProcess(uint32_t ui32Base, uint32_t *pui32DataIn, uint32_t ui32DataLength, bool bPPResult)
Definition: crc.c:254
#define CRC_CFG_SIZE_8BIT
Definition: crc.h:63
#define CRC_CFG_OBR
Definition: crc.h:66
#define CRC_CFG_INIT_0
Definition: crc.h:61
#define CRC_CFG_IBR
Definition: crc.h:67
#define CRC_CFG_TYPE_P8005
Definition: crc.h:70
#define CCM_O_CRCRSLTPP
Definition: hw_ccm.h:51
#define CRC_CFG_TYPE_TCPCHKSUM
Definition: crc.h:74
#define CRC_CFG_SIZE_32BIT
Definition: crc.h:64
uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult)
Definition: crc.c:206
#define CCM_O_CRCSEED
Definition: hw_ccm.h:49
#define CCM0_BASE
Definition: hw_memmap.h:138
#define CCM_CRCCTRL_SIZE
Definition: hw_ccm.h:63
void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
Definition: crc.c:176
#define CRC_CFG_ENDIAN_SBHW
Definition: crc.h:68
void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
Definition: crc.c:143
#define CRC_CFG_TYPE_P4C11DB7
Definition: crc.h:72
#define CRC_CFG_TYPE_P1021
Definition: crc.h:71