EE445M RTOS
Taken at the University of Texas Spring 2015
Crc_api

Functions

void CRCConfigSet (uint32_t ui32Base, uint32_t ui32CRCConfig)
 
void CRCSeedSet (uint32_t ui32Base, uint32_t ui32Seed)
 
void CRCDataWrite (uint32_t ui32Base, uint32_t ui32Data)
 
uint32_t CRCResultRead (uint32_t ui32Base, bool bPPResult)
 
uint32_t CRCDataProcess (uint32_t ui32Base, uint32_t *pui32DataIn, uint32_t ui32DataLength, bool bPPResult)
 

Detailed Description

Function Documentation

void CRCConfigSet ( uint32_t  ui32Base,
uint32_t  ui32CRCConfig 
)

Set the configuration of CRC functionality with the EC module.

Parameters
ui32Baseis the base address of the EC module.
ui32CRCConfigis the configuration of the CRC engine.

This function configures the operation of the CRC engine within the EC module. The configuration is specified with the ui32CRCConfig argument. It is the logical OR of any of the following options:

CRC Initialization Value

  • CRC_CFG_INIT_SEED - Initialize with seed value
  • CRC_CFG_INIT_0 - Initialize to all '0s'
  • CRC_CFG_INIT_1 - Initialize to all '1s'

Input Data Size

  • CRC_CFG_SIZE_8BIT - Input data size of 8 bits
  • CRC_CFG_SIZE_32BIT - Input data size of 32 bits

Post Process Reverse/Inverse

  • CRC_CFG_RESINV - Result inverse enable
  • CRC_CFG_OBR - Output reverse enable

Input Bit Reverse

  • CRC_CFG_IBR - Bit reverse enable

Endian Control

  • CRC_CFG_ENDIAN_SBHW - Swap byte in half-word
  • CRC_CFG_ENDIAN_SHW - Swap half-word

Operation Type

  • CRC_CFG_TYPE_P8005 - Polynomial 0x8005
  • CRC_CFG_TYPE_P1021 - Polynomial 0x1021
  • CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7
  • CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41
  • CRC_CFG_TYPE_TCPCHKSUM - TCP checksum
Returns
None.

Definition at line 98 of file crc.c.

References ASSERT, CCM0_BASE, CCM_O_CRCCTRL, CRC_CFG_ENDIAN_SBHW, CRC_CFG_ENDIAN_SHW, CRC_CFG_IBR, CRC_CFG_INIT_0, CRC_CFG_INIT_1, CRC_CFG_INIT_SEED, CRC_CFG_OBR, CRC_CFG_RESINV, CRC_CFG_SIZE_32BIT, CRC_CFG_SIZE_8BIT, CRC_CFG_TYPE_P1021, CRC_CFG_TYPE_P1EDC6F41, CRC_CFG_TYPE_P4C11DB7, CRC_CFG_TYPE_P8005, CRC_CFG_TYPE_TCPCHKSUM, and HWREG.

99 {
100  //
101  // Check the arguments.
102  //
103  ASSERT(ui32Base == CCM0_BASE);
104  ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
105  (ui32CRCConfig & CRC_CFG_INIT_0) ||
106  (ui32CRCConfig & CRC_CFG_INIT_1) ||
107  (ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
108  (ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
109  (ui32CRCConfig & CRC_CFG_RESINV) ||
110  (ui32CRCConfig & CRC_CFG_OBR) ||
111  (ui32CRCConfig & CRC_CFG_IBR) ||
112  (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
113  (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
114  (ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
115  (ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
116  (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
117  (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
118  (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
119 
120  //
121  // Write the control register with the configuration.
122  //
123  HWREG(ui32Base + CCM_O_CRCCTRL) = ui32CRCConfig;
124 }
#define CRC_CFG_ENDIAN_SHW
Definition: crc.h:69
#define HWREG(x)
Definition: hw_types.h:48
#define CRC_CFG_INIT_SEED
Definition: crc.h:60
#define CRC_CFG_RESINV
Definition: crc.h:65
#define ASSERT(expr)
Definition: debug.h:67
#define CRC_CFG_INIT_1
Definition: crc.h:62
#define CRC_CFG_TYPE_P1EDC6F41
Definition: crc.h:73
#define CCM_O_CRCCTRL
Definition: hw_ccm.h:48
#define CRC_CFG_SIZE_8BIT
Definition: crc.h:63
#define CRC_CFG_OBR
Definition: crc.h:66
#define CRC_CFG_INIT_0
Definition: crc.h:61
#define CRC_CFG_IBR
Definition: crc.h:67
#define CRC_CFG_TYPE_P8005
Definition: crc.h:70
#define CRC_CFG_TYPE_TCPCHKSUM
Definition: crc.h:74
#define CRC_CFG_SIZE_32BIT
Definition: crc.h:64
#define CCM0_BASE
Definition: hw_memmap.h:138
#define CRC_CFG_ENDIAN_SBHW
Definition: crc.h:68
#define CRC_CFG_TYPE_P4C11DB7
Definition: crc.h:72
#define CRC_CFG_TYPE_P1021
Definition: crc.h:71
uint32_t CRCDataProcess ( uint32_t  ui32Base,
uint32_t *  pui32DataIn,
uint32_t  ui32DataLength,
bool  bPPResult 
)

Process data to generate a CRC with the EC module.

Parameters
ui32Baseis the base address of the EC module.
pui32DataInis a pointer to an array of data that is processed.
ui32DataLengthis the number of data items that are processed to produce the CRC.
bPPResultis true to read the post-processed result, or false to read the unmodified result.

This function processes an array of data to produce a CRC result.

The data in the array pointed to be pui32DataIn is either an array of bytes or an array or words depending on the selection of the input data size options CRC_CFG_SIZE_8BIT and CRC_CFG_SIZE_32BIT.

This function returns either the unmodified CRC result or the post- processed CRC result from the EC module. The post-processing options are selectable through CRC_CFG_RESINV and CRC_CFG_OBR parameters.

Returns
The CRC result.

Definition at line 254 of file crc.c.

References ASSERT, CCM0_BASE, CCM_CRCCTRL_SIZE, CCM_O_CRCCTRL, CCM_O_CRCDIN, CRCResultRead(), and HWREG.

256 {
257  uint8_t *pui8DataIn;
258 
259  //
260  // Check the arguments.
261  //
262  ASSERT(ui32Base == CCM0_BASE);
263 
264  //
265  // See if the CRC is operating in 8-bit or 32-bit mode.
266  //
267  if(HWREG(ui32Base + CCM_O_CRCCTRL) & CCM_CRCCTRL_SIZE)
268  {
269  //
270  // The CRC is operating in 8-bit mode, so create an 8-bit pointer to
271  // the data.
272  //
273  pui8DataIn = (uint8_t *)pui32DataIn;
274 
275  //
276  // Loop through the input data.
277  //
278  while(ui32DataLength--)
279  {
280  //
281  // Write the next data byte.
282  //
283  HWREG(ui32Base + CCM_O_CRCDIN) = *pui8DataIn++;
284  }
285  }
286  else
287  {
288  //
289  // The CRC is operating in 32-bit mode, so loop through the input data.
290  //
291  while(ui32DataLength--)
292  {
293  //
294  // Write the next data word.
295  //
296  HWREG(ui32Base + CCM_O_CRCDIN) = *pui32DataIn++;
297  }
298  }
299 
300  //
301  // Return the result.
302  //
303  return(CRCResultRead(ui32Base, bPPResult));
304 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define CCM_O_CRCCTRL
Definition: hw_ccm.h:48
#define CCM_O_CRCDIN
Definition: hw_ccm.h:50
uint32_t CRCResultRead(uint32_t ui32Base, bool bPPResult)
Definition: crc.c:206
#define CCM0_BASE
Definition: hw_memmap.h:138
#define CCM_CRCCTRL_SIZE
Definition: hw_ccm.h:63

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void CRCDataWrite ( uint32_t  ui32Base,
uint32_t  ui32Data 
)

Write data into the EC module for CRC operations.

Parameters
ui32Baseis the base address of the EC module.
ui32Datais the data to be written.

This function writes either 8 or 32 bits of data into the EC module for CRC operations. The distinction between 8 and 32 bits of data is made when the CRC_CFG_SIZE_8BIT or CRC_CFG_SIZE_32BIT flag is set using the CRCConfigSet() function.

When writing 8 bits of data, ensure the data is in the least significant byte position. The remaining bytes should be written with zero. For example, when writing 0xAB, ui32Data should be 0x000000AB.

Returns
None

Definition at line 176 of file crc.c.

References ASSERT, CCM0_BASE, CCM_O_CRCDIN, and HWREG.

177 {
178  //
179  // Check the arguments.
180  //
181  ASSERT(ui32Base == CCM0_BASE);
182 
183  //
184  // Write the data
185  //
186  HWREG(ui32Base + CCM_O_CRCDIN) = ui32Data;
187 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define CCM_O_CRCDIN
Definition: hw_ccm.h:50
#define CCM0_BASE
Definition: hw_memmap.h:138
uint32_t CRCResultRead ( uint32_t  ui32Base,
bool  bPPResult 
)

Reads the result of a CRC operation in the EC module.

Parameters
ui32Baseis the base address of the EC module.
bPPResultis true to read the post-processed result, or false to read the unmodified result.

This function reads either the unmodified CRC result or the post processed CRC result from the EC module. The post-processing options are selectable through CRC_CFG_RESINV and CRC_CFG_OBR parameters in the CRCConfigSet() function.

Returns
The CRC result.

Definition at line 206 of file crc.c.

References ASSERT, CCM0_BASE, CCM_O_CRCRSLTPP, CCM_O_CRCSEED, and HWREG.

Referenced by CRCDataProcess().

207 {
208  //
209  // Check the arguments.
210  //
211  ASSERT(ui32Base == CCM0_BASE);
212 
213  //
214  // Depending on the value of bPPResult, read the appropriate register and
215  // return value.
216  //
217  if(bPPResult)
218  {
219  return(HWREG(ui32Base + CCM_O_CRCRSLTPP));
220  }
221  else
222  {
223  return(HWREG(ui32Base + CCM_O_CRCSEED));
224  }
225 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define CCM_O_CRCRSLTPP
Definition: hw_ccm.h:51
#define CCM_O_CRCSEED
Definition: hw_ccm.h:49
#define CCM0_BASE
Definition: hw_memmap.h:138

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void CRCSeedSet ( uint32_t  ui32Base,
uint32_t  ui32Seed 
)

Write the seed value for CRC operations in the EC module.

Parameters
ui32Baseis the base address of the EC module.
ui32Seedis the seed value.

This function writes the seed value for use with CRC operations in the EC module. This value is the start value for CRC operations. If this value is not written, then the residual seed from the previous operation is used as the starting value.

Note
The seed must be written only if CRC_CFG_INIT_SEED is set with the CRCConfigSet() function.

Definition at line 143 of file crc.c.

References ASSERT, CCM0_BASE, CCM_O_CRCSEED, and HWREG.

144 {
145  //
146  // Check the arguments.
147  //
148  ASSERT(ui32Base == CCM0_BASE);
149 
150  //
151  // Write the seed value to the seed register.
152  //
153  HWREG(ui32Base + CCM_O_CRCSEED) = ui32Seed;
154 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define CCM_O_CRCSEED
Definition: hw_ccm.h:49
#define CCM0_BASE
Definition: hw_memmap.h:138