EE445M RTOS
Taken at the University of Texas Spring 2015
Shamd5_api

Functions

void SHAMD5Reset (uint32_t ui32Base)
 
void SHAMD5DMAEnable (uint32_t ui32Base)
 
void SHAMD5DMADisable (uint32_t ui32Base)
 
uint32_t SHAMD5IntStatus (uint32_t ui32Base, bool bMasked)
 
void SHAMD5IntEnable (uint32_t ui32Base, uint32_t ui32IntFlags)
 
void SHAMD5IntDisable (uint32_t ui32Base, uint32_t ui32IntFlags)
 
void SHAMD5IntClear (uint32_t ui32Base, uint32_t ui32IntFlags)
 
void SHAMD5IntRegister (uint32_t ui32Base, void(*pfnHandler)(void))
 
void SHAMD5IntUnregister (uint32_t ui32Base)
 
void SHAMD5HashLengthSet (uint32_t ui32Base, uint32_t ui32Length)
 
void SHAMD5ConfigSet (uint32_t ui32Base, uint32_t ui32Mode)
 
bool SHAMD5DataWriteNonBlocking (uint32_t ui32Base, uint32_t *pui32Src)
 
void SHAMD5DataWrite (uint32_t ui32Base, uint32_t *pui32Src)
 
void SHAMD5ResultRead (uint32_t ui32Base, uint32_t *pui32Dest)
 
static void _SHAMD5DataWriteMultiple (uint32_t ui32Base, uint32_t *pui32DataSrc, uint32_t ui32DataLength)
 
void SHAMD5DataProcess (uint32_t ui32Base, uint32_t *pui32DataSrc, uint32_t ui32DataLength, uint32_t *pui32HashResult)
 
void SHAMD5HMACProcess (uint32_t ui32Base, uint32_t *pui32DataSrc, uint32_t ui32DataLength, uint32_t *pui32HashResult)
 
void SHAMD5HMACPPKeyGenerate (uint32_t ui32Base, uint32_t *pui32Key, uint32_t *pui32PPKey)
 
void SHAMD5HMACKeySet (uint32_t ui32Base, uint32_t *pui32Src)
 
void SHAMD5HMACPPKeySet (uint32_t ui32Base, uint32_t *pui32Src)
 

Detailed Description

Function Documentation

static void _SHAMD5DataWriteMultiple ( uint32_t  ui32Base,
uint32_t *  pui32DataSrc,
uint32_t  ui32DataLength 
)
static

Writes multiple words of data into the SHA/MD5 data registers.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32DataSrcis a pointer to an array of data to be written.
ui32DataLengthis the length of the data to be written in bytes.

This function writes a variable number of words into the SHA/MD5 data registers. The function waits for each block of data to be processed before another is written. The ui32DataLength parameter must be a multiple of 4 to fall on a word boundry.

Note
This function is used by SHAMD5DataProcess() and SHAMD5HMACProcess() to process data.
Returns
None.

Definition at line 712 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_INPUT_READY, SHAMD5_O_DATA_0_IN, SHAMD5_O_IRQSTATUS, and SHAMD5DataWrite().

Referenced by SHAMD5DataProcess(), and SHAMD5HMACProcess().

714 {
715  uint32_t ui32Idx, ui32Count;
716 
717  //
718  // Check the arguments.
719  //
720  ASSERT(ui32Base == SHAMD5_BASE);
721 
722  //
723  // Calculate the number of blocks of data.
724  //
725  ui32Count = ui32DataLength / 64;
726 
727  //
728  // Loop through all the blocks and write them into the data registers
729  // making sure to block additional operations until we can write the
730  // next 16 words.
731  //
732  for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
733  {
734  //
735  // Write the block of data.
736  //
737  SHAMD5DataWrite(ui32Base, pui32DataSrc);
738 
739  //
740  // Increment the pointer to next block of data.
741  //
742  pui32DataSrc += 16;
743  }
744 
745  //
746  // Calculate the remaining bytes of data that don't make up a full block.
747  //
748  ui32Count = ui32DataLength % 64;
749 
750  //
751  // If there are bytes that do not make up a whole block, then
752  // write them separately.
753  //
754  if(ui32Count)
755  {
756  //
757  // Wait until the engine has finished processing the previous block.
758  //
759  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) &
761  {
762  }
763 
764  //
765  // Loop through the remaining words.
766  //
767  for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
768  {
769  //
770  // Write the word into the data register.
771  //
772  HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Idx) = *pui32DataSrc++;
773  }
774  }
775 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_O_IRQSTATUS
Definition: hw_shamd5.h:86
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_DATA_0_IN
Definition: hw_shamd5.h:67
#define SHAMD5_INT_INPUT_READY
Definition: shamd5.h:80
void SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src)
Definition: shamd5.c:552

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void SHAMD5ConfigSet ( uint32_t  ui32Base,
uint32_t  ui32Mode 
)

Writes the mode in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
ui32Modeis the mode of the SHA/MD5 module.

This function writes the mode register configuring the SHA/MD5 module.

The ui32Mode parameter is a bit-wise OR of values:

  • SHAMD5_ALGO_MD5 - Regular hash with MD5
  • SHAMD5_ALGO_SHA1 - Regular hash with SHA-1
  • SHAMD5_ALGO_SHA224 - Regular hash with SHA-224
  • SHAMD5_ALGO_SHA256 - Regular hash with SHA-256
  • SHAMD5_ALGO_HMAC_MD5 - HMAC with MD5
  • SHAMD5_ALGO_HMAC_SHA1 - HMAC with SHA-1
  • SHAMD5_ALGO_HMAC_SHA224 - HMAC with SHA-224
  • SHAMD5_ALGO_HMAC_SHA256 - HMAC with SHA-256
Returns
None

Definition at line 469 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_ALGO_HMAC_MD5, SHAMD5_ALGO_HMAC_SHA1, SHAMD5_ALGO_HMAC_SHA224, SHAMD5_ALGO_HMAC_SHA256, SHAMD5_ALGO_MD5, SHAMD5_ALGO_SHA1, SHAMD5_ALGO_SHA224, SHAMD5_ALGO_SHA256, SHAMD5_BASE, and SHAMD5_O_MODE.

470 {
471  //
472  // Check the arguments.
473  //
474  ASSERT(ui32Base == SHAMD5_BASE);
475  ASSERT((ui32Mode == SHAMD5_ALGO_MD5) ||
476  (ui32Mode == SHAMD5_ALGO_SHA1) ||
477  (ui32Mode == SHAMD5_ALGO_SHA224) ||
478  (ui32Mode == SHAMD5_ALGO_SHA256) ||
479  (ui32Mode == SHAMD5_ALGO_HMAC_MD5) ||
480  (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) ||
481  (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) ||
482  (ui32Mode == SHAMD5_ALGO_HMAC_SHA256));
483 
484  //
485  // Write the value in the MODE register.
486  //
487  HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode;
488 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define SHAMD5_ALGO_HMAC_MD5
Definition: shamd5.h:64
#define SHAMD5_ALGO_SHA224
Definition: shamd5.h:62
#define SHAMD5_ALGO_SHA1
Definition: shamd5.h:61
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_ALGO_MD5
Definition: shamd5.h:60
#define SHAMD5_ALGO_HMAC_SHA1
Definition: shamd5.h:65
#define SHAMD5_ALGO_SHA256
Definition: shamd5.h:63
#define SHAMD5_ALGO_HMAC_SHA256
Definition: shamd5.h:67
#define SHAMD5_O_MODE
Definition: hw_shamd5.h:65
#define SHAMD5_ALGO_HMAC_SHA224
Definition: shamd5.h:66
void SHAMD5DataProcess ( uint32_t  ui32Base,
uint32_t *  pui32DataSrc,
uint32_t  ui32DataLength,
uint32_t *  pui32HashResult 
)

Compute a hash using the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32DataSrcis a pointer to an array of data that contains the data that will be hashed.
ui32DataLengthspecifies the length of the data to be hashed in bytes.
pui32HashResultis a pointer to an array that holds the result of the hashing operation.

This function computes the hash of an array of data using the SHA/MD5 module.

The length of the hash result is dependent on the algorithm that is in use. The following table shows the correct array size for each algorithm:


| Algorithm | Number of Words in Result |

| MD5 | 4 Words (128 bits) | | SHA-1 | 5 Words (160 bits) | | SHA-224 | 7 Words (224 bits) |

| SHA-256 | 8 Words (256 bits) |

Returns
None

Definition at line 808 of file shamd5.c.

References _SHAMD5DataWriteMultiple(), ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY, SHAMD5_INT_OUTPUT_READY, SHAMD5_O_IRQSTATUS, SHAMD5HashLengthSet(), and SHAMD5ResultRead().

810 {
811  //
812  // Check the arguments.
813  //
814  ASSERT(ui32Base == SHAMD5_BASE);
815  ASSERT((ui32DataLength % 64) == 0);
816 
817  //
818  // Wait for the context to be ready before writing the mode.
819  //
820  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
821  0)
822  {
823  }
824 
825  //
826  // Write the length.
827  //
828  SHAMD5HashLengthSet(ui32Base, ui32DataLength);
829 
830  //
831  // Write the data.
832  //
833  _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength);
834 
835  //
836  // Wait for the output to be ready.
837  //
838  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
839  0)
840  {
841  }
842 
843  //
844  // Read the result.
845  //
846  SHAMD5ResultRead(ui32Base, pui32HashResult);
847 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest)
Definition: shamd5.c:592
#define SHAMD5_O_IRQSTATUS
Definition: hw_shamd5.h:86
#define SHAMD5_INT_OUTPUT_READY
Definition: shamd5.h:81
#define ASSERT(expr)
Definition: debug.h:67
void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length)
Definition: shamd5.c:432
static void _SHAMD5DataWriteMultiple(uint32_t ui32Base, uint32_t *pui32DataSrc, uint32_t ui32DataLength)
Definition: shamd5.c:712
#define SHAMD5_INT_CONTEXT_READY
Definition: shamd5.h:76

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void SHAMD5DataWrite ( uint32_t  ui32Base,
uint32_t *  pui32Src 
)

Perform a blocking write of 16 words of data to the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32Srcis the pointer to the 16-word array of data that will be written.

This function does not return until the module is ready to accept data and the data has been written.

Returns
None.

Definition at line 552 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_INPUT_READY, SHAMD5_O_DATA_0_IN, and SHAMD5_O_IRQSTATUS.

Referenced by _SHAMD5DataWriteMultiple().

553 {
554  uint32_t ui32Counter;
555 
556  //
557  // Check the arguments.
558  //
559  ASSERT(ui32Base == SHAMD5_BASE);
560 
561  //
562  // Wait for the module to be ready to accept data.
563  //
564  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
565  {
566  }
567 
568  //
569  // Write the 16 words of data.
570  //
571  for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4)
572  {
573  HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++;
574  }
575 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_O_IRQSTATUS
Definition: hw_shamd5.h:86
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_DATA_0_IN
Definition: hw_shamd5.h:67
#define SHAMD5_INT_INPUT_READY
Definition: shamd5.h:80

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bool SHAMD5DataWriteNonBlocking ( uint32_t  ui32Base,
uint32_t *  pui32Src 
)

Perform a non-blocking write of 16 words of data to the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32Srcis the pointer to the 16-word array of data that will be written.

This function writes 16 words of data into the data register regardless of whether or not the module is ready to accept the data.

Returns
This function returns true if the write completed successfully. It returns false if the module was not ready.

Definition at line 506 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_INPUT_READY, SHAMD5_O_DATA_0_IN, and SHAMD5_O_IRQSTATUS.

507 {
508  uint32_t ui32Counter;
509 
510  //
511  // Check the arguments.
512  //
513  ASSERT(ui32Base == SHAMD5_BASE);
514 
515  //
516  // Check that the SHA/MD5 module is ready for data. If not, return false.
517  //
518  if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
519  {
520  return(false);
521  }
522 
523  //
524  // Write the 16 words of data.
525  //
526  for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4)
527  {
528  HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++;
529  }
530 
531  //
532  // Return true as a sign of successfully completing the function.
533  //
534  return(true);
535 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_O_IRQSTATUS
Definition: hw_shamd5.h:86
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_DATA_0_IN
Definition: hw_shamd5.h:67
#define SHAMD5_INT_INPUT_READY
Definition: shamd5.h:80
void SHAMD5DMADisable ( uint32_t  ui32Base)

Disables the uDMA requests in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.

This function configures the DMA options of the SHA/MD5 module.

Returns
None

Definition at line 137 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_O_SYSCONFIG, SHAMD5_SYSCONFIG_DMA_EN, and SHAMD5_SYSCONFIG_SADVANCED.

138 {
139  //
140  // Check the arguments.
141  //
142  ASSERT(ui32Base == SHAMD5_BASE);
143 
144  //
145  // Write the new configuration into the register.
146  //
147  HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &=
149 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define SHAMD5_SYSCONFIG_DMA_EN
Definition: hw_shamd5.h:460
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_SYSCONFIG
Definition: hw_shamd5.h:84
#define SHAMD5_SYSCONFIG_SADVANCED
Definition: hw_shamd5.h:454
void SHAMD5DMAEnable ( uint32_t  ui32Base)

Enables the uDMA requests in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.

This function configures the DMA options of the SHA/MD5 module.

Returns
None

Definition at line 111 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_O_SYSCONFIG, SHAMD5_SYSCONFIG_DMA_EN, and SHAMD5_SYSCONFIG_SADVANCED.

112 {
113  //
114  // Check the arguments.
115  //
116  ASSERT(ui32Base == SHAMD5_BASE);
117 
118  //
119  // Write the new configuration into the register.
120  //
121  HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |=
123 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define SHAMD5_SYSCONFIG_DMA_EN
Definition: hw_shamd5.h:460
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_SYSCONFIG
Definition: hw_shamd5.h:84
#define SHAMD5_SYSCONFIG_SADVANCED
Definition: hw_shamd5.h:454
void SHAMD5HashLengthSet ( uint32_t  ui32Base,
uint32_t  ui32Length 
)

Write the hash length to the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
ui32Lengthis the hash length in bytes.

This function writes the length of the hash data of the current operation to the SHA/MD5 module. The value must be a multiple of 64 if the close hash is not set in the mode register.

Note
When this register is written, hash processing is triggered.
Returns
None.

Definition at line 432 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, and SHAMD5_O_LENGTH.

Referenced by SHAMD5DataProcess(), and SHAMD5HMACProcess().

433 {
434  //
435  // Check the arguments.
436  //
437  ASSERT(ui32Base == SHAMD5_BASE);
438 
439  //
440  // Set the LENGTH register and start processing.
441  //
442  HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length;
443 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_LENGTH
Definition: hw_shamd5.h:66

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void SHAMD5HMACKeySet ( uint32_t  ui32Base,
uint32_t *  pui32Src 
)

Writes an HMAC key to the digest registers in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32Srcis the pointer to the 16-word array of the HMAC key.

This function is used to write HMAC key to the digest registers for key preprocessing. The size of pui32Src must be 512 bytes. If the key is less than 512 bytes, then it must be padded with zeros.

Note
It is recommended to use the SHAMD5IntStatus() function to check whether the context is ready before writing the key.
Returns
None

Definition at line 1014 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_MODE_CLOSE_HASH, SHAMD5_MODE_HMAC_KEY_PROC, SHAMD5_MODE_HMAC_OUTER_HASH, SHAMD5_O_MODE, and SHAMD5_O_ODIGEST_A.

1015 {
1016  uint32_t ui32Idx;
1017 
1018  //
1019  // Check the arguments.
1020  //
1021  ASSERT(ui32Base == SHAMD5_BASE);
1022 
1023  //
1024  // Write the key to the digest registers.
1025  //
1026  for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
1027  {
1028  HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++;
1029  }
1030 
1031  //
1032  // Configure the SHA engine for HMAC operation.
1033  //
1037 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_ODIGEST_A
Definition: hw_shamd5.h:48
#define SHAMD5_MODE_CLOSE_HASH
Definition: hw_shamd5.h:256
#define SHAMD5_MODE_HMAC_KEY_PROC
Definition: hw_shamd5.h:254
#define SHAMD5_O_MODE
Definition: hw_shamd5.h:65
#define SHAMD5_MODE_HMAC_OUTER_HASH
Definition: hw_shamd5.h:251
void SHAMD5HMACPPKeyGenerate ( uint32_t  ui32Base,
uint32_t *  pui32Key,
uint32_t *  pui32PPKey 
)

Process an HMAC key using the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32Keyis a pointer to an array that contains the key to be processed.
pui32PPKeyis the pointer to the array that contains the pre-processed key.

This function processes an HMAC key using the SHA/MD5. The resultant pre-processed key can then be used with later HMAC operations to speed processing time.

The pui32Key array must be 16 words (512 bits) long. If the key is less than 512 bits, it must be padded with zeros. The pui32PPKey array must each be 16 words (512 bits) long.

Returns
None

Definition at line 943 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY, SHAMD5_INT_OUTPUT_READY, SHAMD5_MODE_HMAC_KEY_PROC, SHAMD5_O_IRQSTATUS, SHAMD5_O_LENGTH, SHAMD5_O_MODE, and SHAMD5_O_ODIGEST_A.

945 {
946  uint32_t ui32Index;
947 
948  //
949  // Check the arguments.
950  //
951  ASSERT(ui32Base == SHAMD5_BASE);
952 
953  //
954  // Wait for the context to be ready before writing the mode.
955  //
956  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
957  0)
958  {
959  }
960 
961  //
962  // Write the HMAC key.
963  //
964  for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
965  {
966  HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index) = *pui32Key++;
967  }
968 
969  //
970  // Set the flag to cause the HMAC key to be pre-processed.
971  //
973 
974  //
975  // Set the length to zero to start the HMAC key pre-processing.
976  //
977  HWREG(ui32Base + SHAMD5_O_LENGTH) = 0;
978 
979  //
980  // Wait for key to be processed.
981  //
982  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
983  0)
984  {
985  }
986 
987  //
988  // Read the pre-processed key from the SHA/MD5 module.
989  //
990  for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
991  {
992  *pui32PPKey++ = HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index);
993  }
994 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_O_IRQSTATUS
Definition: hw_shamd5.h:86
#define SHAMD5_INT_OUTPUT_READY
Definition: shamd5.h:81
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_ODIGEST_A
Definition: hw_shamd5.h:48
#define SHAMD5_MODE_HMAC_KEY_PROC
Definition: hw_shamd5.h:254
#define SHAMD5_O_LENGTH
Definition: hw_shamd5.h:66
#define SHAMD5_O_MODE
Definition: hw_shamd5.h:65
#define SHAMD5_INT_CONTEXT_READY
Definition: shamd5.h:76
void SHAMD5HMACPPKeySet ( uint32_t  ui32Base,
uint32_t *  pui32Src 
)

Writes a pre-processed HMAC key to the digest registers in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32Srcis the pointer to the 16-word array of the HMAC key.

This function is used to write HMAC key to the digest registers for key preprocessing. The size of pui32Src must be 512 bytes. If the key is less than 512 bytes, then it must be padded with zeros.

Note
It is recommended to use the SHAMD5IntStatus() function to check whether the context is ready before writing the key.
Returns
None

Definition at line 1058 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_MODE_CLOSE_HASH, SHAMD5_MODE_HMAC_OUTER_HASH, SHAMD5_O_DIGEST_COUNT, SHAMD5_O_MODE, and SHAMD5_O_ODIGEST_A.

1059 {
1060  uint32_t ui32Idx;
1061 
1062  //
1063  // Check the arguments.
1064  //
1065  ASSERT(ui32Base == SHAMD5_BASE);
1066 
1067  //
1068  // Write the key to the digest registers.
1069  //
1070  for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
1071  {
1072  HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++;
1073  }
1074 
1075  //
1076  // Configure the SHA engine to continue the HMAC.
1077  //
1080 
1081  //
1082  // Write the digest count to 64 to account for the preprocessed key.
1083  //
1084  HWREG(ui32Base + SHAMD5_O_DIGEST_COUNT) = 64;
1085 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_DIGEST_COUNT
Definition: hw_shamd5.h:64
#define SHAMD5_O_ODIGEST_A
Definition: hw_shamd5.h:48
#define SHAMD5_MODE_CLOSE_HASH
Definition: hw_shamd5.h:256
#define SHAMD5_O_MODE
Definition: hw_shamd5.h:65
#define SHAMD5_MODE_HMAC_OUTER_HASH
Definition: hw_shamd5.h:251
void SHAMD5HMACProcess ( uint32_t  ui32Base,
uint32_t *  pui32DataSrc,
uint32_t  ui32DataLength,
uint32_t *  pui32HashResult 
)

Compute a HMAC with key pre-processing using the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32DataSrcis a pointer to an array of data that contains the data that is to be hashed.
ui32DataLengthspecifies the length of the data to be hashed in bytes.
pui32HashResultis a pointer to an array that holds the result of the hashing operation.

This function computes a HMAC with the given data using the SHA/MD5 module with a preprocessed key.

The length of the hash result is dependent on the algorithm that is selected with the ui32Algo argument. The following table shows the correct array size for each algorithm:


| Algorithm | Number of Words in Result |

| MD5 | 4 Words (128 bits) | | SHA-1 | 5 Words (160 bits) | | SHA-224 | 7 Words (224 bits) |

| SHA-256 | 8 Words (256 bits) |

Returns
None

Definition at line 881 of file shamd5.c.

References _SHAMD5DataWriteMultiple(), ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY, SHAMD5_INT_OUTPUT_READY, SHAMD5_O_IRQSTATUS, SHAMD5HashLengthSet(), and SHAMD5ResultRead().

883 {
884  //
885  // Check the arguments.
886  //
887  ASSERT(ui32Base == SHAMD5_BASE);
888 
889  //
890  // Wait for the context to be ready before writing the mode.
891  //
892  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
893  0)
894  {
895  }
896 
897  //
898  // Write the length.
899  //
900  SHAMD5HashLengthSet(ui32Base, ui32DataLength);
901 
902  //
903  // Write the data in the registers.
904  //
905  _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength);
906 
907  //
908  // Wait for the output to be ready.
909  //
910  while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
911  0)
912  {
913  }
914 
915  //
916  // Read the result.
917  //
918  SHAMD5ResultRead(ui32Base, pui32HashResult);
919 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
void SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest)
Definition: shamd5.c:592
#define SHAMD5_O_IRQSTATUS
Definition: hw_shamd5.h:86
#define SHAMD5_INT_OUTPUT_READY
Definition: shamd5.h:81
#define ASSERT(expr)
Definition: debug.h:67
void SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length)
Definition: shamd5.c:432
static void _SHAMD5DataWriteMultiple(uint32_t ui32Base, uint32_t *pui32DataSrc, uint32_t ui32DataLength)
Definition: shamd5.c:712
#define SHAMD5_INT_CONTEXT_READY
Definition: shamd5.h:76

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void SHAMD5IntClear ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)

Clears interrupt sources in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
ui32IntFlagscontains desired interrupts to disable.

ui32IntFlags must be a logical OR of one or more of the following values:

  • SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
  • SHAMD5_INT_PARTHASH_READY - Context output registers are ready after a context switch.
  • SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
  • SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
Returns
None.

Definition at line 318 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY, SHAMD5_INT_INPUT_READY, SHAMD5_INT_OUTPUT_READY, SHAMD5_INT_PARTHASH_READY, and SHAMD5_O_DMAIC.

319 {
320  //
321  // Check the arguments.
322  //
323  ASSERT(ui32Base == SHAMD5_BASE);
324  ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
325  (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
326  (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
327  (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
328 
329  //
330  // Clear the corresponding flags disabling the interrupt sources.
331  //
332  HWREG(ui32Base + SHAMD5_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 14) |
333  ((ui32IntFlags & 0x00020000) >> 16) |
334  ((ui32IntFlags & 0x00040000) >> 19));
335 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_INT_OUTPUT_READY
Definition: shamd5.h:81
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_DMAIC
Definition: hw_shamd5.h:91
#define SHAMD5_INT_INPUT_READY
Definition: shamd5.h:80
#define SHAMD5_INT_PARTHASH_READY
Definition: shamd5.h:78
#define SHAMD5_INT_CONTEXT_READY
Definition: shamd5.h:76
void SHAMD5IntDisable ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)

Disable interrupt sources in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
ui32IntFlagscontains desired interrupts to disable.

ui32IntFlags must be a logical OR of one or more of the following values:

  • SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
  • SHAMD5_INT_PARTHASH_READY - Context output registers are ready after a context switch.
  • SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
  • SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
Returns
None.

Definition at line 270 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY, SHAMD5_INT_INPUT_READY, SHAMD5_INT_OUTPUT_READY, SHAMD5_INT_PARTHASH_READY, SHAMD5_O_DMAIM, SHAMD5_O_IRQENABLE, SHAMD5_O_SYSCONFIG, and SHAMD5_SYSCONFIG_IT_EN.

271 {
272  //
273  // Check the arguments.
274  //
275  ASSERT(ui32Base == SHAMD5_BASE);
276  ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
277  (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
278  (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
279  (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
280 
281  //
282  // Clear the corresponding flags disabling the interrupt sources.
283  //
284  HWREG(ui32Base + SHAMD5_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 14) |
285  ((ui32IntFlags & 0x00020000) >> 16) |
286  ((ui32IntFlags & 0x00040000) >> 19));
287  HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
288 
289  //
290  // If there are no interrupts enabled, then disable all interrupts.
291  //
292  if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0)
293  {
295  }
296 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define SHAMD5_O_IRQENABLE
Definition: hw_shamd5.h:87
#define SHAMD5_O_DMAIM
Definition: hw_shamd5.h:88
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_INT_OUTPUT_READY
Definition: shamd5.h:81
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_INT_INPUT_READY
Definition: shamd5.h:80
#define SHAMD5_O_SYSCONFIG
Definition: hw_shamd5.h:84
#define SHAMD5_INT_PARTHASH_READY
Definition: shamd5.h:78
#define SHAMD5_INT_CONTEXT_READY
Definition: shamd5.h:76
#define SHAMD5_SYSCONFIG_IT_EN
Definition: hw_shamd5.h:461
void SHAMD5IntEnable ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)

Enable interrupt sources in the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
ui32IntFlagscontains desired interrupts to enable.

This function enables interrupt sources in the SHA/MD5 module. ui32IntFlags must be a logical OR of one or more of the following values:

  • SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
  • SHAMD5_INT_PARTHASH_READY - Context output registers are ready after a context switch.
  • SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
  • SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
Returns
None.

Definition at line 225 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY, SHAMD5_INT_INPUT_READY, SHAMD5_INT_OUTPUT_READY, SHAMD5_INT_PARTHASH_READY, SHAMD5_O_DMAIM, SHAMD5_O_IRQENABLE, SHAMD5_O_SYSCONFIG, and SHAMD5_SYSCONFIG_IT_EN.

226 {
227  //
228  // Check the arguments.
229  //
230  ASSERT(ui32Base == SHAMD5_BASE);
231  ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
232  (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
233  (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
234  (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
235 
236  //
237  // Enable the interrupt sources.
238  //
239  HWREG(ui32Base + SHAMD5_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 14) |
240  ((ui32IntFlags & 0x00020000) >> 16) |
241  ((ui32IntFlags & 0x00040000) >> 19));
242  HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
243 
244  //
245  // Enable all interrupts.
246  //
248 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define SHAMD5_O_IRQENABLE
Definition: hw_shamd5.h:87
#define SHAMD5_O_DMAIM
Definition: hw_shamd5.h:88
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_INT_OUTPUT_READY
Definition: shamd5.h:81
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_INT_INPUT_READY
Definition: shamd5.h:80
#define SHAMD5_O_SYSCONFIG
Definition: hw_shamd5.h:84
#define SHAMD5_INT_PARTHASH_READY
Definition: shamd5.h:78
#define SHAMD5_INT_CONTEXT_READY
Definition: shamd5.h:76
#define SHAMD5_SYSCONFIG_IT_EN
Definition: hw_shamd5.h:461
void SHAMD5IntRegister ( uint32_t  ui32Base,
void(*)(void)  pfnHandler 
)

Registers an interrupt handler for the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pfnHandleris a pointer to the function to be called when the enabled SHA/MD5 interrupts occur.

This function registers the interrupt handler in the interrupt vector table, and enables SHA/MD5 interrupts on the interrupt controller; specific SHA/MD5 interrupt sources must be enabled using SHAMD5IntEnable(). The interrupt handler being registered must clear the source of the interrupt using SHAMD5IntClear().

If the application is using a static interrupt vector table stored in flash, then it is not necessary to register the interrupt handler this way. Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the interrupt controller.

See also
IntRegister() for important information about registering interrupt handlers.
Returns
None.

Definition at line 363 of file shamd5.c.

References ASSERT, INT_SHA0_TM4C129, IntEnable(), IntRegister(), and SHAMD5_BASE.

364 {
365  //
366  // Check the arguments.
367  //
368  ASSERT(ui32Base == SHAMD5_BASE);
369 
370  //
371  // Register the interrupt handler.
372  //
373  IntRegister(INT_SHA0_TM4C129, pfnHandler);
374 
375  //
376  // Enable the interrupt
377  //
379 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define ASSERT(expr)
Definition: debug.h:67
#define INT_SHA0_TM4C129
Definition: hw_ints.h:268
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Definition: interrupt.c:309
void IntEnable(uint32_t ui32Interrupt)
Definition: interrupt.c:610

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uint32_t SHAMD5IntStatus ( uint32_t  ui32Base,
bool  bMasked 
)

Get the interrupt status of the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
bMaskedis false if the raw interrupt status is required and true if the masked interrupt status is required.

This function returns the current value of the IRQSTATUS register. The value will be a logical OR of the following:

  • SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
  • SHAMD5_INT_PARTHASH_READY - Context output registers are ready after a context switch.
  • SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
  • SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
Returns
Interrupt status

Definition at line 172 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_O_DMAMIS, SHAMD5_O_DMARIS, SHAMD5_O_IRQENABLE, and SHAMD5_O_IRQSTATUS.

173 {
174  uint32_t ui32Status, ui32Enable, ui32Temp;
175 
176  //
177  // Check the arguments.
178  //
179  ASSERT(ui32Base == SHAMD5_BASE);
180 
181  //
182  // Return the value of the IRQSTATUS register.
183  //
184  ui32Status = HWREG(ui32Base + SHAMD5_O_IRQSTATUS);
185  if(bMasked)
186  {
187  ui32Enable = HWREG(ui32Base + SHAMD5_O_IRQENABLE);
188  ui32Temp = HWREG(ui32Base + SHAMD5_O_DMAMIS);
189  return((ui32Status & ui32Enable) |
190  ((ui32Temp & 0x00000001) << 19) |
191  ((ui32Temp & 0x00000002) << 16) |
192  ((ui32Temp & 0x00000004) << 14));
193  }
194  else
195  {
196  ui32Temp = HWREG(ui32Base + SHAMD5_O_DMARIS);
197  return(ui32Status |
198  ((ui32Temp & 0x00000001) << 19) |
199  ((ui32Temp & 0x00000002) << 16) |
200  ((ui32Temp & 0x00000004) << 14));
201  }
202 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define SHAMD5_O_IRQENABLE
Definition: hw_shamd5.h:87
#define SHAMD5_O_DMARIS
Definition: hw_shamd5.h:89
#define SHAMD5_O_DMAMIS
Definition: hw_shamd5.h:90
#define HWREG(x)
Definition: hw_types.h:48
#define SHAMD5_O_IRQSTATUS
Definition: hw_shamd5.h:86
#define ASSERT(expr)
Definition: debug.h:67
void SHAMD5IntUnregister ( uint32_t  ui32Base)

Unregisters an interrupt handler for the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.

This function unregisters the previously registered interrupt handler and disables the interrupt in the interrupt controller.

See also
IntRegister() for important information about registering interrupt handlers.
Returns
None.

Definition at line 397 of file shamd5.c.

References ASSERT, INT_SHA0_TM4C129, IntDisable(), IntUnregister(), and SHAMD5_BASE.

398 {
399  //
400  // Check the arguments.
401  //
402  ASSERT(ui32Base == SHAMD5_BASE);
403 
404  //
405  // Disable the interrupt.
406  //
408 
409  //
410  // Unregister the interrupt handler.
411  //
413 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define ASSERT(expr)
Definition: debug.h:67
#define INT_SHA0_TM4C129
Definition: hw_ints.h:268
void IntUnregister(uint32_t ui32Interrupt)
Definition: interrupt.c:381
void IntDisable(uint32_t ui32Interrupt)
Definition: interrupt.c:684

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void SHAMD5Reset ( uint32_t  ui32Base)

Resets the SHA/MD5 module.

Parameters
ui32Baseis the base address of the SHA/MD5 module.

This function performs a soft-reset of the SHA/MD5 module using the SYSCONFIG register.

Returns
None.

Definition at line 71 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_O_SYSCONFIG, SHAMD5_O_SYSSTATUS, SHAMD5_SYSCONFIG_SIDLE_FORCE, SHAMD5_SYSCONFIG_SIDLE_M, SHAMD5_SYSCONFIG_SOFTRESET, and SHAMD5_SYSSTATUS_RESETDONE.

72 {
73  //
74  // Check the arguments.
75  //
76  ASSERT(ui32Base == SHAMD5_BASE);
77 
78  //
79  // Set the soft-reset bit.
80  //
82 
83  //
84  // Wait for the reset to complete.
85  //
86  while((HWREG(ui32Base + SHAMD5_O_SYSSTATUS) &
88  {
89  }
90 
91  //
92  // Force idle mode.
93  //
94  HWREG(ui32Base + SHAMD5_O_SYSCONFIG) =
97 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_SYSCONFIG_SIDLE_M
Definition: hw_shamd5.h:456
#define SHAMD5_SYSSTATUS_RESETDONE
Definition: hw_shamd5.h:471
#define SHAMD5_SYSCONFIG_SOFTRESET
Definition: hw_shamd5.h:462
#define SHAMD5_O_SYSCONFIG
Definition: hw_shamd5.h:84
#define SHAMD5_O_SYSSTATUS
Definition: hw_shamd5.h:85
#define SHAMD5_SYSCONFIG_SIDLE_FORCE
Definition: hw_shamd5.h:458
void SHAMD5ResultRead ( uint32_t  ui32Base,
uint32_t *  pui32Dest 
)

Reads the result of a hashing operation.

Parameters
ui32Baseis the base address of the SHA/MD5 module.
pui32Destis the pointer to the 16-word array of data that will be written.

This function does not return until the module is ready to accept data and the data has been written.

Returns
None.

Definition at line 592 of file shamd5.c.

References ASSERT, HWREG, SHAMD5_BASE, SHAMD5_MODE_ALGO_M, SHAMD5_MODE_ALGO_MD5, SHAMD5_MODE_ALGO_SHA1, SHAMD5_MODE_ALGO_SHA224, SHAMD5_MODE_ALGO_SHA256, SHAMD5_O_IDIGEST_A, and SHAMD5_O_MODE.

Referenced by SHAMD5DataProcess(), and SHAMD5HMACProcess().

593 {
594  uint32_t ui32Idx, ui32Count;
595 
596  //
597  // Check the arguments.
598  //
599  ASSERT(ui32Base == SHAMD5_BASE);
600 
601  //
602  // Determine the number of bytes in the result, based on the hash type.
603  //
604  switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M)
605  {
606  //
607  // The MD5 hash is being used.
608  //
610  {
611  //
612  // There are 16 bytes in the MD5 hash.
613  //
614  ui32Count = 16;
615 
616  //
617  // Done.
618  //
619  break;
620  }
621 
622  //
623  // The SHA-1 hash is being used.
624  //
626  {
627  //
628  // There are 20 bytes in the SHA-1 hash.
629  //
630  ui32Count = 20;
631 
632  //
633  // Done.
634  //
635  break;
636  }
637 
638  //
639  // The SHA-224 hash is being used.
640  //
642  {
643  //
644  // There are 28 bytes in the SHA-224 hash.
645  //
646  ui32Count = 28;
647 
648  //
649  // Done.
650  //
651  break;
652  }
653 
654  //
655  // The SHA-256 hash is being used.
656  //
658  {
659  //
660  // There are 32 bytes in the SHA-256 hash.
661  //
662  ui32Count = 32;
663 
664  //
665  // Done.
666  //
667  break;
668  }
669 
670  //
671  // The hash type is not recognized.
672  //
673  default:
674  {
675  //
676  // Return without reading a result since the hardware appears to be
677  // misconfigured.
678  //
679  return;
680  }
681  }
682 
683  //
684  // Read the hash result.
685  //
686  for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
687  {
688  *pui32Dest++ = HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx);
689  }
690 }
#define SHAMD5_BASE
Definition: hw_memmap.h:139
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define SHAMD5_O_IDIGEST_A
Definition: hw_shamd5.h:56
#define SHAMD5_O_MODE
Definition: hw_shamd5.h:65
#define SHAMD5_MODE_ALGO_SHA1
Definition: hw_shamd5.h:269
#define SHAMD5_MODE_ALGO_MD5
Definition: hw_shamd5.h:268
#define SHAMD5_MODE_ALGO_SHA224
Definition: hw_shamd5.h:270
#define SHAMD5_MODE_ALGO_SHA256
Definition: hw_shamd5.h:271
#define SHAMD5_MODE_ALGO_M
Definition: hw_shamd5.h:267

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