shamd5.c

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//*****************************************************************************
//
// shamd5.c - Driver for the SHA/MD5 module.
//
// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************

#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_nvic.h"
#include "inc/hw_shamd5.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/shamd5.h"

//*****************************************************************************
//
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5Reset(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Set the soft-reset bit.
    //
    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_SOFTRESET;

    //
    // Wait for the reset to complete.
    //
    while((HWREG(ui32Base + SHAMD5_O_SYSSTATUS) &
           SHAMD5_SYSSTATUS_RESETDONE) == 0)
    {
    }

    //
    // Force idle mode.
    //
    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) =
        ((HWREG(ui32Base + SHAMD5_O_SYSCONFIG) & ~SHAMD5_SYSCONFIG_SIDLE_M) |
         SHAMD5_SYSCONFIG_SIDLE_FORCE);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5DMAEnable(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Write the new configuration into the register.
    //
    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |=
        SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5DMADisable(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Write the new configuration into the register.
    //
    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &=
        ~(SHAMD5_SYSCONFIG_SADVANCED | SHAMD5_SYSCONFIG_DMA_EN);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
SHAMD5IntStatus(uint32_t ui32Base, bool bMasked)
{
    uint32_t ui32Status, ui32Enable, ui32Temp;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Return the value of the IRQSTATUS register.
    //
    ui32Status = HWREG(ui32Base + SHAMD5_O_IRQSTATUS);
    if(bMasked)
    {
        ui32Enable = HWREG(ui32Base + SHAMD5_O_IRQENABLE);
        ui32Temp = HWREG(ui32Base + SHAMD5_O_DMAMIS);
        return((ui32Status & ui32Enable) |
               ((ui32Temp & 0x00000001) << 19) |
               ((ui32Temp & 0x00000002) << 16) |
               ((ui32Temp & 0x00000004) << 14));
    }
    else
    {
        ui32Temp = HWREG(ui32Base + SHAMD5_O_DMARIS);
        return(ui32Status |
               ((ui32Temp & 0x00000001) << 19) |
               ((ui32Temp & 0x00000002) << 16) |
               ((ui32Temp & 0x00000004) << 14));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);
    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));

    //
    // Enable the interrupt sources.
    //
    HWREG(ui32Base + SHAMD5_O_DMAIM) |= (((ui32IntFlags & 0x00010000) >> 14) |
                                         ((ui32IntFlags & 0x00020000) >> 16) |
                                         ((ui32IntFlags & 0x00040000) >> 19));
    HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;

    //
    // Enable all interrupts.
    //
    HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_IT_EN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);
    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));

    //
    // Clear the corresponding flags disabling the interrupt sources.
    //
    HWREG(ui32Base + SHAMD5_O_DMAIM) &= ~(((ui32IntFlags & 0x00010000) >> 14) |
                                          ((ui32IntFlags & 0x00020000) >> 16) |
                                          ((ui32IntFlags & 0x00040000) >> 19));
    HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);

    //
    // If there are no interrupts enabled, then disable all interrupts.
    //
    if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0)
    {
        HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_IT_EN;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);
    ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
           (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
           (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
           (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));

    //
    // Clear the corresponding flags disabling the interrupt sources.
    //
    HWREG(ui32Base + SHAMD5_O_DMAIC) = (((ui32IntFlags & 0x00010000) >> 14) |
                                        ((ui32IntFlags & 0x00020000) >> 16) |
                                        ((ui32IntFlags & 0x00040000) >> 19));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5IntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Register the interrupt handler.
    //
    IntRegister(INT_SHA0_TM4C129, pfnHandler);

    //
    // Enable the interrupt
    //
    IntEnable(INT_SHA0_TM4C129);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5IntUnregister(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Disable the interrupt.
    //
    IntDisable(INT_SHA0_TM4C129);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(INT_SHA0_TM4C129);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5HashLengthSet(uint32_t ui32Base, uint32_t ui32Length)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Set the LENGTH register and start processing.
    //
    HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);
    ASSERT((ui32Mode == SHAMD5_ALGO_MD5) ||
           (ui32Mode == SHAMD5_ALGO_SHA1) ||
           (ui32Mode == SHAMD5_ALGO_SHA224) ||
           (ui32Mode == SHAMD5_ALGO_SHA256) ||
           (ui32Mode == SHAMD5_ALGO_HMAC_MD5) ||
           (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) ||
           (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) ||
           (ui32Mode == SHAMD5_ALGO_HMAC_SHA256));

    //
    // Write the value in the MODE register.
    //
    HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode;
}

//*****************************************************************************
//
//
//*****************************************************************************
bool
SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src)
{
    uint32_t ui32Counter;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Check that the SHA/MD5 module is ready for data.  If not, return false.
    //
    if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
    {
        return(false);
    }

    //
    // Write the 16 words of data.
    //
    for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4)
    {
        HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++;
    }

    //
    // Return true as a sign of successfully completing the function.
    //
    return(true);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5DataWrite(uint32_t ui32Base, uint32_t *pui32Src)
{
    uint32_t ui32Counter;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Wait for the module to be ready to accept data.
    //
    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
    {
    }

    //
    // Write the 16 words of data.
    //
    for(ui32Counter = 0; ui32Counter < 64; ui32Counter += 4)
    {
        HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Counter) = *pui32Src++;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5ResultRead(uint32_t ui32Base, uint32_t *pui32Dest)
{
    uint32_t ui32Idx, ui32Count;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Determine the number of bytes in the result, based on the hash type.
    //
    switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M)
    {
        //
        // The MD5 hash is being used.
        //
        case SHAMD5_MODE_ALGO_MD5:
        {
            //
            // There are 16 bytes in the MD5 hash.
            //
            ui32Count = 16;

            //
            // Done.
            //
            break;
        }

        //
        // The SHA-1 hash is being used.
        //
        case SHAMD5_MODE_ALGO_SHA1:
        {
            //
            // There are 20 bytes in the SHA-1 hash.
            //
            ui32Count = 20;

            //
            // Done.
            //
            break;
        }

        //
        // The SHA-224 hash is being used.
        //
        case SHAMD5_MODE_ALGO_SHA224:
        {
            //
            // There are 28 bytes in the SHA-224 hash.
            //
            ui32Count = 28;

            //
            // Done.
            //
            break;
        }

        //
        // The SHA-256 hash is being used.
        //
        case SHAMD5_MODE_ALGO_SHA256:
        {
            //
            // There are 32 bytes in the SHA-256 hash.
            //
            ui32Count = 32;

            //
            // Done.
            //
            break;
        }

        //
        // The hash type is not recognized.
        //
        default:
        {
            //
            // Return without reading a result since the hardware appears to be
            // misconfigured.
            //
            return;
        }
    }

    //
    // Read the hash result.
    //
    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
    {
        *pui32Dest++ = HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
static void
_SHAMD5DataWriteMultiple(uint32_t ui32Base, uint32_t *pui32DataSrc,
                         uint32_t ui32DataLength)
{
    uint32_t ui32Idx, ui32Count;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Calculate the number of blocks of data.
    //
    ui32Count = ui32DataLength / 64;

    //
    // Loop through all the blocks and write them into the data registers
    // making sure to block additional operations until we can write the
    // next 16 words.
    //
    for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
    {
        //
        // Write the block of data.
        //
        SHAMD5DataWrite(ui32Base, pui32DataSrc);

        //
        // Increment the pointer to next block of data.
        //
        pui32DataSrc += 16;
    }

    //
    // Calculate the remaining bytes of data that don't make up a full block.
    //
    ui32Count = ui32DataLength % 64;

    //
    // If there are bytes that do not make up a whole block, then
    // write them separately.
    //
    if(ui32Count)
    {
        //
        // Wait until the engine has finished processing the previous block.
        //
        while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) &
               SHAMD5_INT_INPUT_READY) == 0)
        {
        }

        //
        // Loop through the remaining words.
        //
        for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
        {
            //
            // Write the word into the data register.
            //
            HWREG(ui32Base + SHAMD5_O_DATA_0_IN + ui32Idx) = *pui32DataSrc++;
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5DataProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
                  uint32_t ui32DataLength, uint32_t *pui32HashResult)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);
    ASSERT((ui32DataLength % 64) == 0);

    //
    // Wait for the context to be ready before writing the mode.
    //
    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
          0)
    {
    }

    //
    // Write the length.
    //
    SHAMD5HashLengthSet(ui32Base, ui32DataLength);

    //
    // Write the data.
    //
    _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength);

    //
    // Wait for the output to be ready.
    //
    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
          0)
    {
    }

    //
    // Read the result.
    //
    SHAMD5ResultRead(ui32Base, pui32HashResult);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5HMACProcess(uint32_t ui32Base, uint32_t *pui32DataSrc,
                  uint32_t ui32DataLength, uint32_t *pui32HashResult)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Wait for the context to be ready before writing the mode.
    //
    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
          0)
    {
    }

    //
    // Write the length.
    //
    SHAMD5HashLengthSet(ui32Base, ui32DataLength);

    //
    // Write the data in the registers.
    //
    _SHAMD5DataWriteMultiple(ui32Base, pui32DataSrc, ui32DataLength);

    //
    // Wait for the output to be ready.
    //
    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
          0)
    {
    }

    //
    // Read the result.
    //
    SHAMD5ResultRead(ui32Base, pui32HashResult);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint32_t *pui32Key,
                        uint32_t *pui32PPKey)
{
    uint32_t ui32Index;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Wait for the context to be ready before writing the mode.
    //
    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) ==
          0)
    {
    }

    //
    // Write the HMAC key.
    //
    for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
    {
        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index) = *pui32Key++;
    }

    //
    // Set the flag to cause the HMAC key to be pre-processed.
    //
    HWREG(ui32Base + SHAMD5_O_MODE) |= SHAMD5_MODE_HMAC_KEY_PROC;

    //
    // Set the length to zero to start the HMAC key pre-processing.
    //
    HWREG(ui32Base + SHAMD5_O_LENGTH) = 0;

    //
    // Wait for key to be processed.
    //
    while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) ==
          0)
    {
    }

    //
    // Read the pre-processed key from the SHA/MD5 module.
    //
    for(ui32Index = 0; ui32Index < 64; ui32Index += 4)
    {
        *pui32PPKey++ = HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Index);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5HMACKeySet(uint32_t ui32Base, uint32_t *pui32Src)
{
    uint32_t ui32Idx;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Write the key to the digest registers.
    //
    for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
    {
        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++;
    }

    //
    // Configure the SHA engine for HMAC operation.
    //
    HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH |
                                        SHAMD5_MODE_HMAC_KEY_PROC |
                                        SHAMD5_MODE_CLOSE_HASH);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
SHAMD5HMACPPKeySet(uint32_t ui32Base, uint32_t *pui32Src)
{
    uint32_t ui32Idx;

    //
    // Check the arguments.
    //
    ASSERT(ui32Base == SHAMD5_BASE);

    //
    // Write the key to the digest registers.
    //
    for(ui32Idx = 0; ui32Idx < 64; ui32Idx += 4)
    {
        HWREG(ui32Base + SHAMD5_O_ODIGEST_A + ui32Idx) = *pui32Src++;
    }

    //
    // Configure the SHA engine to continue the HMAC.
    //
    HWREG(ui32Base + SHAMD5_O_MODE) |= (SHAMD5_MODE_HMAC_OUTER_HASH |
                                        SHAMD5_MODE_CLOSE_HASH);

    //
    // Write the digest count to 64 to account for the preprocessed key.
    //
    HWREG(ui32Base + SHAMD5_O_DIGEST_COUNT) = 64;
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************