EE445M RTOS
Taken at the University of Texas Spring 2015
timer.c
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1 //*****************************************************************************
2 //
3 // timer.c - Driver for the timer module.
4 //
5 // Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
6 // Software License Agreement
7 //
8 // Redistribution and use in source and binary forms, with or without
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23 //
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34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 //
36 // This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
37 //
38 //*****************************************************************************
39 
40 //*****************************************************************************
41 //
44 //
45 //*****************************************************************************
46 
47 #include <stdbool.h>
48 #include <stdint.h>
49 #include "inc/hw_ints.h"
50 #include "inc/hw_memmap.h"
51 #include "inc/hw_timer.h"
52 #include "inc/hw_types.h"
53 #include "inc/hw_sysctl.h"
54 #include "driverlib/debug.h"
55 #include "driverlib/interrupt.h"
56 #include "driverlib/timer.h"
57 
58 //*****************************************************************************
59 //
60 // A macro used to determine whether the target part supports new
61 // configuration and control options.
62 //
63 //*****************************************************************************
64 #define NEW_TIMER_CONFIGURATION CLASS_IS_TM4C129
65 
66 //*****************************************************************************
67 //
68 // A mapping of timer base address to interrupt number.
69 //
70 //*****************************************************************************
71 static const uint32_t g_ppui32TimerIntMap[][2] =
72 {
85 };
86 static const uint_fast8_t g_ui8TimerIntMapRows =
87  sizeof(g_ppui32TimerIntMap) / sizeof(g_ppui32TimerIntMap[0]);
88 
89 static const uint32_t g_ppui32TimerIntMapSnowflake[][2] =
90 {
99 };
100 static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake =
102  sizeof(g_ppui32TimerIntMapSnowflake[0]);
103 
104 //*****************************************************************************
105 //
115 //
116 //*****************************************************************************
117 #ifdef DEBUG
118 static bool
119 _TimerBaseValid(uint32_t ui32Base)
120 {
121  return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) ||
122  (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) ||
123  (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) ||
124  (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) ||
125  (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) ||
126  (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE));
127 }
128 #endif
129 
130 //*****************************************************************************
131 //
143 //
144 //*****************************************************************************
145 static uint32_t
146 _TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer)
147 {
148  uint32_t ui32Int;
149  uint_fast8_t ui8Idx, ui8Rows;
150  const uint32_t (*ppui32SSIIntMap)[2];
151 
152  //
153  // Default interrupt map.
154  //
155  ppui32SSIIntMap = g_ppui32TimerIntMap;
156  ui8Rows = g_ui8TimerIntMapRows;
157 
158  if(CLASS_IS_TM4C129)
159  {
160  ppui32SSIIntMap = g_ppui32TimerIntMapSnowflake;
162  }
163 
164  //
165  // Loop through the table that maps timer base addresses to interrupt
166  // numbers.
167  //
168  for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
169  {
170  //
171  // See if this base address matches.
172  //
173  if(ppui32SSIIntMap[ui8Idx][0] == ui32Base)
174  {
175  ui32Int = ppui32SSIIntMap[ui8Idx][1];
176 
177  if(ui32Timer == TIMER_B)
178  {
179  ui32Int += 1;
180  }
181 
182  //
183  // Return the corresponding interrupt number.
184  //
185  return(ui32Int);
186  }
187  }
188 
189  //
190  // The base address could not be found, so return an error.
191  //
192  return(0);
193 }
194 
195 //*****************************************************************************
196 //
207 //
208 //*****************************************************************************
209 void
210 TimerEnable(uint32_t ui32Base, uint32_t ui32Timer)
211 {
212  //
213  // Check the arguments.
214  //
215  ASSERT(_TimerBaseValid(ui32Base));
216  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
217  (ui32Timer == TIMER_BOTH));
218 
219  //
220  // Enable the timer(s) module.
221  //
222  HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN |
224 }
225 
226 //*****************************************************************************
227 //
237 //
238 //*****************************************************************************
239 void
240 TimerDisable(uint32_t ui32Base, uint32_t ui32Timer)
241 {
242  //
243  // Check the arguments.
244  //
245  ASSERT(_TimerBaseValid(ui32Base));
246  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
247  (ui32Timer == TIMER_BOTH));
248 
249  //
250  // Disable the timer module.
251  //
252  HWREG(ui32Base + TIMER_O_CTL) &= ~(ui32Timer &
254 }
255 
256 //*****************************************************************************
257 //
344 //
345 //*****************************************************************************
346 void
347 TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
348 {
349  //
350  // Check the arguments.
351  //
352  ASSERT(_TimerBaseValid(ui32Base));
353  ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) ||
354  (ui32Config == TIMER_CFG_ONE_SHOT_UP) ||
355  (ui32Config == TIMER_CFG_PERIODIC) ||
356  (ui32Config == TIMER_CFG_PERIODIC_UP) ||
357  (ui32Config == TIMER_CFG_RTC) ||
358  ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
359  ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
360  ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
361  ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
362  ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
363  ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
364  ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
365  ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
366  ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) &&
367  (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
368  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
369  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
370  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
371  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
372  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) ||
373  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
374  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) ||
375  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM))));
376 
377  //
378  // Disable the timers.
379  //
380  HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
381 
382  //
383  // Set the global timer configuration.
384  //
385  HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24;
386 
387  //
388  // Set the configuration of the A and B timers and set the TxPWMIE bit.
389  // Note that the B timer configuration is ignored by the hardware in 32-bit
390  // modes.
391  //
393  {
394  HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) |
395  (ui32Config & 0xff) |
397  HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) |
398  ((ui32Config >> 8) & 0xff) |
400  }
401  else
402  {
403  HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) |
405  HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) |
407  }
408 }
409 
410 //*****************************************************************************
411 //
424 //
425 //*****************************************************************************
426 void
427 TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)
428 {
429  //
430  // Check the arguments.
431  //
432  ASSERT(_TimerBaseValid(ui32Base));
433  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
434  (ui32Timer == TIMER_BOTH));
435 
436  //
437  // Set the output levels as requested.
438  //
439  ui32Timer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
440  HWREG(ui32Base + TIMER_O_CTL) = (bInvert ?
441  (HWREG(ui32Base + TIMER_O_CTL) |
442  ui32Timer) :
443  (HWREG(ui32Base + TIMER_O_CTL) &
444  ~(ui32Timer)));
445 }
446 
447 //*****************************************************************************
448 //
461 //
462 //*****************************************************************************
463 void
464 TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer,
465  bool bEnable)
466 {
467  //
468  // Check the arguments.
469  //
470  ASSERT(_TimerBaseValid(ui32Base));
471  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
472  (ui32Timer == TIMER_BOTH));
473 
474  //
475  // On newer devices the Timer time out ADC trigger enable must also
476  // be set.
477  //
479  {
480  uint32_t ui32Val;
481 
482  //
483  // Determine which bits to set or clear in GPTMADCEV.
484  //
486  ui32Val &= ui32Timer;
487 
488  //
489  // Write the GPTM ADC Event register to enable or disable the trigger
490  // to the ADC.
491  //
492  HWREG(ui32Base + TIMER_O_ADCEV) = (bEnable ?
493  (HWREG(ui32Base + TIMER_O_ADCEV) |
494  ui32Val) :
495  (HWREG(ui32Base + TIMER_O_ADCEV) &
496  ~(ui32Val)));
497  }
498 
499  //
500  // Set the trigger output as requested.
501  // Set the ADC trigger output as requested.
502  //
503  ui32Timer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
504  HWREG(ui32Base + TIMER_O_CTL) = (bEnable ?
505  (HWREG(ui32Base + TIMER_O_CTL) |
506  ui32Timer) :
507  (HWREG(ui32Base + TIMER_O_CTL) &
508  ~(ui32Timer)));
509 }
510 
511 //*****************************************************************************
512 //
526 //
527 //*****************************************************************************
528 void
529 TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer,
530  uint32_t ui32Event)
531 {
532  //
533  // Check the arguments.
534  //
535  ASSERT(_TimerBaseValid(ui32Base));
536  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
537  (ui32Timer == TIMER_BOTH));
538 
539  //
540  // Set the event type.
541  //
543  HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) &
544  ~ui32Timer) | (ui32Event & ui32Timer));
545 }
546 
547 //*****************************************************************************
548 //
562 //
563 //*****************************************************************************
564 void
565 TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer,
566  bool bStall)
567 {
568  //
569  // Check the arguments.
570  //
571  ASSERT(_TimerBaseValid(ui32Base));
572  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
573  (ui32Timer == TIMER_BOTH));
574 
575  //
576  // Set the stall mode.
577  //
578  ui32Timer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
579  HWREG(ui32Base + TIMER_O_CTL) = (bStall ?
580  (HWREG(ui32Base + TIMER_O_CTL) |
581  ui32Timer) :
582  (HWREG(ui32Base + TIMER_O_CTL) &
583  ~(ui32Timer)));
584 }
585 
586 //*****************************************************************************
587 //
604 //
605 //*****************************************************************************
606 void
607 TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer,
608  bool bWait)
609 {
610  //
611  // Check the arguments.
612  //
613  ASSERT(_TimerBaseValid(ui32Base));
614  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
615  (ui32Timer == TIMER_BOTH));
616 
617  //
618  // Set the wait on trigger mode for timer A.
619  //
620  if((ui32Timer & TIMER_A) != 0)
621  {
622  if(bWait)
623  {
624  HWREG(ui32Base + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT;
625  }
626  else
627  {
628  HWREG(ui32Base + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT);
629  }
630  }
631 
632  //
633  // Set the wait on trigger mode for timer B.
634  //
635  if((ui32Timer & TIMER_B) != 0)
636  {
637  if(bWait)
638  {
639  HWREG(ui32Base + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT;
640  }
641  else
642  {
643  HWREG(ui32Base + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT);
644  }
645  }
646 }
647 
648 //*****************************************************************************
649 //
658 //
659 //*****************************************************************************
660 void
661 TimerRTCEnable(uint32_t ui32Base)
662 {
663  //
664  // Check the arguments.
665  //
666  ASSERT(_TimerBaseValid(ui32Base));
667 
668  //
669  // Enable RTC counting.
670  //
671  HWREG(ui32Base + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
672 }
673 
674 //*****************************************************************************
675 //
683 //
684 //*****************************************************************************
685 void
686 TimerRTCDisable(uint32_t ui32Base)
687 {
688  //
689  // Check the arguments.
690  //
691  ASSERT(_TimerBaseValid(ui32Base));
692 
693  //
694  // Disable RTC counting.
695  //
696  HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
697 }
698 
699 //*****************************************************************************
700 //
716 //
717 //*****************************************************************************
718 void
719 TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source)
720 {
721  //
722  // Check the arguments.
723  //
724  ASSERT(_TimerBaseValid(ui32Base));
725  ASSERT((ui32Source == TIMER_CLOCK_SYSTEM) ||
726  (ui32Source == TIMER_CLOCK_PIOSC));
727 
728  //
729  // Set the timer clock source.
730  //
731  HWREG(ui32Base + TIMER_O_CC) = ui32Source;
732 }
733 
734 //*****************************************************************************
735 //
749 //
750 //*****************************************************************************
751 uint32_t
752 TimerClockSourceGet(uint32_t ui32Base)
753 {
754  //
755  // Check the arguments.
756  //
757  ASSERT(_TimerBaseValid(ui32Base));
758 
759  //
760  // Return the timer clock source.
761  //
762  return(HWREG(ui32Base + TIMER_O_CC));
763 }
764 
765 //*****************************************************************************
766 //
787 //
788 //*****************************************************************************
789 void
790 TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
791 {
792  //
793  // Check the arguments.
794  //
795  ASSERT(_TimerBaseValid(ui32Base));
796  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
797  (ui32Timer == TIMER_BOTH));
798  ASSERT(ui32Value < 256);
799 
800  //
801  // Set the timer A prescaler if requested.
802  //
803  if(ui32Timer & TIMER_A)
804  {
805  HWREG(ui32Base + TIMER_O_TAPR) = ui32Value;
806  }
807 
808  //
809  // Set the timer B prescaler if requested.
810  //
811  if(ui32Timer & TIMER_B)
812  {
813  HWREG(ui32Base + TIMER_O_TBPR) = ui32Value;
814  }
815 }
816 
817 //*****************************************************************************
818 //
836 //
837 //*****************************************************************************
838 uint32_t
839 TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer)
840 {
841  //
842  // Check the arguments.
843  //
844  ASSERT(_TimerBaseValid(ui32Base));
845  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
846  (ui32Timer == TIMER_BOTH));
847 
848  //
849  // Return the appropriate prescale value.
850  //
851  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPR) :
852  HWREG(ui32Base + TIMER_O_TBPR));
853 }
854 
855 //*****************************************************************************
856 //
878 //
879 //*****************************************************************************
880 void
881 TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
882  uint32_t ui32Value)
883 {
884  //
885  // Check the arguments.
886  //
887  ASSERT(_TimerBaseValid(ui32Base));
888  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
889  (ui32Timer == TIMER_BOTH));
890  ASSERT(ui32Value < 256);
891 
892  //
893  // Set the timer A prescale match if requested.
894  //
895  if(ui32Timer & TIMER_A)
896  {
897  HWREG(ui32Base + TIMER_O_TAPMR) = ui32Value;
898  }
899 
900  //
901  // Set the timer B prescale match if requested.
902  //
903  if(ui32Timer & TIMER_B)
904  {
905  HWREG(ui32Base + TIMER_O_TBPMR) = ui32Value;
906  }
907 }
908 
909 //*****************************************************************************
910 //
929 //
930 //*****************************************************************************
931 uint32_t
932 TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
933 {
934  //
935  // Check the arguments.
936  //
937  ASSERT(_TimerBaseValid(ui32Base));
938  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
939  (ui32Timer == TIMER_BOTH));
940 
941  //
942  // Return the appropriate prescale match value.
943  //
944  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPMR) :
945  HWREG(ui32Base + TIMER_O_TBPMR));
946 }
947 
948 //*****************************************************************************
949 //
966 //
967 //*****************************************************************************
968 void
969 TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
970 {
971  //
972  // Check the arguments.
973  //
974  ASSERT(_TimerBaseValid(ui32Base));
975  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
976  (ui32Timer == TIMER_BOTH));
977 
978  //
979  // Set the timer A load value if requested.
980  //
981  if(ui32Timer & TIMER_A)
982  {
983  HWREG(ui32Base + TIMER_O_TAILR) = ui32Value;
984  }
985 
986  //
987  // Set the timer B load value if requested.
988  //
989  if(ui32Timer & TIMER_B)
990  {
991  HWREG(ui32Base + TIMER_O_TBILR) = ui32Value;
992  }
993 }
994 
995 //*****************************************************************************
996 //
1012 //
1013 //*****************************************************************************
1014 uint32_t
1015 TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer)
1016 {
1017  //
1018  // Check the arguments.
1019  //
1020  ASSERT(_TimerBaseValid(ui32Base));
1021  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
1022 
1023  //
1024  // Return the appropriate load value.
1025  //
1026  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAILR) :
1027  HWREG(ui32Base + TIMER_O_TBILR));
1028 }
1029 
1030 //*****************************************************************************
1031 //
1041 //
1042 //*****************************************************************************
1043 void
1044 TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value)
1045 {
1046  //
1047  // Check the arguments.
1048  //
1049  ASSERT(_TimerBaseValid(ui32Base));
1050 
1051  //
1052  // Set the timer load value. The upper 32-bits must be written before the
1053  // lower 32-bits in order to adhere to the hardware interlocks on the
1054  // 64-bit value.
1055  //
1056  HWREG(ui32Base + TIMER_O_TBILR) = ui64Value >> 32;
1057  HWREG(ui32Base + TIMER_O_TAILR) = ui64Value & 0xffffffff;
1058 }
1059 
1060 //*****************************************************************************
1061 //
1070 //
1071 //*****************************************************************************
1072 uint64_t
1073 TimerLoadGet64(uint32_t ui32Base)
1074 {
1075  uint32_t ui32High1, ui32High2, ui32Low;
1076 
1077  //
1078  // Check the arguments.
1079  //
1080  ASSERT(_TimerBaseValid(ui32Base));
1081 
1082  //
1083  // Read the 64-bit load value. A read of the low 32-bits is performed
1084  // between two reads of the upper 32-bits; if the upper 32-bit values match
1085  // then the 64-bit value is consistent. If they do not match, then the
1086  // read is performed again until they do match (it should never execute the
1087  // loop body more than twice).
1088  //
1089  do
1090  {
1091  ui32High1 = HWREG(ui32Base + TIMER_O_TBILR);
1092  ui32Low = HWREG(ui32Base + TIMER_O_TAILR);
1093  ui32High2 = HWREG(ui32Base + TIMER_O_TBILR);
1094  }
1095  while(ui32High1 != ui32High2);
1096 
1097  //
1098  // Return the load value.
1099  //
1100  return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
1101 }
1102 
1103 //*****************************************************************************
1104 //
1119 //
1120 //*****************************************************************************
1121 uint32_t
1122 TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer)
1123 {
1124  //
1125  // Check the arguments.
1126  //
1127  ASSERT(_TimerBaseValid(ui32Base));
1128  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
1129 
1130  //
1131  // Return the appropriate timer value.
1132  //
1133  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAR) :
1134  HWREG(ui32Base + TIMER_O_TBR));
1135 }
1136 
1137 //*****************************************************************************
1138 //
1146 //
1147 //*****************************************************************************
1148 uint64_t
1149 TimerValueGet64(uint32_t ui32Base)
1150 {
1151  uint32_t ui32High1, ui32High2, ui32Low;
1152 
1153  //
1154  // Check the arguments.
1155  //
1156  ASSERT(_TimerBaseValid(ui32Base));
1157 
1158  //
1159  // Read the 64-bit timer value. A read of the low 32-bits is performed
1160  // between two reads of the upper 32-bits; if the upper 32-bit values match
1161  // then the 64-bit value is consistent. If they do not match, then the
1162  // read is performed again until they do match (it should never execute the
1163  // loop body more than twice).
1164  //
1165  do
1166  {
1167  ui32High1 = HWREG(ui32Base + TIMER_O_TBR);
1168  ui32Low = HWREG(ui32Base + TIMER_O_TAR);
1169  ui32High2 = HWREG(ui32Base + TIMER_O_TBR);
1170  }
1171  while(ui32High1 != ui32High2);
1172 
1173  //
1174  // Return the timer value.
1175  //
1176  return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
1177 }
1178 
1179 //*****************************************************************************
1180 //
1200 //
1201 //*****************************************************************************
1202 void
1203 TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
1204  uint32_t ui32Value)
1205 {
1206  //
1207  // Check the arguments.
1208  //
1209  ASSERT(_TimerBaseValid(ui32Base));
1210  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
1211  (ui32Timer == TIMER_BOTH));
1212 
1213  //
1214  // Set the timer A match value if requested.
1215  //
1216  if(ui32Timer & TIMER_A)
1217  {
1218  HWREG(ui32Base + TIMER_O_TAMATCHR) = ui32Value;
1219  }
1220 
1221  //
1222  // Set the timer B match value if requested.
1223  //
1224  if(ui32Timer & TIMER_B)
1225  {
1226  HWREG(ui32Base + TIMER_O_TBMATCHR) = ui32Value;
1227  }
1228 }
1229 
1230 //*****************************************************************************
1231 //
1246 //
1247 //*****************************************************************************
1248 uint32_t
1249 TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
1250 {
1251  //
1252  // Check the arguments.
1253  //
1254  ASSERT(_TimerBaseValid(ui32Base));
1255  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
1256 
1257  //
1258  // Return the appropriate match value.
1259  //
1260  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAMATCHR) :
1261  HWREG(ui32Base + TIMER_O_TBMATCHR));
1262 }
1263 
1264 //*****************************************************************************
1265 //
1276 //
1277 //*****************************************************************************
1278 void
1279 TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value)
1280 {
1281  //
1282  // Check the arguments.
1283  //
1284  ASSERT(_TimerBaseValid(ui32Base));
1285 
1286  //
1287  // Set the timer match value. The upper 32-bits must be written before the
1288  // lower 32-bits in order to adhere to the hardware interlocks on the
1289  // 64-bit value.
1290  //
1291  HWREG(ui32Base + TIMER_O_TBMATCHR) = ui64Value >> 32;
1292  HWREG(ui32Base + TIMER_O_TAMATCHR) = ui64Value & 0xffffffff;
1293 }
1294 
1295 //*****************************************************************************
1296 //
1304 //
1305 //*****************************************************************************
1306 uint64_t
1307 TimerMatchGet64(uint32_t ui32Base)
1308 {
1309  uint32_t ui32High1, ui32High2, ui32Low;
1310 
1311  //
1312  // Check the arguments.
1313  //
1314  ASSERT(_TimerBaseValid(ui32Base));
1315 
1316  //
1317  // Read the 64-bit match value. A read of the low 32-bits is performed
1318  // between two reads of the upper 32-bits; if the upper 32-bit values match
1319  // then the 64-bit value is consistent. If they do not match, then the
1320  // read is performed again until they do match (it should never execute the
1321  // loop body more than twice).
1322  //
1323  do
1324  {
1325  ui32High1 = HWREG(ui32Base + TIMER_O_TBMATCHR);
1326  ui32Low = HWREG(ui32Base + TIMER_O_TAMATCHR);
1327  ui32High2 = HWREG(ui32Base + TIMER_O_TBMATCHR);
1328  }
1329  while(ui32High1 != ui32High2);
1330 
1331  //
1332  // Return the match value.
1333  //
1334  return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
1335 }
1336 
1337 //*****************************************************************************
1338 //
1357 //
1358 //*****************************************************************************
1359 void
1360 TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer,
1361  void (*pfnHandler)(void))
1362 {
1363  uint32_t ui32Int;
1364 
1365  //
1366  // Check the arguments.
1367  //
1368  ASSERT(_TimerBaseValid(ui32Base));
1369  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
1370  (ui32Timer == TIMER_BOTH));
1371 
1372  //
1373  // Get the interrupt number for this timer module.
1374  //
1375  ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
1376 
1377  ASSERT(ui32Int != 0);
1378 
1379  //
1380  // Register the interrupt handler.
1381  //
1382  IntRegister(ui32Int, pfnHandler);
1383 
1384  //
1385  // Enable the interrupt.
1386  //
1387  IntEnable(ui32Int);
1388 }
1389 
1390 //*****************************************************************************
1391 //
1406 //
1407 //*****************************************************************************
1408 void
1409 TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer)
1410 {
1411  uint32_t ui32Int;
1412 
1413  //
1414  // Check the arguments.
1415  //
1416  ASSERT(_TimerBaseValid(ui32Base));
1417  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
1418  (ui32Timer == TIMER_BOTH));
1419 
1420  //
1421  // Get the interrupt number for this timer module.
1422  //
1423  ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
1424 
1425  //
1426  // Disable the interrupt.
1427  //
1428  IntDisable(ui32Int);
1429 
1430  //
1431  // Unregister the interrupt handler.
1432  //
1433  IntUnregister(ui32Int);
1434 }
1435 
1436 //*****************************************************************************
1437 //
1461 //
1462 //*****************************************************************************
1463 void
1464 TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
1465 {
1466  //
1467  // Check the arguments.
1468  //
1469  ASSERT(_TimerBaseValid(ui32Base));
1470 
1471  //
1472  // Enable the specified interrupts.
1473  //
1474  HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags;
1475 }
1476 
1477 //*****************************************************************************
1478 //
1493 //
1494 //*****************************************************************************
1495 void
1496 TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
1497 {
1498  //
1499  // Check the arguments.
1500  //
1501  ASSERT(_TimerBaseValid(ui32Base));
1502 
1503  //
1504  // Disable the specified interrupts.
1505  //
1506  HWREG(ui32Base + TIMER_O_IMR) &= ~(ui32IntFlags);
1507 }
1508 
1509 //*****************************************************************************
1510 //
1523 //
1524 //*****************************************************************************
1525 uint32_t
1526 TimerIntStatus(uint32_t ui32Base, bool bMasked)
1527 {
1528  //
1529  // Check the arguments.
1530  //
1531  ASSERT(_TimerBaseValid(ui32Base));
1532 
1533  //
1534  // Return either the interrupt status or the raw interrupt status as
1535  // requested.
1536  //
1537  return(bMasked ? HWREG(ui32Base + TIMER_O_MIS) :
1538  HWREG(ui32Base + TIMER_O_RIS));
1539 }
1540 
1541 //*****************************************************************************
1542 //
1565 //
1566 //*****************************************************************************
1567 void
1568 TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
1569 {
1570  //
1571  // Check the arguments.
1572  //
1573  ASSERT(_TimerBaseValid(ui32Base));
1574 
1575  //
1576  // Clear the requested interrupt sources.
1577  //
1578  HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags;
1579 }
1580 
1581 //*****************************************************************************
1582 //
1626 //
1627 //*****************************************************************************
1628 void
1629 TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers)
1630 {
1631  //
1632  // Check the arguments.
1633  //
1634  ASSERT(ui32Base == TIMER0_BASE);
1635 
1636  //
1637  // Synchronize the specified timers.
1638  //
1639  HWREG(ui32Base + TIMER_O_SYNC) = ui32Timers;
1640 }
1641 
1642 //*****************************************************************************
1643 //
1675 //
1676 //*****************************************************************************
1677 void
1678 TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent)
1679 {
1680  //
1681  // Check the arguments.
1682  //
1683  ASSERT(_TimerBaseValid(ui32Base));
1684 
1685  //
1686  // Set the ADC triggers.
1687  //
1688  HWREG(ui32Base + TIMER_O_ADCEV) = ui32ADCEvent;
1689 }
1690 
1691 //*****************************************************************************
1692 //
1721 //
1722 //*****************************************************************************
1723 uint32_t
1724 TimerADCEventGet(uint32_t ui32Base)
1725 {
1726  //
1727  // Check the arguments.
1728  //
1729  ASSERT(_TimerBaseValid(ui32Base));
1730 
1731  //
1732  // Return the current ADC triggers.
1733  //
1734  return(HWREG(ui32Base + TIMER_O_ADCEV));
1735 }
1736 
1737 //*****************************************************************************
1738 //
1769 //
1770 //*****************************************************************************
1771 void
1772 TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent)
1773 {
1774  //
1775  // Check the arguments.
1776  //
1777  ASSERT(_TimerBaseValid(ui32Base));
1778 
1779  //
1780  // Set the uDMA triggers.
1781  //
1782  HWREG(ui32Base + TIMER_O_DMAEV) = ui32DMAEvent;
1783 }
1784 
1785 //*****************************************************************************
1786 //
1816 //
1817 //*****************************************************************************
1818 uint32_t
1819 TimerDMAEventGet(uint32_t ui32Base)
1820 {
1821  //
1822  // Check the arguments.
1823  //
1824  ASSERT(_TimerBaseValid(ui32Base));
1825 
1826  //
1827  // Return the current uDMA triggers.
1828  //
1829  return(HWREG(ui32Base + TIMER_O_DMAEV));
1830 }
1831 
1832 //*****************************************************************************
1833 //
1868 //
1869 //*****************************************************************************
1870 void
1871 TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Config)
1872 {
1873  uint32_t ui32Value;
1874 
1875  if((ui32Timer & TIMER_A) == TIMER_A)
1876  {
1877  ui32Value = HWREG(ui32Base + TIMER_O_TAMR) & ~(0x00000500);
1878  ui32Value |= ui32Config;
1879  HWREG(ui32Base + TIMER_O_TAMR) = ui32Value;
1880  }
1881 
1882  if((ui32Timer & TIMER_B) == TIMER_B)
1883  {
1884  ui32Value = HWREG(ui32Base + TIMER_O_TBMR) & ~(0x00000500);
1885  ui32Value |= ui32Config;
1886  HWREG(ui32Base + TIMER_O_TBMR) = ui32Value;
1887  }
1888 }
1889 
1890 //*****************************************************************************
1891 //
1892 // Close the Doxygen group.
1894 //
1895 //*****************************************************************************
#define TIMER_CTL_TBEVENT_M
Definition: hw_timer.h:192
#define WTIMER0_BASE
Definition: hw_memmap.h:87
uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
Definition: timer.c:1249
#define TIMER_CFG_SPLIT_PAIR
Definition: timer.h:66
#define TIMER_O_TAR
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static const uint32_t g_ppui32TimerIntMap[][2]
Definition: timer.c:71
#define TIMER_CFG_PERIODIC
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void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
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#define TIMER_CFG_ONE_SHOT
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#define TIMER_CFG_B_PERIODIC_UP
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#define TIMER0_BASE
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#define INT_TIMER2A_TM4C129
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void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer)
Definition: timer.c:240
#define TIMER2_BASE
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#define TIMER_CFG_RTC
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#define TIMER_O_TBPMR
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#define TIMER_CTL_TBSTALL
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#define TIMER_CTL_TAOTE
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#define TIMER_TBMR_TBWOT
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#define TIMER_O_TBPR
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#define TIMER_CTL_TBEN
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#define TIMER_O_DMAEV
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#define TIMER_O_TBMATCHR
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#define TIMER_CLOCK_PIOSC
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#define WTIMER1_BASE
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#define TIMER_CFG_A_ONE_SHOT_UP
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#define TIMER_CLOCK_SYSTEM
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#define INT_TIMER1A_TM4C129
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#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_ADCEV_TBTOADCEN
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void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value)
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#define TIMER_CTL_RTCEN
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#define TIMER_CFG_B_CAP_COUNT
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#define TIMER_CTL_TBOTE
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#define INT_TIMER0A_TM4C129
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static uint32_t _TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer)
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#define TIMER_CTL_TAPWML
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#define TIMER_CFG_ONE_SHOT_UP
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#define TIMER_O_TAMATCHR
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#define TIMER_B
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static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake
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#define INT_WTIMER0A_TM4C123
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#define TIMER_CFG_B_ONE_SHOT
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#define TIMER_CTL_TBPWML
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#define INT_TIMER7A_TM4C129
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#define TIMER_O_IMR
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#define INT_TIMER5A_TM4C123
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#define TIMER_CFG_B_CAP_TIME_UP
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static const uint32_t g_ppui32TimerIntMapSnowflake[][2]
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#define TIMER_O_CTL
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#define TIMER_CFG_A_CAP_COUNT
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#define TIMER_O_CC
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#define INT_WTIMER4A_TM4C123
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static const uint_fast8_t g_ui8TimerIntMapRows
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#define TIMER_CFG_B_CAP_COUNT_UP
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#define TIMER_TAMR_TAPWMIE
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#define TIMER_O_MIS
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#define TIMER_O_RIS
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#define INT_TIMER5A_TM4C129
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#define TIMER_TAMR_TAWOT
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#define TIMER_CFG_PERIODIC_UP
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#define CLASS_IS_TM4C129
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#define TIMER_CFG_B_CAP_TIME
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#define INT_TIMER4A_TM4C123
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#define INT_WTIMER5A_TM4C123
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#define TIMER_O_TBMR
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#define NEW_TIMER_CONFIGURATION
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#define TIMER_O_TAMR
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#define INT_TIMER6A_TM4C129
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#define INT_TIMER2A_TM4C123
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#define TIMER_CFG_A_CAP_TIME
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#define TIMER4_BASE
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