EE445M RTOS
Taken at the University of Texas Spring 2015
Timer_api

Macros

#define NEW_TIMER_CONFIGURATION   CLASS_IS_TM4C129
 

Functions

static uint32_t _TimerIntNumberGet (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerEnable (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerDisable (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerConfigure (uint32_t ui32Base, uint32_t ui32Config)
 
void TimerControlLevel (uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)
 
void TimerControlTrigger (uint32_t ui32Base, uint32_t ui32Timer, bool bEnable)
 
void TimerControlEvent (uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event)
 
void TimerControlStall (uint32_t ui32Base, uint32_t ui32Timer, bool bStall)
 
void TimerControlWaitOnTrigger (uint32_t ui32Base, uint32_t ui32Timer, bool bWait)
 
void TimerRTCEnable (uint32_t ui32Base)
 
void TimerRTCDisable (uint32_t ui32Base)
 
void TimerClockSourceSet (uint32_t ui32Base, uint32_t ui32Source)
 
uint32_t TimerClockSourceGet (uint32_t ui32Base)
 
void TimerPrescaleSet (uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
 
uint32_t TimerPrescaleGet (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerPrescaleMatchSet (uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
 
uint32_t TimerPrescaleMatchGet (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerLoadSet (uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
 
uint32_t TimerLoadGet (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerLoadSet64 (uint32_t ui32Base, uint64_t ui64Value)
 
uint64_t TimerLoadGet64 (uint32_t ui32Base)
 
uint32_t TimerValueGet (uint32_t ui32Base, uint32_t ui32Timer)
 
uint64_t TimerValueGet64 (uint32_t ui32Base)
 
void TimerMatchSet (uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
 
uint32_t TimerMatchGet (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerMatchSet64 (uint32_t ui32Base, uint64_t ui64Value)
 
uint64_t TimerMatchGet64 (uint32_t ui32Base)
 
void TimerIntRegister (uint32_t ui32Base, uint32_t ui32Timer, void(*pfnHandler)(void))
 
void TimerIntUnregister (uint32_t ui32Base, uint32_t ui32Timer)
 
void TimerIntEnable (uint32_t ui32Base, uint32_t ui32IntFlags)
 
void TimerIntDisable (uint32_t ui32Base, uint32_t ui32IntFlags)
 
uint32_t TimerIntStatus (uint32_t ui32Base, bool bMasked)
 
void TimerIntClear (uint32_t ui32Base, uint32_t ui32IntFlags)
 
void TimerSynchronize (uint32_t ui32Base, uint32_t ui32Timers)
 
void TimerADCEventSet (uint32_t ui32Base, uint32_t ui32ADCEvent)
 
uint32_t TimerADCEventGet (uint32_t ui32Base)
 
void TimerDMAEventSet (uint32_t ui32Base, uint32_t ui32DMAEvent)
 
uint32_t TimerDMAEventGet (uint32_t ui32Base)
 
void TimerUpdateMode (uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Config)
 

Variables

static const uint32_t g_ppui32TimerIntMap [][2]
 
static const uint_fast8_t g_ui8TimerIntMapRows
 
static const uint32_t g_ppui32TimerIntMapSnowflake [][2]
 
static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake
 

Detailed Description

Macro Definition Documentation

#define NEW_TIMER_CONFIGURATION   CLASS_IS_TM4C129

Definition at line 64 of file timer.c.

Referenced by TimerConfigure(), and TimerControlTrigger().

Function Documentation

static uint32_t _TimerIntNumberGet ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)
static

Returns a timer modules interrupt number.

Parameters
ui32Baseis the base address of the selected timer.
ui32Timerspecifies the timer(s) to enable; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.

This function returns the interrupt number for a given timer module specified by the ui32Base and ui32Timer parameter.

Returns
Returns a timer module's interrupt number or 0 if the interrupt does not exist.

Definition at line 146 of file timer.c.

References CLASS_IS_TM4C129, g_ppui32TimerIntMap, g_ppui32TimerIntMapSnowflake, g_ui8TimerIntMapRows, g_ui8TimerIntMapRowsSnowflake, and TIMER_B.

Referenced by TimerIntRegister(), and TimerIntUnregister().

147 {
148  uint32_t ui32Int;
149  uint_fast8_t ui8Idx, ui8Rows;
150  const uint32_t (*ppui32SSIIntMap)[2];
151 
152  //
153  // Default interrupt map.
154  //
155  ppui32SSIIntMap = g_ppui32TimerIntMap;
156  ui8Rows = g_ui8TimerIntMapRows;
157 
158  if(CLASS_IS_TM4C129)
159  {
160  ppui32SSIIntMap = g_ppui32TimerIntMapSnowflake;
162  }
163 
164  //
165  // Loop through the table that maps timer base addresses to interrupt
166  // numbers.
167  //
168  for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
169  {
170  //
171  // See if this base address matches.
172  //
173  if(ppui32SSIIntMap[ui8Idx][0] == ui32Base)
174  {
175  ui32Int = ppui32SSIIntMap[ui8Idx][1];
176 
177  if(ui32Timer == TIMER_B)
178  {
179  ui32Int += 1;
180  }
181 
182  //
183  // Return the corresponding interrupt number.
184  //
185  return(ui32Int);
186  }
187  }
188 
189  //
190  // The base address could not be found, so return an error.
191  //
192  return(0);
193 }
static const uint32_t g_ppui32TimerIntMap[][2]
Definition: timer.c:71
#define TIMER_B
Definition: timer.h:153
static const uint_fast8_t g_ui8TimerIntMapRowsSnowflake
Definition: timer.c:100
static const uint32_t g_ppui32TimerIntMapSnowflake[][2]
Definition: timer.c:89
static const uint_fast8_t g_ui8TimerIntMapRows
Definition: timer.c:86
#define CLASS_IS_TM4C129
Definition: hw_types.h:99

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uint32_t TimerADCEventGet ( uint32_t  ui32Base)

Returns the events that can cause an ADC trigger event.

Parameters
ui32Baseis the base address of the timer module.

This function returns the timer events that can cause an ADC trigger event. The ADC trigger events are the logical OR of any of the following values:

  • TIMER_ADC_MODEMATCH_B - The mode match ADC trigger for timer B is enabled.
  • TIMER_ADC_CAPEVENT_B - The capture event ADC trigger for timer B is enabled.
  • TIMER_ADC_CAPMATCH_B - The capture match ADC trigger for timer B is enabled.
  • TIMER_ADC_TIMEOUT_B - The timeout ADC trigger for timer B is enabled.
  • TIMER_ADC_MODEMATCH_A - The mode match ADC trigger for timer A is enabled.
  • TIMER_ADC_RTC_A - The RTC ADC trigger for timer A is enabled.
  • TIMER_ADC_CAPEVENT_A - The capture event ADC trigger for timer A is enabled.
  • TIMER_ADC_CAPMATCH_A - The capture match ADC trigger for timer A is enabled.
  • TIMER_ADC_TIMEOUT_A - The timeout ADC trigger for timer A is enabled.
Note
The ability to specify ADC event triggers varies with the Tiva part in use. Please consult the data sheet for the part you are using to determine whether this support is available.
Returns
The timer events that trigger the ADC.

Definition at line 1724 of file timer.c.

References ASSERT, HWREG, and TIMER_O_ADCEV.

1725 {
1726  //
1727  // Check the arguments.
1728  //
1729  ASSERT(_TimerBaseValid(ui32Base));
1730 
1731  //
1732  // Return the current ADC triggers.
1733  //
1734  return(HWREG(ui32Base + TIMER_O_ADCEV));
1735 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_ADCEV
Definition: hw_timer.h:75
void TimerADCEventSet ( uint32_t  ui32Base,
uint32_t  ui32ADCEvent 
)

Enables the events that can cause an ADC trigger event.

Parameters
ui32Baseis the base address of the timer module.
ui32ADCEventis a bit mask of the events that can cause an ADC trigger event.

This function enables the timer events that can cause an ADC trigger event. The ADC trigger events are specified in the ui32ADCEvent parameter by passing in the logical OR of any of the following values:

  • TIMER_ADC_MODEMATCH_B - Enables the mode match ADC trigger for timer B.
  • TIMER_ADC_CAPEVENT_B - Enables the capture event ADC trigger for timer B.
  • TIMER_ADC_CAPMATCH_B - Enables the capture match ADC trigger for timer B.
  • TIMER_ADC_TIMEOUT_B - Enables the timeout ADC trigger for timer B.
  • TIMER_ADC_MODEMATCH_A - Enables the mode match ADC trigger for timer A.
  • TIMER_ADC_RTC_A - Enables the RTC ADC trigger for timer A.
  • TIMER_ADC_CAPEVENT_A - Enables the capture event ADC trigger for timer A.
  • TIMER_ADC_CAPMATCH_A - Enables the capture match ADC trigger for timer A.
  • TIMER_ADC_TIMEOUT_A - Enables the timeout ADC trigger for timer A.
Note
The ability to specify ADC event triggers varies with the Tiva part in use. Please consult the data sheet for the part you are using to determine whether this support is available.
Returns
None.

Definition at line 1678 of file timer.c.

References ASSERT, HWREG, and TIMER_O_ADCEV.

1679 {
1680  //
1681  // Check the arguments.
1682  //
1683  ASSERT(_TimerBaseValid(ui32Base));
1684 
1685  //
1686  // Set the ADC triggers.
1687  //
1688  HWREG(ui32Base + TIMER_O_ADCEV) = ui32ADCEvent;
1689 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_ADCEV
Definition: hw_timer.h:75
uint32_t TimerClockSourceGet ( uint32_t  ui32Base)

Returns the clock source for the specified timer module.

Parameters
ui32Baseis the base address of the timer module.

This function returns the clock source for the specified timer module. The possible clock sources are the system clock (TIMER_CLOCK_SYSTEM) or the precision internal oscillator (TIMER_CLOCK_PIOSC).

Note
The ability to specify the timer clock source varies with the Tiva part in use. Please consult the data sheet for the part you are using to determine whether this support is available.
Returns
Returns either TIMER_CLOCK_SYSTEM or TIMER_CLOCK_PIOSC.

Definition at line 752 of file timer.c.

References ASSERT, HWREG, and TIMER_O_CC.

753 {
754  //
755  // Check the arguments.
756  //
757  ASSERT(_TimerBaseValid(ui32Base));
758 
759  //
760  // Return the timer clock source.
761  //
762  return(HWREG(ui32Base + TIMER_O_CC));
763 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_CC
Definition: hw_timer.h:77
void TimerClockSourceSet ( uint32_t  ui32Base,
uint32_t  ui32Source 
)

Sets the clock source for the specified timer module.

Parameters
ui32Baseis the base address of the timer module.
ui32Sourceis the clock source for the timer module.

This function sets the clock source for both timer A and timer B for the given timer module. The possible clock sources are the system clock (TIMER_CLOCK_SYSTEM) or the precision internal oscillator (TIMER_CLOCK_PIOSC).

Note
The ability to specify the timer clock source varies with the Tiva part in use. Please consult the data sheet for the part you are using to determine whether this support is available.
Returns
None.

Definition at line 719 of file timer.c.

References ASSERT, HWREG, TIMER_CLOCK_PIOSC, TIMER_CLOCK_SYSTEM, and TIMER_O_CC.

720 {
721  //
722  // Check the arguments.
723  //
724  ASSERT(_TimerBaseValid(ui32Base));
725  ASSERT((ui32Source == TIMER_CLOCK_SYSTEM) ||
726  (ui32Source == TIMER_CLOCK_PIOSC));
727 
728  //
729  // Set the timer clock source.
730  //
731  HWREG(ui32Base + TIMER_O_CC) = ui32Source;
732 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_CLOCK_PIOSC
Definition: timer.h:193
#define TIMER_CLOCK_SYSTEM
Definition: timer.h:192
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_CC
Definition: hw_timer.h:77
void TimerConfigure ( uint32_t  ui32Base,
uint32_t  ui32Config 
)

Configures the timer(s).

Parameters
ui32Baseis the base address of the timer module.
ui32Configis the configuration for the timer.

This function configures the operating mode of the timer(s). The timer module is disabled before being configured and is left in the disabled state. The timer can be configured to be a single full-width timer by using the TIMER_CFG_* values or a pair of half-width timers using the TIMER_CFG_A_* and TIMER_CFG_B_* values passed in the ui32Config parameter.

The configuration is specified in ui32Config as one of the following values:

  • TIMER_CFG_ONE_SHOT - Full-width one-shot timer
  • TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up instead of down (not available on all parts)
  • TIMER_CFG_PERIODIC - Full-width periodic timer
  • TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up instead of down (not available on all parts)
  • TIMER_CFG_RTC - Full-width real time clock timer
  • TIMER_CFG_SPLIT_PAIR - Two half-width timers

When configured for a pair of half-width timers, each timer is separately configured. The first timer is configured by setting ui32Config to the result of a logical OR operation between one of the following values and ui32Config:

  • TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer
  • TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up instead of down (not available on all parts)
  • TIMER_CFG_A_PERIODIC - Half-width periodic timer
  • TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up instead of down (not available on all parts)
  • TIMER_CFG_A_CAP_COUNT - Half-width edge count capture
  • TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts up instead of down (not available on all parts)
  • TIMER_CFG_A_CAP_TIME - Half-width edge time capture
  • TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up instead of down (not available on all parts)
  • TIMER_CFG_A_PWM - Half-width PWM output

Some Tiva devices also allow configuring an action when the timers reach their timeout. Please consult the data sheet for the part you are using to determine whether configuring actions on timers is available.

One of the following can be combined with the TIMER_CFG_* values to enable an action on timer A:

  • TIMER_CFG_A_ACT_TOINTD - masks the timeout interrupt of timer A.
  • TIMER_CFG_A_ACT_NONE - no additional action on timeout of timer A.
  • TIMER_CFG_A_ACT_TOGGLE - toggle CCP on timeout of timer A.
  • TIMER_CFG_A_ACT_SETTO - set CCP on timeout of timer A.
  • TIMER_CFG_A_ACT_CLRTO - clear CCP on timeout of timer A.
  • TIMER_CFG_A_ACT_SETTOGTO - set CCP immediately and then toggle it on timeout of timer A.
  • TIMER_CFG_A_ACT_CLRTOGTO - clear CCP immediately and then toggle it on timeout of timer A.
  • TIMER_CFG_A_ACT_SETCLRTO - set CCP immediately and then clear it on timeout of timer A.
  • TIMER_CFG_A_ACT_CLRSETTO - clear CCP immediately and then set it on timeout of timer A.

One of the following can be combined with the TIMER_CFG_* values to enable an action on timer B:

  • TIMER_CFG_B_ACT_TOINTD - masks the timeout interrupt of timer B.
  • TIMER_CFG_B_ACT_NONE - no additional action on timeout of timer B.
  • TIMER_CFG_B_ACT_TOGGLE - toggle CCP on timeout of timer B.
  • TIMER_CFG_B_ACT_SETTO - set CCP on timeout of timer B.
  • TIMER_CFG_B_ACT_CLRTO - clear CCP on timeout of timer B.
  • TIMER_CFG_B_ACT_SETTOGTO - set CCP immediately and then toggle it on timeout of timer B.
  • TIMER_CFG_B_ACT_CLRTOGTO - clear CCP immediately and then toggle it on timeout of timer B.
  • TIMER_CFG_B_ACT_SETCLRTO - set CCP immediately and then clear it on timeout of timer B.
  • TIMER_CFG_B_ACT_CLRSETTO - clear CCP immediately and then set it on timeout of timer B.

Similarly, the second timer is configured by setting ui32Config to the result of a logical OR operation between one of the corresponding TIMER_CFG_B_* values and ui32Config.

Returns
None.

Definition at line 347 of file timer.c.

References ASSERT, HWREG, NEW_TIMER_CONFIGURATION, TIMER_CFG_A_CAP_COUNT, TIMER_CFG_A_CAP_TIME, TIMER_CFG_A_ONE_SHOT, TIMER_CFG_A_ONE_SHOT_UP, TIMER_CFG_A_PERIODIC, TIMER_CFG_A_PERIODIC_UP, TIMER_CFG_A_PWM, TIMER_CFG_B_CAP_COUNT, TIMER_CFG_B_CAP_COUNT_UP, TIMER_CFG_B_CAP_TIME, TIMER_CFG_B_CAP_TIME_UP, TIMER_CFG_B_ONE_SHOT, TIMER_CFG_B_ONE_SHOT_UP, TIMER_CFG_B_PERIODIC, TIMER_CFG_B_PERIODIC_UP, TIMER_CFG_B_PWM, TIMER_CFG_ONE_SHOT, TIMER_CFG_ONE_SHOT_UP, TIMER_CFG_PERIODIC, TIMER_CFG_PERIODIC_UP, TIMER_CFG_RTC, TIMER_CFG_SPLIT_PAIR, TIMER_CTL_TAEN, TIMER_CTL_TBEN, TIMER_O_CFG, TIMER_O_CTL, TIMER_O_TAMR, TIMER_O_TBMR, TIMER_TAMR_TAPWMIE, and TIMER_TBMR_TBPWMIE.

Referenced by main(), and timer_add_interrupt().

348 {
349  //
350  // Check the arguments.
351  //
352  ASSERT(_TimerBaseValid(ui32Base));
353  ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) ||
354  (ui32Config == TIMER_CFG_ONE_SHOT_UP) ||
355  (ui32Config == TIMER_CFG_PERIODIC) ||
356  (ui32Config == TIMER_CFG_PERIODIC_UP) ||
357  (ui32Config == TIMER_CFG_RTC) ||
358  ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
359  ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
360  ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
361  ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
362  ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
363  ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
364  ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
365  ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
366  ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) &&
367  (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
368  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
369  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
370  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
371  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
372  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) ||
373  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
374  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) ||
375  ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM))));
376 
377  //
378  // Disable the timers.
379  //
380  HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
381 
382  //
383  // Set the global timer configuration.
384  //
385  HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24;
386 
387  //
388  // Set the configuration of the A and B timers and set the TxPWMIE bit.
389  // Note that the B timer configuration is ignored by the hardware in 32-bit
390  // modes.
391  //
393  {
394  HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) |
395  (ui32Config & 0xff) |
397  HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) |
398  ((ui32Config >> 8) & 0xff) |
400  }
401  else
402  {
403  HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) |
405  HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) |
407  }
408 }
#define TIMER_CFG_SPLIT_PAIR
Definition: timer.h:66
#define TIMER_CFG_PERIODIC
Definition: timer.h:62
#define TIMER_CFG_ONE_SHOT
Definition: timer.h:59
#define TIMER_CFG_B_PERIODIC_UP
Definition: timer.h:79
#define TIMER_CFG_RTC
Definition: timer.h:65
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_CFG_A_PWM
Definition: timer.h:75
#define TIMER_CTL_TBEN
Definition: hw_timer.h:197
#define TIMER_CFG_A_ONE_SHOT_UP
Definition: timer.h:68
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_CFG_B_CAP_COUNT
Definition: timer.h:80
#define TIMER_CFG_ONE_SHOT_UP
Definition: timer.h:60
#define TIMER_CFG_A_PERIODIC
Definition: timer.h:69
#define TIMER_CTL_TAEN
Definition: hw_timer.h:207
#define TIMER_CFG_B_ONE_SHOT
Definition: timer.h:76
#define TIMER_CFG_A_PERIODIC_UP
Definition: timer.h:70
#define TIMER_CFG_B_CAP_TIME_UP
Definition: timer.h:83
#define TIMER_O_CTL
Definition: hw_timer.h:51
#define TIMER_CFG_A_ONE_SHOT
Definition: timer.h:67
#define TIMER_CFG_B_ONE_SHOT_UP
Definition: timer.h:77
#define TIMER_CFG_B_PWM
Definition: timer.h:84
#define TIMER_TBMR_TBPWMIE
Definition: hw_timer.h:168
#define TIMER_CFG_A_CAP_COUNT
Definition: timer.h:71
#define TIMER_O_CFG
Definition: hw_timer.h:48
#define TIMER_CFG_B_CAP_COUNT_UP
Definition: timer.h:81
#define TIMER_TAMR_TAPWMIE
Definition: hw_timer.h:124
#define TIMER_CFG_B_PERIODIC
Definition: timer.h:78
#define TIMER_CFG_PERIODIC_UP
Definition: timer.h:63
#define TIMER_CFG_B_CAP_TIME
Definition: timer.h:82
#define TIMER_O_TBMR
Definition: hw_timer.h:50
#define NEW_TIMER_CONFIGURATION
Definition: timer.c:64
#define TIMER_O_TAMR
Definition: hw_timer.h:49
#define TIMER_CFG_A_CAP_TIME
Definition: timer.h:73

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void TimerControlEvent ( uint32_t  ui32Base,
uint32_t  ui32Timer,
uint32_t  ui32Event 
)

Controls the event type.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to be adjusted; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
ui32Eventspecifies the type of event; must be one of TIMER_EVENT_POS_EDGE, TIMER_EVENT_NEG_EDGE, or TIMER_EVENT_BOTH_EDGES.

This function configures the signal edge(s) that triggers the timer when in capture mode.

Returns
None.

Definition at line 529 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_CTL_TAEVENT_M, TIMER_CTL_TBEVENT_M, and TIMER_O_CTL.

531 {
532  //
533  // Check the arguments.
534  //
535  ASSERT(_TimerBaseValid(ui32Base));
536  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
537  (ui32Timer == TIMER_BOTH));
538 
539  //
540  // Set the event type.
541  //
543  HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) &
544  ~ui32Timer) | (ui32Event & ui32Timer));
545 }
#define TIMER_CTL_TBEVENT_M
Definition: hw_timer.h:192
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_O_CTL
Definition: hw_timer.h:51
#define TIMER_CTL_TAEVENT_M
Definition: hw_timer.h:202
void TimerControlLevel ( uint32_t  ui32Base,
uint32_t  ui32Timer,
bool  bInvert 
)

Controls the output level.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to adjust; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
bInvertspecifies the output level.

This function configures the PWM output level for the specified timer. If the bInvert parameter is true, then the timer's output is made active low; otherwise, it is made active high.

Returns
None.

Definition at line 427 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_CTL_TAPWML, TIMER_CTL_TBPWML, and TIMER_O_CTL.

428 {
429  //
430  // Check the arguments.
431  //
432  ASSERT(_TimerBaseValid(ui32Base));
433  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
434  (ui32Timer == TIMER_BOTH));
435 
436  //
437  // Set the output levels as requested.
438  //
439  ui32Timer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
440  HWREG(ui32Base + TIMER_O_CTL) = (bInvert ?
441  (HWREG(ui32Base + TIMER_O_CTL) |
442  ui32Timer) :
443  (HWREG(ui32Base + TIMER_O_CTL) &
444  ~(ui32Timer)));
445 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_CTL_TAPWML
Definition: hw_timer.h:198
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_CTL_TBPWML
Definition: hw_timer.h:189
#define TIMER_O_CTL
Definition: hw_timer.h:51
void TimerControlStall ( uint32_t  ui32Base,
uint32_t  ui32Timer,
bool  bStall 
)

Controls the stall handling.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to be adjusted; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
bStallspecifies the response to a stall signal.

This function controls the stall response for the specified timer. If the bStall parameter is true, then the timer stops counting if the processor enters debug mode; otherwise the timer keeps running while in debug mode.

Returns
None.

Definition at line 565 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_CTL_TASTALL, TIMER_CTL_TBSTALL, and TIMER_O_CTL.

567 {
568  //
569  // Check the arguments.
570  //
571  ASSERT(_TimerBaseValid(ui32Base));
572  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
573  (ui32Timer == TIMER_BOTH));
574 
575  //
576  // Set the stall mode.
577  //
578  ui32Timer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
579  HWREG(ui32Base + TIMER_O_CTL) = (bStall ?
580  (HWREG(ui32Base + TIMER_O_CTL) |
581  ui32Timer) :
582  (HWREG(ui32Base + TIMER_O_CTL) &
583  ~(ui32Timer)));
584 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_CTL_TBSTALL
Definition: hw_timer.h:196
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_O_CTL
Definition: hw_timer.h:51
#define TIMER_CTL_TASTALL
Definition: hw_timer.h:206
void TimerControlTrigger ( uint32_t  ui32Base,
uint32_t  ui32Timer,
bool  bEnable 
)

Enables or disables the ADC trigger output.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer to adjust; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
bEnablespecifies the desired ADC trigger state.

This function controls the ADC trigger output for the specified timer. If the bEnable parameter is true, then the timer's ADC output trigger is enabled; otherwise it is disabled.

Returns
None.

Definition at line 464 of file timer.c.

References ASSERT, HWREG, NEW_TIMER_CONFIGURATION, TIMER_A, TIMER_ADCEV_TATOADCEN, TIMER_ADCEV_TBTOADCEN, TIMER_B, TIMER_BOTH, TIMER_CTL_TAOTE, TIMER_CTL_TBOTE, TIMER_O_ADCEV, and TIMER_O_CTL.

Referenced by adc_interrupt_init().

466 {
467  //
468  // Check the arguments.
469  //
470  ASSERT(_TimerBaseValid(ui32Base));
471  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
472  (ui32Timer == TIMER_BOTH));
473 
474  //
475  // On newer devices the Timer time out ADC trigger enable must also
476  // be set.
477  //
479  {
480  uint32_t ui32Val;
481 
482  //
483  // Determine which bits to set or clear in GPTMADCEV.
484  //
486  ui32Val &= ui32Timer;
487 
488  //
489  // Write the GPTM ADC Event register to enable or disable the trigger
490  // to the ADC.
491  //
492  HWREG(ui32Base + TIMER_O_ADCEV) = (bEnable ?
493  (HWREG(ui32Base + TIMER_O_ADCEV) |
494  ui32Val) :
495  (HWREG(ui32Base + TIMER_O_ADCEV) &
496  ~(ui32Val)));
497  }
498 
499  //
500  // Set the trigger output as requested.
501  // Set the ADC trigger output as requested.
502  //
503  ui32Timer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
504  HWREG(ui32Base + TIMER_O_CTL) = (bEnable ?
505  (HWREG(ui32Base + TIMER_O_CTL) |
506  ui32Timer) :
507  (HWREG(ui32Base + TIMER_O_CTL) &
508  ~(ui32Timer)));
509 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_CTL_TAOTE
Definition: hw_timer.h:199
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_ADCEV_TBTOADCEN
Definition: hw_timer.h:664
#define TIMER_CTL_TBOTE
Definition: hw_timer.h:190
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_ADCEV_TATOADCEN
Definition: hw_timer.h:674
#define TIMER_O_CTL
Definition: hw_timer.h:51
#define TIMER_O_ADCEV
Definition: hw_timer.h:75
#define NEW_TIMER_CONFIGURATION
Definition: timer.c:64

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void TimerControlWaitOnTrigger ( uint32_t  ui32Base,
uint32_t  ui32Timer,
bool  bWait 
)

Controls the wait on trigger handling.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to be adjusted; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
bWaitspecifies if the timer should wait for a trigger input.

This function controls whether or not a timer waits for a trigger input to start counting. When enabled, the previous timer in the trigger chain must count to its timeout in order for this timer to start counting. Refer to the part's data sheet for a description of the trigger chain.

Note
This functionality is not available on all parts. This function should not be used for Timer 0A or Wide Timer 0A.
Returns
None.

Definition at line 607 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_O_TAMR, TIMER_O_TBMR, TIMER_TAMR_TAWOT, and TIMER_TBMR_TBWOT.

609 {
610  //
611  // Check the arguments.
612  //
613  ASSERT(_TimerBaseValid(ui32Base));
614  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
615  (ui32Timer == TIMER_BOTH));
616 
617  //
618  // Set the wait on trigger mode for timer A.
619  //
620  if((ui32Timer & TIMER_A) != 0)
621  {
622  if(bWait)
623  {
624  HWREG(ui32Base + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT;
625  }
626  else
627  {
628  HWREG(ui32Base + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT);
629  }
630  }
631 
632  //
633  // Set the wait on trigger mode for timer B.
634  //
635  if((ui32Timer & TIMER_B) != 0)
636  {
637  if(bWait)
638  {
639  HWREG(ui32Base + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT;
640  }
641  else
642  {
643  HWREG(ui32Base + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT);
644  }
645  }
646 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_TBMR_TBWOT
Definition: hw_timer.h:172
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_TAMR_TAWOT
Definition: hw_timer.h:128
#define TIMER_O_TBMR
Definition: hw_timer.h:50
#define TIMER_O_TAMR
Definition: hw_timer.h:49
void TimerDisable ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Disables the timer(s).

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to disable; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.

This function disables operation of the timer module.

Returns
None.

Definition at line 240 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_CTL_TAEN, TIMER_CTL_TBEN, and TIMER_O_CTL.

241 {
242  //
243  // Check the arguments.
244  //
245  ASSERT(_TimerBaseValid(ui32Base));
246  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
247  (ui32Timer == TIMER_BOTH));
248 
249  //
250  // Disable the timer module.
251  //
252  HWREG(ui32Base + TIMER_O_CTL) &= ~(ui32Timer &
254 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_CTL_TBEN
Definition: hw_timer.h:197
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_CTL_TAEN
Definition: hw_timer.h:207
#define TIMER_O_CTL
Definition: hw_timer.h:51
uint32_t TimerDMAEventGet ( uint32_t  ui32Base)

Returns the events that can trigger a uDMA request.

Parameters
ui32Baseis the base address of the timer module.

This function returns the timer events that can trigger the start of a uDMA sequence. The uDMA trigger events are the logical OR of the following values:

  • TIMER_DMA_MODEMATCH_B - Enables the mode match uDMA trigger for timer B.
  • TIMER_DMA_CAPEVENT_B - Enables the capture event uDMA trigger for timer B.
  • TIMER_DMA_CAPMATCH_B - Enables the capture match uDMA trigger for timer B.
  • TIMER_DMA_TIMEOUT_B - Enables the timeout uDMA trigger for timer B.
  • TIMER_DMA_MODEMATCH_A - Enables the mode match uDMA trigger for timer A.
  • TIMER_DMA_RTC_A - Enables the RTC uDMA trigger for timer A.
  • TIMER_DMA_CAPEVENT_A - Enables the capture event uDMA trigger for timer A.
  • TIMER_DMA_CAPMATCH_A - Enables the capture match uDMA trigger for timer A.
  • TIMER_DMA_TIMEOUT_A - Enables the timeout uDMA trigger for timer A.
Note
The ability to specify uDMA event triggers varies with the Tiva part in use. Please consult the data sheet for the part you are using to determine whether this support is available.
Returns
The timer events that trigger the uDMA.

Definition at line 1819 of file timer.c.

References ASSERT, HWREG, and TIMER_O_DMAEV.

1820 {
1821  //
1822  // Check the arguments.
1823  //
1824  ASSERT(_TimerBaseValid(ui32Base));
1825 
1826  //
1827  // Return the current uDMA triggers.
1828  //
1829  return(HWREG(ui32Base + TIMER_O_DMAEV));
1830 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_DMAEV
Definition: hw_timer.h:74
#define ASSERT(expr)
Definition: debug.h:67
void TimerDMAEventSet ( uint32_t  ui32Base,
uint32_t  ui32DMAEvent 
)

Enables the events that can trigger a uDMA request.

Parameters
ui32Baseis the base address of the timer module.
ui32DMAEventis a bit mask of the events that can trigger uDMA.

This function enables the timer events that can trigger the start of a uDMA sequence. The uDMA trigger events are specified in the ui32DMAEvent parameter by passing in the logical OR of the following values:

  • TIMER_DMA_MODEMATCH_B - The mode match uDMA trigger for timer B is enabled.
  • TIMER_DMA_CAPEVENT_B - The capture event uDMA trigger for timer B is enabled.
  • TIMER_DMA_CAPMATCH_B - The capture match uDMA trigger for timer B is enabled.
  • TIMER_DMA_TIMEOUT_B - The timeout uDMA trigger for timer B is enabled.
  • TIMER_DMA_MODEMATCH_A - The mode match uDMA trigger for timer A is enabled.
  • TIMER_DMA_RTC_A - The RTC uDMA trigger for timer A is enabled.
  • TIMER_DMA_CAPEVENT_A - The capture event uDMA trigger for timer A is enabled.
  • TIMER_DMA_CAPMATCH_A - The capture match uDMA trigger for timer A is enabled.
  • TIMER_DMA_TIMEOUT_A - The timeout uDMA trigger for timer A is enabled.
Note
The ability to specify uDMA event triggers varies with the Tiva part in use. Please consult the data sheet for the part you are using to determine whether this support is available.
Returns
None.

Definition at line 1772 of file timer.c.

References ASSERT, HWREG, and TIMER_O_DMAEV.

1773 {
1774  //
1775  // Check the arguments.
1776  //
1777  ASSERT(_TimerBaseValid(ui32Base));
1778 
1779  //
1780  // Set the uDMA triggers.
1781  //
1782  HWREG(ui32Base + TIMER_O_DMAEV) = ui32DMAEvent;
1783 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_DMAEV
Definition: hw_timer.h:74
#define ASSERT(expr)
Definition: debug.h:67
void TimerEnable ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Enables the timer(s).

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to enable; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.

This function enables operation of the timer module. The timer must be configured before it is enabled.

Returns
None.

Definition at line 210 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_CTL_TAEN, TIMER_CTL_TBEN, and TIMER_O_CTL.

Referenced by main(), and timer_add_interrupt().

211 {
212  //
213  // Check the arguments.
214  //
215  ASSERT(_TimerBaseValid(ui32Base));
216  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
217  (ui32Timer == TIMER_BOTH));
218 
219  //
220  // Enable the timer(s) module.
221  //
222  HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN |
224 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_CTL_TBEN
Definition: hw_timer.h:197
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_CTL_TAEN
Definition: hw_timer.h:207
#define TIMER_O_CTL
Definition: hw_timer.h:51

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void TimerIntClear ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)

Clears timer interrupt sources.

Parameters
ui32Baseis the base address of the timer module.
ui32IntFlagsis a bit mask of the interrupt sources to be cleared.

The specified timer interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep the interrupt from being triggered again immediately upon exit.

The ui32IntFlags parameter has the same definition as the ui32IntFlags parameter to TimerIntEnable().

Note
Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).
Returns
None.

Definition at line 1568 of file timer.c.

References ASSERT, HWREG, and TIMER_O_ICR.

Referenced by sA_Handler(), TIMER0A_Handler(), TIMER1A_Handler(), TIMER2A_Handler(), and timer_task().

1569 {
1570  //
1571  // Check the arguments.
1572  //
1573  ASSERT(_TimerBaseValid(ui32Base));
1574 
1575  //
1576  // Clear the requested interrupt sources.
1577  //
1578  HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags;
1579 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_ICR
Definition: hw_timer.h:56

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void TimerIntDisable ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)

Disables individual timer interrupt sources.

Parameters
ui32Baseis the base address of the timer module.
ui32IntFlagsis the bit mask of the interrupt sources to be disabled.

This function disables the indicated timer interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter has the same definition as the ui32IntFlags parameter to TimerIntEnable().

Returns
None.

Definition at line 1496 of file timer.c.

References ASSERT, HWREG, and TIMER_O_IMR.

1497 {
1498  //
1499  // Check the arguments.
1500  //
1501  ASSERT(_TimerBaseValid(ui32Base));
1502 
1503  //
1504  // Disable the specified interrupts.
1505  //
1506  HWREG(ui32Base + TIMER_O_IMR) &= ~(ui32IntFlags);
1507 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_IMR
Definition: hw_timer.h:53
void TimerIntEnable ( uint32_t  ui32Base,
uint32_t  ui32IntFlags 
)

Enables individual timer interrupt sources.

Parameters
ui32Baseis the base address of the timer module.
ui32IntFlagsis the bit mask of the interrupt sources to be enabled.

This function enables the indicated timer interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter must be the logical OR of any combination of the following:

  • TIMER_TIMB_DMA - Timer B uDMA complete
  • TIMER_TIMA_DMA - Timer A uDMA complete
  • TIMER_CAPB_EVENT - Capture B event interrupt
  • TIMER_CAPB_MATCH - Capture B match interrupt
  • TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
  • TIMER_RTC_MATCH - RTC interrupt mask
  • TIMER_CAPA_EVENT - Capture A event interrupt
  • TIMER_CAPA_MATCH - Capture A match interrupt
  • TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
Returns
None.

Definition at line 1464 of file timer.c.

References ASSERT, HWREG, and TIMER_O_IMR.

Referenced by main(), and timer_add_interrupt().

1465 {
1466  //
1467  // Check the arguments.
1468  //
1469  ASSERT(_TimerBaseValid(ui32Base));
1470 
1471  //
1472  // Enable the specified interrupts.
1473  //
1474  HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags;
1475 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_IMR
Definition: hw_timer.h:53

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void TimerIntRegister ( uint32_t  ui32Base,
uint32_t  ui32Timer,
void(*)(void)  pfnHandler 
)

Registers an interrupt handler for the timer interrupt.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s); must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
pfnHandleris a pointer to the function to be called when the timer interrupt occurs.

This function registers the handler to be called when a timer interrupt occurs. In addition, this function enables the global interrupt in the interrupt controller; specific timer interrupts must be enabled via TimerIntEnable(). It is the interrupt handler's responsibility to clear the interrupt source via TimerIntClear().

See also
IntRegister() for important information about registering interrupt handlers.
Returns
None.

Definition at line 1360 of file timer.c.

References _TimerIntNumberGet(), ASSERT, IntEnable(), IntRegister(), TIMER_A, TIMER_B, and TIMER_BOTH.

1362 {
1363  uint32_t ui32Int;
1364 
1365  //
1366  // Check the arguments.
1367  //
1368  ASSERT(_TimerBaseValid(ui32Base));
1369  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
1370  (ui32Timer == TIMER_BOTH));
1371 
1372  //
1373  // Get the interrupt number for this timer module.
1374  //
1375  ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
1376 
1377  ASSERT(ui32Int != 0);
1378 
1379  //
1380  // Register the interrupt handler.
1381  //
1382  IntRegister(ui32Int, pfnHandler);
1383 
1384  //
1385  // Enable the interrupt.
1386  //
1387  IntEnable(ui32Int);
1388 }
#define ASSERT(expr)
Definition: debug.h:67
static uint32_t _TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer)
Definition: timer.c:146
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Definition: interrupt.c:309
void IntEnable(uint32_t ui32Interrupt)
Definition: interrupt.c:610

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uint32_t TimerIntStatus ( uint32_t  ui32Base,
bool  bMasked 
)

Gets the current interrupt status.

Parameters
ui32Baseis the base address of the timer module.
bMaskedis false if the raw interrupt status is required and true if the masked interrupt status is required.

This function returns the interrupt status for the timer module. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns
The current interrupt status, enumerated as a bit field of values described in TimerIntEnable().

Definition at line 1526 of file timer.c.

References ASSERT, HWREG, TIMER_O_MIS, and TIMER_O_RIS.

1527 {
1528  //
1529  // Check the arguments.
1530  //
1531  ASSERT(_TimerBaseValid(ui32Base));
1532 
1533  //
1534  // Return either the interrupt status or the raw interrupt status as
1535  // requested.
1536  //
1537  return(bMasked ? HWREG(ui32Base + TIMER_O_MIS) :
1538  HWREG(ui32Base + TIMER_O_RIS));
1539 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_MIS
Definition: hw_timer.h:55
#define TIMER_O_RIS
Definition: hw_timer.h:54
void TimerIntUnregister ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Unregisters an interrupt handler for the timer interrupt.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s); must be one of TIMER_A, TIMER_B, or TIMER_BOTH.

This function unregisters the handler to be called when a timer interrupt occurs. This function also masks off the interrupt in the interrupt controller so that the interrupt handler is no longer called.

See also
IntRegister() for important information about registering interrupt handlers.
Returns
None.

Definition at line 1409 of file timer.c.

References _TimerIntNumberGet(), ASSERT, IntDisable(), IntUnregister(), TIMER_A, TIMER_B, and TIMER_BOTH.

1410 {
1411  uint32_t ui32Int;
1412 
1413  //
1414  // Check the arguments.
1415  //
1416  ASSERT(_TimerBaseValid(ui32Base));
1417  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
1418  (ui32Timer == TIMER_BOTH));
1419 
1420  //
1421  // Get the interrupt number for this timer module.
1422  //
1423  ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
1424 
1425  //
1426  // Disable the interrupt.
1427  //
1428  IntDisable(ui32Int);
1429 
1430  //
1431  // Unregister the interrupt handler.
1432  //
1433  IntUnregister(ui32Int);
1434 }
#define ASSERT(expr)
Definition: debug.h:67
static uint32_t _TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer)
Definition: timer.c:146
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
void IntUnregister(uint32_t ui32Interrupt)
Definition: interrupt.c:381
void IntDisable(uint32_t ui32Interrupt)
Definition: interrupt.c:684

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uint32_t TimerLoadGet ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Gets the timer load value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer; must be one of TIMER_A or TIMER_B. Only TIMER_A should be used when the timer is configured for full-width operation.

This function gets the currently programmed interval load value for the specified timer.

Note
This function can be used for both full- and half-width modes of 16/32-bit timers and for half-width modes of 32/64-bit timers. Use TimerLoadGet64() for full-width modes of 32/64-bit timers.
Returns
Returns the load value for the timer.

Definition at line 1015 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_O_TAILR, and TIMER_O_TBILR.

1016 {
1017  //
1018  // Check the arguments.
1019  //
1020  ASSERT(_TimerBaseValid(ui32Base));
1021  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
1022 
1023  //
1024  // Return the appropriate load value.
1025  //
1026  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAILR) :
1027  HWREG(ui32Base + TIMER_O_TBILR));
1028 }
#define TIMER_O_TAILR
Definition: hw_timer.h:57
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_O_TBILR
Definition: hw_timer.h:58
uint64_t TimerLoadGet64 ( uint32_t  ui32Base)

Gets the timer load value for a 64-bit timer.

Parameters
ui32Baseis the base address of the timer module.

This function gets the currently programmed interval load value for the specified 64-bit timer.

Returns
Returns the load value for the timer.

Definition at line 1073 of file timer.c.

References ASSERT, HWREG, TIMER_O_TAILR, and TIMER_O_TBILR.

1074 {
1075  uint32_t ui32High1, ui32High2, ui32Low;
1076 
1077  //
1078  // Check the arguments.
1079  //
1080  ASSERT(_TimerBaseValid(ui32Base));
1081 
1082  //
1083  // Read the 64-bit load value. A read of the low 32-bits is performed
1084  // between two reads of the upper 32-bits; if the upper 32-bit values match
1085  // then the 64-bit value is consistent. If they do not match, then the
1086  // read is performed again until they do match (it should never execute the
1087  // loop body more than twice).
1088  //
1089  do
1090  {
1091  ui32High1 = HWREG(ui32Base + TIMER_O_TBILR);
1092  ui32Low = HWREG(ui32Base + TIMER_O_TAILR);
1093  ui32High2 = HWREG(ui32Base + TIMER_O_TBILR);
1094  }
1095  while(ui32High1 != ui32High2);
1096 
1097  //
1098  // Return the load value.
1099  //
1100  return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
1101 }
#define TIMER_O_TAILR
Definition: hw_timer.h:57
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_TBILR
Definition: hw_timer.h:58
void TimerLoadSet ( uint32_t  ui32Base,
uint32_t  ui32Timer,
uint32_t  ui32Value 
)

Sets the timer load value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to adjust; must be one of TIMER_A, TIMER_B, or TIMER_BOTH. Only TIMER_A should be used when the timer is configured for full-width operation.
ui32Valueis the load value.

This function configures the timer load value; if the timer is running then the value is immediately loaded into the timer.

Note
This function can be used for both full- and half-width modes of 16/32-bit timers and for half-width modes of 32/64-bit timers. Use TimerLoadSet64() for full-width modes of 32/64-bit timers.
Returns
None.

Definition at line 969 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_O_TAILR, and TIMER_O_TBILR.

Referenced by main(), and timer_add_interrupt().

970 {
971  //
972  // Check the arguments.
973  //
974  ASSERT(_TimerBaseValid(ui32Base));
975  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
976  (ui32Timer == TIMER_BOTH));
977 
978  //
979  // Set the timer A load value if requested.
980  //
981  if(ui32Timer & TIMER_A)
982  {
983  HWREG(ui32Base + TIMER_O_TAILR) = ui32Value;
984  }
985 
986  //
987  // Set the timer B load value if requested.
988  //
989  if(ui32Timer & TIMER_B)
990  {
991  HWREG(ui32Base + TIMER_O_TBILR) = ui32Value;
992  }
993 }
#define TIMER_O_TAILR
Definition: hw_timer.h:57
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_O_TBILR
Definition: hw_timer.h:58

Here is the caller graph for this function:

void TimerLoadSet64 ( uint32_t  ui32Base,
uint64_t  ui64Value 
)

Sets the timer load value for a 64-bit timer.

Parameters
ui32Baseis the base address of the timer module.
ui64Valueis the load value.

This function configures the timer load value for a 64-bit timer; if the timer is running, then the value is immediately loaded into the timer.

Returns
None.

Definition at line 1044 of file timer.c.

References ASSERT, HWREG, TIMER_O_TAILR, and TIMER_O_TBILR.

1045 {
1046  //
1047  // Check the arguments.
1048  //
1049  ASSERT(_TimerBaseValid(ui32Base));
1050 
1051  //
1052  // Set the timer load value. The upper 32-bits must be written before the
1053  // lower 32-bits in order to adhere to the hardware interlocks on the
1054  // 64-bit value.
1055  //
1056  HWREG(ui32Base + TIMER_O_TBILR) = ui64Value >> 32;
1057  HWREG(ui32Base + TIMER_O_TAILR) = ui64Value & 0xffffffff;
1058 }
#define TIMER_O_TAILR
Definition: hw_timer.h:57
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_TBILR
Definition: hw_timer.h:58
uint32_t TimerMatchGet ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Gets the timer match value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer; must be one of TIMER_A or TIMER_B. Only TIMER_A should be used when the timer is configured for full-width operation.

This function gets the match value for the specified timer.

Note
This function can be used for both full- and half-width modes of 16/32-bit timers and for half-width modes of 32/64-bit timers. Use TimerMatchGet64() for full-width modes of 32/64-bit timers.
Returns
Returns the match value for the timer.

Definition at line 1249 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_O_TAMATCHR, and TIMER_O_TBMATCHR.

1250 {
1251  //
1252  // Check the arguments.
1253  //
1254  ASSERT(_TimerBaseValid(ui32Base));
1255  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
1256 
1257  //
1258  // Return the appropriate match value.
1259  //
1260  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAMATCHR) :
1261  HWREG(ui32Base + TIMER_O_TBMATCHR));
1262 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBMATCHR
Definition: hw_timer.h:60
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_TAMATCHR
Definition: hw_timer.h:59
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
uint64_t TimerMatchGet64 ( uint32_t  ui32Base)

Gets the timer match value for a 64-bit timer.

Parameters
ui32Baseis the base address of the timer module.

This function gets the match value for the specified timer.

Returns
Returns the match value for the timer.

Definition at line 1307 of file timer.c.

References ASSERT, HWREG, TIMER_O_TAMATCHR, and TIMER_O_TBMATCHR.

1308 {
1309  uint32_t ui32High1, ui32High2, ui32Low;
1310 
1311  //
1312  // Check the arguments.
1313  //
1314  ASSERT(_TimerBaseValid(ui32Base));
1315 
1316  //
1317  // Read the 64-bit match value. A read of the low 32-bits is performed
1318  // between two reads of the upper 32-bits; if the upper 32-bit values match
1319  // then the 64-bit value is consistent. If they do not match, then the
1320  // read is performed again until they do match (it should never execute the
1321  // loop body more than twice).
1322  //
1323  do
1324  {
1325  ui32High1 = HWREG(ui32Base + TIMER_O_TBMATCHR);
1326  ui32Low = HWREG(ui32Base + TIMER_O_TAMATCHR);
1327  ui32High2 = HWREG(ui32Base + TIMER_O_TBMATCHR);
1328  }
1329  while(ui32High1 != ui32High2);
1330 
1331  //
1332  // Return the match value.
1333  //
1334  return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
1335 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBMATCHR
Definition: hw_timer.h:60
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_TAMATCHR
Definition: hw_timer.h:59
void TimerMatchSet ( uint32_t  ui32Base,
uint32_t  ui32Timer,
uint32_t  ui32Value 
)

Sets the timer match value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to adjust; must be one of TIMER_A, TIMER_B, or TIMER_BOTH. Only TIMER_A should be used when the timer is configured for full-width operation.
ui32Valueis the match value.

This function configures the match value for a timer. This value is used in capture count mode to determine when to interrupt the processor and in PWM mode to determine the duty cycle of the output signal. On some Tiva devices, match interrupts can also be generated in periodic and one-shot modes.

Note
This function can be used for both full- and half-width modes of 16/32-bit timers and for half-width modes of 32/64-bit timers. Use TimerMatchSet64() for full-width modes of 32/64-bit timers.
Returns
None.

Definition at line 1203 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_O_TAMATCHR, and TIMER_O_TBMATCHR.

1205 {
1206  //
1207  // Check the arguments.
1208  //
1209  ASSERT(_TimerBaseValid(ui32Base));
1210  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
1211  (ui32Timer == TIMER_BOTH));
1212 
1213  //
1214  // Set the timer A match value if requested.
1215  //
1216  if(ui32Timer & TIMER_A)
1217  {
1218  HWREG(ui32Base + TIMER_O_TAMATCHR) = ui32Value;
1219  }
1220 
1221  //
1222  // Set the timer B match value if requested.
1223  //
1224  if(ui32Timer & TIMER_B)
1225  {
1226  HWREG(ui32Base + TIMER_O_TBMATCHR) = ui32Value;
1227  }
1228 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBMATCHR
Definition: hw_timer.h:60
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_TAMATCHR
Definition: hw_timer.h:59
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
void TimerMatchSet64 ( uint32_t  ui32Base,
uint64_t  ui64Value 
)

Sets the timer match value for a 64-bit timer.

Parameters
ui32Baseis the base address of the timer module.
ui64Valueis the match value.

This function configures the match value for a timer. This value is used in capture count mode to determine when to interrupt the processor and in PWM mode to determine the duty cycle of the output signal.

Returns
None.

Definition at line 1279 of file timer.c.

References ASSERT, HWREG, TIMER_O_TAMATCHR, and TIMER_O_TBMATCHR.

1280 {
1281  //
1282  // Check the arguments.
1283  //
1284  ASSERT(_TimerBaseValid(ui32Base));
1285 
1286  //
1287  // Set the timer match value. The upper 32-bits must be written before the
1288  // lower 32-bits in order to adhere to the hardware interlocks on the
1289  // 64-bit value.
1290  //
1291  HWREG(ui32Base + TIMER_O_TBMATCHR) = ui64Value >> 32;
1292  HWREG(ui32Base + TIMER_O_TAMATCHR) = ui64Value & 0xffffffff;
1293 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBMATCHR
Definition: hw_timer.h:60
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_TAMATCHR
Definition: hw_timer.h:59
uint32_t TimerPrescaleGet ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Gets the timer prescale value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer; must be one of TIMER_A or TIMER_B.

This function gets the value of the input clock prescaler. The prescaler is only operational when in half-width mode and is used to extend the range of the half-width timer modes. The prescaler provides the least significant bits when counting down in periodic and one-shot modes; in all other modes, the prescaler provides the most significant bits.

Note
The availability of the prescaler varies with the Tiva part and timer mode in use. Please consult the datasheet for the part you are using to determine whether this support is available.
Returns
The value of the timer prescaler.

Definition at line 839 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_O_TAPR, and TIMER_O_TBPR.

840 {
841  //
842  // Check the arguments.
843  //
844  ASSERT(_TimerBaseValid(ui32Base));
845  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
846  (ui32Timer == TIMER_BOTH));
847 
848  //
849  // Return the appropriate prescale value.
850  //
851  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPR) :
852  HWREG(ui32Base + TIMER_O_TBPR));
853 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBPR
Definition: hw_timer.h:62
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_O_TAPR
Definition: hw_timer.h:61
uint32_t TimerPrescaleMatchGet ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Gets the timer prescale match value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer; must be one of TIMER_A or TIMER_B.

This function gets the value of the input clock prescaler match value. When in a half-width mode that uses the counter match and prescaler, the prescale match effectively extends the range of the match. The prescaler provides the least significant bits when counting down in periodic and one-shot modes; in all other modes, the prescaler provides the most significant bits.

Note
The availability of the prescaler match varies with the Tiva part and timer mode in use. Please consult the datasheet for the part you are using to determine whether this support is available.
Returns
The value of the timer prescale match.

Definition at line 932 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_O_TAPMR, and TIMER_O_TBPMR.

933 {
934  //
935  // Check the arguments.
936  //
937  ASSERT(_TimerBaseValid(ui32Base));
938  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
939  (ui32Timer == TIMER_BOTH));
940 
941  //
942  // Return the appropriate prescale match value.
943  //
944  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPMR) :
945  HWREG(ui32Base + TIMER_O_TBPMR));
946 }
#define TIMER_O_TAPMR
Definition: hw_timer.h:63
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBPMR
Definition: hw_timer.h:64
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
void TimerPrescaleMatchSet ( uint32_t  ui32Base,
uint32_t  ui32Timer,
uint32_t  ui32Value 
)

Sets the timer prescale match value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to adjust; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
ui32Valueis the timer prescale match value which must be between 0 and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) for 32/64-bit timers.

This function configures the value of the input clock prescaler match value. When in a half-width mode that uses the counter match and the prescaler, the prescale match effectively extends the range of the match. The prescaler provides the least significant bits when counting down in periodic and one-shot modes; in all other modes, the prescaler provides the most significant bits.

Note
The availability of the prescaler match varies with the Tiva part and timer mode in use. Please consult the datasheet for the part you are using to determine whether this support is available.
Returns
None.

Definition at line 881 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_O_TAPMR, and TIMER_O_TBPMR.

883 {
884  //
885  // Check the arguments.
886  //
887  ASSERT(_TimerBaseValid(ui32Base));
888  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
889  (ui32Timer == TIMER_BOTH));
890  ASSERT(ui32Value < 256);
891 
892  //
893  // Set the timer A prescale match if requested.
894  //
895  if(ui32Timer & TIMER_A)
896  {
897  HWREG(ui32Base + TIMER_O_TAPMR) = ui32Value;
898  }
899 
900  //
901  // Set the timer B prescale match if requested.
902  //
903  if(ui32Timer & TIMER_B)
904  {
905  HWREG(ui32Base + TIMER_O_TBPMR) = ui32Value;
906  }
907 }
#define TIMER_O_TAPMR
Definition: hw_timer.h:63
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBPMR
Definition: hw_timer.h:64
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
void TimerPrescaleSet ( uint32_t  ui32Base,
uint32_t  ui32Timer,
uint32_t  ui32Value 
)

Sets the timer prescale value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s) to adjust; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
ui32Valueis the timer prescale value which must be between 0 and 255 (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) for 32/64-bit timers.

This function configures the value of the input clock prescaler. The prescaler is only operational when in half-width mode and is used to extend the range of the half-width timer modes. The prescaler provides the least significant bits when counting down in periodic and one-shot modes; in all other modes, the prescaler provides the most significant bits.

Note
The availability of the prescaler varies with the Tiva part and timer mode in use. Please consult the datasheet for the part you are using to determine whether this support is available.
Returns
None.

Definition at line 790 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_BOTH, TIMER_O_TAPR, and TIMER_O_TBPR.

791 {
792  //
793  // Check the arguments.
794  //
795  ASSERT(_TimerBaseValid(ui32Base));
796  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
797  (ui32Timer == TIMER_BOTH));
798  ASSERT(ui32Value < 256);
799 
800  //
801  // Set the timer A prescaler if requested.
802  //
803  if(ui32Timer & TIMER_A)
804  {
805  HWREG(ui32Base + TIMER_O_TAPR) = ui32Value;
806  }
807 
808  //
809  // Set the timer B prescaler if requested.
810  //
811  if(ui32Timer & TIMER_B)
812  {
813  HWREG(ui32Base + TIMER_O_TBPR) = ui32Value;
814  }
815 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_O_TBPR
Definition: hw_timer.h:62
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_BOTH
Definition: timer.h:154
#define TIMER_O_TAPR
Definition: hw_timer.h:61
void TimerRTCDisable ( uint32_t  ui32Base)

Disables RTC counting.

Parameters
ui32Baseis the base address of the timer module.

This function causes the timer to stop counting when in RTC mode.

Returns
None.

Definition at line 686 of file timer.c.

References ASSERT, HWREG, TIMER_CTL_RTCEN, and TIMER_O_CTL.

687 {
688  //
689  // Check the arguments.
690  //
691  ASSERT(_TimerBaseValid(ui32Base));
692 
693  //
694  // Disable RTC counting.
695  //
696  HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
697 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_CTL_RTCEN
Definition: hw_timer.h:201
#define TIMER_O_CTL
Definition: hw_timer.h:51
void TimerRTCEnable ( uint32_t  ui32Base)

Enables RTC counting.

Parameters
ui32Baseis the base address of the timer module.

This function causes the timer to start counting when in RTC mode. If not configured for RTC mode, this function does nothing.

Returns
None.

Definition at line 661 of file timer.c.

References ASSERT, HWREG, TIMER_CTL_RTCEN, and TIMER_O_CTL.

662 {
663  //
664  // Check the arguments.
665  //
666  ASSERT(_TimerBaseValid(ui32Base));
667 
668  //
669  // Enable RTC counting.
670  //
671  HWREG(ui32Base + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
672 }
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_CTL_RTCEN
Definition: hw_timer.h:201
#define TIMER_O_CTL
Definition: hw_timer.h:51
void TimerSynchronize ( uint32_t  ui32Base,
uint32_t  ui32Timers 
)

Synchronizes the counters in a set of timers.

Parameters
ui32Baseis the base address of the timer module. This parameter must be the base address of Timer0 (in other words, TIMER0_BASE).
ui32Timersis the set of timers to synchronize.

This function synchronizes the counters in a specified set of timers. When a timer is running in half-width mode, each half can be included or excluded in the synchronization event. When a timer is running in full-width mode, only the A timer can be synchronized (specifying the B timer has no effect).

The ui32Timers parameter is the logical OR of any of the following defines:

  • TIMER_0A_SYNC
  • TIMER_0B_SYNC
  • TIMER_1A_SYNC
  • TIMER_1B_SYNC
  • TIMER_2A_SYNC
  • TIMER_2B_SYNC
  • TIMER_3A_SYNC
  • TIMER_3B_SYNC
  • TIMER_4A_SYNC
  • TIMER_4B_SYNC
  • TIMER_5A_SYNC
  • TIMER_5B_SYNC
  • WTIMER_0A_SYNC
  • WTIMER_0B_SYNC
  • WTIMER_1A_SYNC
  • WTIMER_1B_SYNC
  • WTIMER_2A_SYNC
  • WTIMER_2B_SYNC
  • WTIMER_3A_SYNC
  • WTIMER_3B_SYNC
  • WTIMER_4A_SYNC
  • WTIMER_4B_SYNC
  • WTIMER_5A_SYNC
  • WTIMER_5B_SYNC
Note
This functionality is not available on all parts.
Returns
None.

Definition at line 1629 of file timer.c.

References ASSERT, HWREG, TIMER0_BASE, and TIMER_O_SYNC.

1630 {
1631  //
1632  // Check the arguments.
1633  //
1634  ASSERT(ui32Base == TIMER0_BASE);
1635 
1636  //
1637  // Synchronize the specified timers.
1638  //
1639  HWREG(ui32Base + TIMER_O_SYNC) = ui32Timers;
1640 }
#define TIMER0_BASE
Definition: hw_memmap.h:81
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_SYNC
Definition: hw_timer.h:52
void TimerUpdateMode ( uint32_t  ui32Base,
uint32_t  ui32Timer,
uint32_t  ui32Config 
)

This function configures the update of timer load and match settings.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer(s); must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
ui32Configis a combination of the updates methods for the timers specified in the ui32Timer parameter.

This function configures how the timer updates the timer load and match values for the timers. The ui32Timer values can be TIMER_A, TIMER_B, or TIMER_BOTH to apply the settings in ui32Config to either timer or both timers. If the timer is not split then the TIMER_A should be used. The ui32Config values affects when the TimerLoadSet() and TimerLoadSet64() values take effect.

Similarly the ui32Config value affects when the TimerMatchSet() and TimerMatchSet64() values take effect.

Note
These settings have no effect if the timer is not in count down mode and are mostly useful when operating in PWM mode to allow for synchronous update of timer match and load values.
Returns
None.

Definition at line 1871 of file timer.c.

References HWREG, TIMER_A, TIMER_B, TIMER_O_TAMR, and TIMER_O_TBMR.

1872 {
1873  uint32_t ui32Value;
1874 
1875  if((ui32Timer & TIMER_A) == TIMER_A)
1876  {
1877  ui32Value = HWREG(ui32Base + TIMER_O_TAMR) & ~(0x00000500);
1878  ui32Value |= ui32Config;
1879  HWREG(ui32Base + TIMER_O_TAMR) = ui32Value;
1880  }
1881 
1882  if((ui32Timer & TIMER_B) == TIMER_B)
1883  {
1884  ui32Value = HWREG(ui32Base + TIMER_O_TBMR) & ~(0x00000500);
1885  ui32Value |= ui32Config;
1886  HWREG(ui32Base + TIMER_O_TBMR) = ui32Value;
1887  }
1888 }
#define HWREG(x)
Definition: hw_types.h:48
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_O_TBMR
Definition: hw_timer.h:50
#define TIMER_O_TAMR
Definition: hw_timer.h:49
uint32_t TimerValueGet ( uint32_t  ui32Base,
uint32_t  ui32Timer 
)

Gets the current timer value.

Parameters
ui32Baseis the base address of the timer module.
ui32Timerspecifies the timer; must be one of TIMER_A or TIMER_B. Only TIMER_A should be used when the timer is configured for full-width operation.

This function reads the current value of the specified timer.

Note
This function can be used for both full- and half-width modes of 16/32-bit timers and for half-width modes of 32/64-bit timers. Use TimerValueGet64() for full-width modes of 32/64-bit timers.
Returns
Returns the current value of the timer.

Definition at line 1122 of file timer.c.

References ASSERT, HWREG, TIMER_A, TIMER_B, TIMER_O_TAR, and TIMER_O_TBR.

1123 {
1124  //
1125  // Check the arguments.
1126  //
1127  ASSERT(_TimerBaseValid(ui32Base));
1128  ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
1129 
1130  //
1131  // Return the appropriate timer value.
1132  //
1133  return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAR) :
1134  HWREG(ui32Base + TIMER_O_TBR));
1135 }
#define TIMER_O_TAR
Definition: hw_timer.h:65
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_B
Definition: timer.h:153
#define TIMER_A
Definition: timer.h:152
#define TIMER_O_TBR
Definition: hw_timer.h:66
uint64_t TimerValueGet64 ( uint32_t  ui32Base)

Gets the current 64-bit timer value.

Parameters
ui32Baseis the base address of the timer module.

This function reads the current value of the specified timer.

Returns
Returns the current value of the timer.

Definition at line 1149 of file timer.c.

References ASSERT, HWREG, TIMER_O_TAR, and TIMER_O_TBR.

1150 {
1151  uint32_t ui32High1, ui32High2, ui32Low;
1152 
1153  //
1154  // Check the arguments.
1155  //
1156  ASSERT(_TimerBaseValid(ui32Base));
1157 
1158  //
1159  // Read the 64-bit timer value. A read of the low 32-bits is performed
1160  // between two reads of the upper 32-bits; if the upper 32-bit values match
1161  // then the 64-bit value is consistent. If they do not match, then the
1162  // read is performed again until they do match (it should never execute the
1163  // loop body more than twice).
1164  //
1165  do
1166  {
1167  ui32High1 = HWREG(ui32Base + TIMER_O_TBR);
1168  ui32Low = HWREG(ui32Base + TIMER_O_TAR);
1169  ui32High2 = HWREG(ui32Base + TIMER_O_TBR);
1170  }
1171  while(ui32High1 != ui32High2);
1172 
1173  //
1174  // Return the timer value.
1175  //
1176  return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
1177 }
#define TIMER_O_TAR
Definition: hw_timer.h:65
#define HWREG(x)
Definition: hw_types.h:48
#define ASSERT(expr)
Definition: debug.h:67
#define TIMER_O_TBR
Definition: hw_timer.h:66

Variable Documentation

const uint32_t g_ppui32TimerIntMap[][2]
static
Initial value:
=
{
}
#define WTIMER0_BASE
Definition: hw_memmap.h:87
#define TIMER0_BASE
Definition: hw_memmap.h:81
#define TIMER2_BASE
Definition: hw_memmap.h:83
#define WTIMER1_BASE
Definition: hw_memmap.h:88
#define INT_WTIMER0A_TM4C123
Definition: hw_ints.h:131
#define INT_WTIMER2A_TM4C123
Definition: hw_ints.h:135
#define INT_TIMER5A_TM4C123
Definition: hw_ints.h:129
#define WTIMER4_BASE
Definition: hw_memmap.h:97
#define TIMER5_BASE
Definition: hw_memmap.h:86
#define WTIMER3_BASE
Definition: hw_memmap.h:96
#define TIMER1_BASE
Definition: hw_memmap.h:82
#define INT_WTIMER1A_TM4C123
Definition: hw_ints.h:133
#define INT_TIMER3A_TM4C123
Definition: hw_ints.h:100
#define INT_TIMER0A_TM4C123
Definition: hw_ints.h:83
#define TIMER3_BASE
Definition: hw_memmap.h:84
#define INT_WTIMER4A_TM4C123
Definition: hw_ints.h:139
#define INT_WTIMER3A_TM4C123
Definition: hw_ints.h:137
#define WTIMER5_BASE
Definition: hw_memmap.h:98
#define INT_TIMER4A_TM4C123
Definition: hw_ints.h:127
#define INT_TIMER1A_TM4C123
Definition: hw_ints.h:85
#define WTIMER2_BASE
Definition: hw_memmap.h:95
#define INT_WTIMER5A_TM4C123
Definition: hw_ints.h:141
#define INT_TIMER2A_TM4C123
Definition: hw_ints.h:87
#define TIMER4_BASE
Definition: hw_memmap.h:85

Definition at line 71 of file timer.c.

Referenced by _TimerIntNumberGet().

const uint32_t g_ppui32TimerIntMapSnowflake[][2]
static
Initial value:
=
{
}
#define TIMER0_BASE
Definition: hw_memmap.h:81
#define INT_TIMER2A_TM4C129
Definition: hw_ints.h:199
#define TIMER2_BASE
Definition: hw_memmap.h:83
#define INT_TIMER1A_TM4C129
Definition: hw_ints.h:197
#define INT_TIMER0A_TM4C129
Definition: hw_ints.h:195
#define INT_TIMER4A_TM4C129
Definition: hw_ints.h:239
#define INT_TIMER3A_TM4C129
Definition: hw_ints.h:211
#define TIMER6_BASE
Definition: hw_memmap.h:130
#define INT_TIMER7A_TM4C129
Definition: hw_ints.h:274
#define TIMER5_BASE
Definition: hw_memmap.h:86
#define TIMER1_BASE
Definition: hw_memmap.h:82
#define TIMER7_BASE
Definition: hw_memmap.h:131
#define TIMER3_BASE
Definition: hw_memmap.h:84
#define INT_TIMER5A_TM4C129
Definition: hw_ints.h:241
#define INT_TIMER6A_TM4C129
Definition: hw_ints.h:272
#define TIMER4_BASE
Definition: hw_memmap.h:85

Definition at line 89 of file timer.c.

Referenced by _TimerIntNumberGet().

const uint_fast8_t g_ui8TimerIntMapRows
static
Initial value:
=
static const uint32_t g_ppui32TimerIntMap[][2]
Definition: timer.c:71

Definition at line 86 of file timer.c.

Referenced by _TimerIntNumberGet().

const uint_fast8_t g_ui8TimerIntMapRowsSnowflake
static
Initial value:
=
static const uint32_t g_ppui32TimerIntMapSnowflake[][2]
Definition: timer.c:89

Definition at line 100 of file timer.c.

Referenced by _TimerIntNumberGet().