EE445M RTOS
Taken at the University of Texas Spring 2015
i2c.c
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1 //*****************************************************************************
2 //
3 // i2c.c - Driver for Inter-IC (I2C) bus block.
4 //
5 // Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
6 // Software License Agreement
7 //
8 // Redistribution and use in source and binary forms, with or without
9 // modification, are permitted provided that the following conditions
10 // are met:
11 //
12 // Redistributions of source code must retain the above copyright
13 // notice, this list of conditions and the following disclaimer.
14 //
15 // Redistributions in binary form must reproduce the above copyright
16 // notice, this list of conditions and the following disclaimer in the
17 // documentation and/or other materials provided with the
18 // distribution.
19 //
20 // Neither the name of Texas Instruments Incorporated nor the names of
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22 // from this software without specific prior written permission.
23 //
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 //
36 // This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
37 //
38 //*****************************************************************************
39 
40 //*****************************************************************************
41 //
44 //
45 //*****************************************************************************
46 
47 #include <stdbool.h>
48 #include <stdint.h>
49 #include "inc/hw_i2c.h"
50 #include "inc/hw_ints.h"
51 #include "inc/hw_memmap.h"
52 #include "inc/hw_sysctl.h"
53 #include "inc/hw_types.h"
54 #include "driverlib/debug.h"
55 #include "driverlib/i2c.h"
56 #include "driverlib/interrupt.h"
57 
58 //*****************************************************************************
59 //
60 // A mapping of I2C base address to interrupt number.
61 //
62 //*****************************************************************************
63 static const uint32_t g_ppui32I2CIntMap[][2] =
64 {
71 };
72 
73 static const int_fast8_t g_i8I2CIntMapRows =
74  sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]);
75 
76 static const uint32_t g_ppui32I2CIntMapSnowflake[][2] =
77 {
88 };
89 static const int_fast8_t g_i8I2CIntMapSnowflakeRows =
90  sizeof(g_ppui32I2CIntMapSnowflake) / sizeof(g_ppui32I2CIntMapSnowflake[0]);
91 
92 //*****************************************************************************
93 //
103 //
104 //*****************************************************************************
105 #ifdef DEBUG
106 static bool
107 _I2CBaseValid(uint32_t ui32Base)
108 {
109  return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) ||
110  (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) ||
111  (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) ||
112  (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) ||
113  (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE));
114 }
115 #endif
116 
117 //*****************************************************************************
118 //
128 //
129 //*****************************************************************************
130 static uint32_t
131 _I2CIntNumberGet(uint32_t ui32Base)
132 {
133  int_fast8_t i8Idx, i8Rows;
134  const uint32_t (*ppui32I2CIntMap)[2];
135 
136  //
137  // Check the arguments.
138  //
139  ASSERT(_I2CBaseValid(ui32Base));
140 
141  ppui32I2CIntMap = g_ppui32I2CIntMap;
142  i8Rows = g_i8I2CIntMapRows;
143 
144  if(CLASS_IS_TM4C129)
145  {
146  ppui32I2CIntMap = g_ppui32I2CIntMapSnowflake;
148  }
149 
150  //
151  // Loop through the table that maps I2C base addresses to interrupt
152  // numbers.
153  //
154  for(i8Idx = 0; i8Idx < i8Rows; i8Idx++)
155  {
156  //
157  // See if this base address matches.
158  //
159  if(ppui32I2CIntMap[i8Idx][0] == ui32Base)
160  {
161  //
162  // Return the corresponding interrupt number.
163  //
164  return(ppui32I2CIntMap[i8Idx][1]);
165  }
166  }
167 
168  //
169  // The base address could not be found, so return an error.
170  //
171  return(0);
172 }
173 
174 //*****************************************************************************
175 //
199 //
200 //*****************************************************************************
201 void
202 I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
203  bool bFast)
204 {
205  uint32_t ui32SCLFreq;
206  uint32_t ui32TPR;
207 
208  //
209  // Check the arguments.
210  //
211  ASSERT(_I2CBaseValid(ui32Base));
212 
213  //
214  // Must enable the device before doing anything else.
215  //
216  I2CMasterEnable(ui32Base);
217 
218  //
219  // Get the desired SCL speed.
220  //
221  if(bFast == true)
222  {
223  ui32SCLFreq = 400000;
224  }
225  else
226  {
227  ui32SCLFreq = 100000;
228  }
229 
230  //
231  // Compute the clock divider that achieves the fastest speed less than or
232  // equal to the desired speed. The numerator is biased to favor a larger
233  // clock divider so that the resulting clock is always less than or equal
234  // to the desired clock, never greater.
235  //
236  ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) /
237  (2 * 10 * ui32SCLFreq)) - 1;
238  HWREG(ui32Base + I2C_O_MTPR) = ui32TPR;
239 
240  //
241  // Check to see if this I2C peripheral is High-Speed enabled. If yes, also
242  // choose the fastest speed that is less than or equal to 3.4 Mbps.
243  //
244  if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS)
245  {
246  ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) /
247  (2 * 3 * 3400000)) - 1;
248  HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR;
249  }
250 }
251 
252 //*****************************************************************************
253 //
266 //
267 //*****************************************************************************
268 void
269 I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
270 {
271  //
272  // Check the arguments.
273  //
274  ASSERT(_I2CBaseValid(ui32Base));
275  ASSERT(!(ui8SlaveAddr & 0x80));
276 
277  //
278  // Must enable the device before doing anything else.
279  //
280  I2CSlaveEnable(ui32Base);
281 
282  //
283  // Set up the slave address.
284  //
285  HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
286 }
287 
288 //*****************************************************************************
289 //
304 //
305 //*****************************************************************************
306 void
307 I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)
308 {
309  //
310  // Check the arguments.
311  //
312  ASSERT(_I2CBaseValid(ui32Base));
313  ASSERT(!(ui8AddrNum > 1));
314  ASSERT(!(ui8SlaveAddr & 0x80));
315 
316  //
317  // Determine which slave address is being set.
318  //
319  switch(ui8AddrNum)
320  {
321  //
322  // Set up the primary slave address.
323  //
324  case 0:
325  {
326  HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
327  break;
328  }
329 
330  //
331  // Set up and enable the secondary slave address.
332  //
333  case 1:
334  {
335  HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr;
336  break;
337  }
338  }
339 }
340 
341 //*****************************************************************************
342 //
350 //
351 //*****************************************************************************
352 void
353 I2CMasterEnable(uint32_t ui32Base)
354 {
355  //
356  // Check the arguments.
357  //
358  ASSERT(_I2CBaseValid(ui32Base));
359 
360  //
361  // Enable the master block.
362  //
363  HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE;
364 }
365 
366 //*****************************************************************************
367 //
375 //
376 //*****************************************************************************
377 void
378 I2CSlaveEnable(uint32_t ui32Base)
379 {
380  //
381  // Check the arguments.
382  //
383  ASSERT(_I2CBaseValid(ui32Base));
384 
385  //
386  // Enable the clock to the slave block.
387  //
388  HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE;
389 
390  //
391  // Enable the slave.
392  //
393  HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
394 }
395 
396 //*****************************************************************************
397 //
405 //
406 //*****************************************************************************
407 void
408 I2CMasterDisable(uint32_t ui32Base)
409 {
410  //
411  // Check the arguments.
412  //
413  ASSERT(_I2CBaseValid(ui32Base));
414 
415  //
416  // Disable the master block.
417  //
418  HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE);
419 }
420 
421 //*****************************************************************************
422 //
430 //
431 //*****************************************************************************
432 void
433 I2CSlaveDisable(uint32_t ui32Base)
434 {
435  //
436  // Check the arguments.
437  //
438  ASSERT(_I2CBaseValid(ui32Base));
439 
440  //
441  // Disable the slave.
442  //
443  HWREG(ui32Base + I2C_O_SCSR) = 0;
444 
445  //
446  // Disable the clock to the slave block.
447  //
448  HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE);
449 }
450 
451 //*****************************************************************************
452 //
470 //
471 //*****************************************************************************
472 void
473 I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
474 {
475  uint32_t ui32Int;
476 
477  //
478  // Check the arguments.
479  //
480  ASSERT(_I2CBaseValid(ui32Base));
481 
482  //
483  // Determine the interrupt number based on the I2C port.
484  //
485  ui32Int = _I2CIntNumberGet(ui32Base);
486 
487  ASSERT(ui32Int != 0);
488 
489  //
490  // Register the interrupt handler, returning an error if an error occurs.
491  //
492  IntRegister(ui32Int, pfnHandler);
493 
494  //
495  // Enable the I2C interrupt.
496  //
497  IntEnable(ui32Int);
498 }
499 
500 //*****************************************************************************
501 //
514 //
515 //*****************************************************************************
516 void
517 I2CIntUnregister(uint32_t ui32Base)
518 {
519  uint32_t ui32Int;
520 
521  //
522  // Check the arguments.
523  //
524  ASSERT(_I2CBaseValid(ui32Base));
525 
526  //
527  // Determine the interrupt number based on the I2C port.
528  //
529  ui32Int = _I2CIntNumberGet(ui32Base);
530 
531  ASSERT(ui32Int != 0);
532 
533  //
534  // Disable the interrupt.
535  //
536  IntDisable(ui32Int);
537 
538  //
539  // Unregister the interrupt handler.
540  //
541  IntUnregister(ui32Int);
542 }
543 
544 //*****************************************************************************
545 //
553 //
554 //*****************************************************************************
555 void
556 I2CMasterIntEnable(uint32_t ui32Base)
557 {
558  //
559  // Check the arguments.
560  //
561  ASSERT(_I2CBaseValid(ui32Base));
562 
563  //
564  // Enable the master interrupt.
565  //
566  HWREG(ui32Base + I2C_O_MIMR) = 1;
567 }
568 
569 //*****************************************************************************
570 //
600 //
601 //*****************************************************************************
602 void
603 I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
604 {
605  //
606  // Check the arguments.
607  //
608  ASSERT(_I2CBaseValid(ui32Base));
609 
610  //
611  // Enable the master interrupt.
612  //
613  HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags;
614 }
615 
616 //*****************************************************************************
617 //
625 //
626 //*****************************************************************************
627 void
628 I2CSlaveIntEnable(uint32_t ui32Base)
629 {
630  //
631  // Check the arguments.
632  //
633  ASSERT(_I2CBaseValid(ui32Base));
634 
635  //
636  // Enable the slave interrupt.
637  //
638  HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
639 }
640 
641 //*****************************************************************************
642 //
669 //
670 //*****************************************************************************
671 void
672 I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
673 {
674  //
675  // Check the arguments.
676  //
677  ASSERT(_I2CBaseValid(ui32Base));
678 
679  //
680  // Enable the slave interrupt.
681  //
682  HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags;
683 }
684 
685 //*****************************************************************************
686 //
694 //
695 //*****************************************************************************
696 void
697 I2CMasterIntDisable(uint32_t ui32Base)
698 {
699  //
700  // Check the arguments.
701  //
702  ASSERT(_I2CBaseValid(ui32Base));
703 
704  //
705  // Disable the master interrupt.
706  //
707  HWREG(ui32Base + I2C_O_MIMR) = 0;
708 }
709 
710 //*****************************************************************************
711 //
726 //
727 //*****************************************************************************
728 void
729 I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
730 {
731  //
732  // Check the arguments.
733  //
734  ASSERT(_I2CBaseValid(ui32Base));
735 
736  //
737  // Disable the master interrupt.
738  //
739  HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags;
740 }
741 
742 //*****************************************************************************
743 //
751 //
752 //*****************************************************************************
753 void
754 I2CSlaveIntDisable(uint32_t ui32Base)
755 {
756  //
757  // Check the arguments.
758  //
759  ASSERT(_I2CBaseValid(ui32Base));
760 
761  //
762  // Disable the slave interrupt.
763  //
764  HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
765 }
766 
767 //*****************************************************************************
768 //
783 //
784 //*****************************************************************************
785 void
786 I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
787 {
788  //
789  // Check the arguments.
790  //
791  ASSERT(_I2CBaseValid(ui32Base));
792 
793  //
794  // Disable the slave interrupt.
795  //
796  HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags;
797 }
798 
799 //*****************************************************************************
800 //
813 //
814 //*****************************************************************************
815 bool
816 I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
817 {
818  //
819  // Check the arguments.
820  //
821  ASSERT(_I2CBaseValid(ui32Base));
822 
823  //
824  // Return either the interrupt status or the raw interrupt status as
825  // requested.
826  //
827  if(bMasked)
828  {
829  return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false);
830  }
831  else
832  {
833  return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false);
834  }
835 }
836 
837 //*****************************************************************************
838 //
851 //
852 //*****************************************************************************
853 uint32_t
854 I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked)
855 {
856  //
857  // Check the arguments.
858  //
859  ASSERT(_I2CBaseValid(ui32Base));
860 
861  //
862  // Return either the interrupt status or the raw interrupt status as
863  // requested.
864  //
865  if(bMasked)
866  {
867  return(HWREG(ui32Base + I2C_O_MMIS));
868  }
869  else
870  {
871  return(HWREG(ui32Base + I2C_O_MRIS));
872  }
873 }
874 
875 //*****************************************************************************
876 //
889 //
890 //*****************************************************************************
891 bool
892 I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
893 {
894  //
895  // Check the arguments.
896  //
897  ASSERT(_I2CBaseValid(ui32Base));
898 
899  //
900  // Return either the interrupt status or the raw interrupt status as
901  // requested.
902  //
903  if(bMasked)
904  {
905  return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false);
906  }
907  else
908  {
909  return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false);
910  }
911 }
912 
913 //*****************************************************************************
914 //
927 //
928 //*****************************************************************************
929 uint32_t
930 I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked)
931 {
932  //
933  // Check the arguments.
934  //
935  ASSERT(_I2CBaseValid(ui32Base));
936 
937  //
938  // Return either the interrupt status or the raw interrupt status as
939  // requested.
940  //
941  if(bMasked)
942  {
943  return(HWREG(ui32Base + I2C_O_SMIS));
944  }
945  else
946  {
947  return(HWREG(ui32Base + I2C_O_SRIS));
948  }
949 }
950 
951 //*****************************************************************************
952 //
971 //
972 //*****************************************************************************
973 void
974 I2CMasterIntClear(uint32_t ui32Base)
975 {
976  //
977  // Check the arguments.
978  //
979  ASSERT(_I2CBaseValid(ui32Base));
980 
981  //
982  // Clear the I2C master interrupt source.
983  //
984  HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC;
985 
986  //
987  // Workaround for I2C master interrupt clear errata for rev B Tiva
988  // devices. For later devices, this write is ignored and therefore
989  // harmless (other than the slight performance hit).
990  //
991  HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC;
992 }
993 
994 //*****************************************************************************
995 //
1018 //
1019 //*****************************************************************************
1020 void
1021 I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
1022 {
1023  //
1024  // Check the arguments.
1025  //
1026  ASSERT(_I2CBaseValid(ui32Base));
1027 
1028  //
1029  // Clear the I2C master interrupt source.
1030  //
1031  HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags;
1032 }
1033 
1034 //*****************************************************************************
1035 //
1054 //
1055 //*****************************************************************************
1056 void
1057 I2CSlaveIntClear(uint32_t ui32Base)
1058 {
1059  //
1060  // Check the arguments.
1061  //
1062  ASSERT(_I2CBaseValid(ui32Base));
1063 
1064  //
1065  // Clear the I2C slave interrupt source.
1066  //
1067  HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC;
1068 }
1069 
1070 //*****************************************************************************
1071 //
1094 //
1095 //*****************************************************************************
1096 void
1097 I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
1098 {
1099  //
1100  // Check the arguments.
1101  //
1102  ASSERT(_I2CBaseValid(ui32Base));
1103 
1104  //
1105  // Clear the I2C slave interrupt source.
1106  //
1107  HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags;
1108 }
1109 
1110 //*****************************************************************************
1111 //
1125 //
1126 //*****************************************************************************
1127 void
1128 I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr,
1129  bool bReceive)
1130 {
1131  //
1132  // Check the arguments.
1133  //
1134  ASSERT(_I2CBaseValid(ui32Base));
1135  ASSERT(!(ui8SlaveAddr & 0x80));
1136 
1137  //
1138  // Set the address of the slave with which the master will communicate.
1139  //
1140  HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
1141 }
1142 
1143 //*****************************************************************************
1144 //
1157 //
1158 //*****************************************************************************
1159 uint32_t
1160 I2CMasterLineStateGet(uint32_t ui32Base)
1161 {
1162  //
1163  // Check the arguments.
1164  //
1165  ASSERT(_I2CBaseValid(ui32Base));
1166 
1167  //
1168  // Return the line state.
1169  //
1170  return(HWREG(ui32Base + I2C_O_MBMON));
1171 }
1172 
1173 //*****************************************************************************
1174 //
1184 //
1185 //*****************************************************************************
1186 bool
1187 I2CMasterBusy(uint32_t ui32Base)
1188 {
1189  //
1190  // Check the arguments.
1191  //
1192  ASSERT(_I2CBaseValid(ui32Base));
1193 
1194  //
1195  // Return the busy status.
1196  //
1197  if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY)
1198  {
1199  return(true);
1200  }
1201  else
1202  {
1203  return(false);
1204  }
1205 }
1206 
1207 //*****************************************************************************
1208 //
1219 //
1220 //*****************************************************************************
1221 bool
1222 I2CMasterBusBusy(uint32_t ui32Base)
1223 {
1224  //
1225  // Check the arguments.
1226  //
1227  ASSERT(_I2CBaseValid(ui32Base));
1228 
1229  //
1230  // Return the bus busy status.
1231  //
1232  if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY)
1233  {
1234  return(true);
1235  }
1236  else
1237  {
1238  return(false);
1239  }
1240 }
1241 
1242 //*****************************************************************************
1243 //
1281 //
1282 //*****************************************************************************
1283 void
1284 I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
1285 {
1286  //
1287  // Check the arguments.
1288  //
1289  ASSERT(_I2CBaseValid(ui32Base));
1290  ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
1291  (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
1292  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
1293  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
1294  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
1295  (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
1296  (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
1297  (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
1298  (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
1300  (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) ||
1301  (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) ||
1302  (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) ||
1303  (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) ||
1304  (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) ||
1311  (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND));
1312 
1313  //
1314  // Send the command.
1315  //
1316  HWREG(ui32Base + I2C_O_MCS) = ui32Cmd;
1317 }
1318 
1319 //*****************************************************************************
1320 //
1331 //
1332 //*****************************************************************************
1333 uint32_t
1334 I2CMasterErr(uint32_t ui32Base)
1335 {
1336  uint32_t ui32Err;
1337 
1338  //
1339  // Check the arguments.
1340  //
1341  ASSERT(_I2CBaseValid(ui32Base));
1342 
1343  //
1344  // Get the raw error state
1345  //
1346  ui32Err = HWREG(ui32Base + I2C_O_MCS);
1347 
1348  //
1349  // If the I2C master is busy, then all the other bit are invalid, and
1350  // don't have an error to report.
1351  //
1352  if(ui32Err & I2C_MCS_BUSY)
1353  {
1354  return(I2C_MASTER_ERR_NONE);
1355  }
1356 
1357  //
1358  // Check for errors.
1359  //
1360  if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST))
1361  {
1362  return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK));
1363  }
1364  else
1365  {
1366  return(I2C_MASTER_ERR_NONE);
1367  }
1368 }
1369 
1370 //*****************************************************************************
1371 //
1380 //
1381 //*****************************************************************************
1382 void
1383 I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
1384 {
1385  //
1386  // Check the arguments.
1387  //
1388  ASSERT(_I2CBaseValid(ui32Base));
1389 
1390  //
1391  // Write the byte.
1392  //
1393  HWREG(ui32Base + I2C_O_MDR) = ui8Data;
1394 }
1395 
1396 //*****************************************************************************
1397 //
1406 //
1407 //*****************************************************************************
1408 uint32_t
1409 I2CMasterDataGet(uint32_t ui32Base)
1410 {
1411  //
1412  // Check the arguments.
1413  //
1414  ASSERT(_I2CBaseValid(ui32Base));
1415 
1416  //
1417  // Read a byte.
1418  //
1419  return(HWREG(ui32Base + I2C_O_MDR));
1420 }
1421 
1422 //*****************************************************************************
1423 //
1439 //
1440 //*****************************************************************************
1441 void
1442 I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value)
1443 {
1444  //
1445  // Check the arguments.
1446  //
1447  ASSERT(_I2CBaseValid(ui32Base));
1448 
1449  //
1450  // Write the timeout value.
1451  //
1452  HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value;
1453 }
1454 
1455 //*****************************************************************************
1456 //
1469 //
1470 //*****************************************************************************
1471 void
1472 I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable)
1473 {
1474  //
1475  // Check the arguments.
1476  //
1477  ASSERT(_I2CBaseValid(ui32Base));
1478 
1479  //
1480  // Enable or disable based on bEnable.
1481  //
1482  if(bEnable)
1483  {
1484  HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN;
1485  }
1486  else
1487  {
1488  HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN;
1489  }
1490 }
1491 
1492 //*****************************************************************************
1493 //
1504 //
1505 //*****************************************************************************
1506 void
1507 I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK)
1508 {
1509  //
1510  // Check the arguments.
1511  //
1512  ASSERT(_I2CBaseValid(ui32Base));
1513 
1514  //
1515  // ACK or NACK based on the value of bACK.
1516  //
1517  if(bACK)
1518  {
1519  HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL;
1520  }
1521  else
1522  {
1523  HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL;
1524  }
1525 }
1526 
1527 //*****************************************************************************
1528 //
1558 //
1559 //*****************************************************************************
1560 uint32_t
1561 I2CSlaveStatus(uint32_t ui32Base)
1562 {
1563  //
1564  // Check the arguments.
1565  //
1566  ASSERT(_I2CBaseValid(ui32Base));
1567 
1568  //
1569  // Return the slave status.
1570  //
1571  return(HWREG(ui32Base + I2C_O_SCSR));
1572 }
1573 
1574 //*****************************************************************************
1575 //
1584 //
1585 //*****************************************************************************
1586 void
1587 I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
1588 {
1589  //
1590  // Check the arguments.
1591  //
1592  ASSERT(_I2CBaseValid(ui32Base));
1593 
1594  //
1595  // Write the byte.
1596  //
1597  HWREG(ui32Base + I2C_O_SDR) = ui8Data;
1598 }
1599 
1600 //*****************************************************************************
1601 //
1610 //
1611 //*****************************************************************************
1612 uint32_t
1613 I2CSlaveDataGet(uint32_t ui32Base)
1614 {
1615  //
1616  // Check the arguments.
1617  //
1618  ASSERT(_I2CBaseValid(ui32Base));
1619 
1620  //
1621  // Read a byte.
1622  //
1623  return(HWREG(ui32Base + I2C_O_SDR));
1624 }
1625 
1626 //*****************************************************************************
1627 //
1652 //
1653 //*****************************************************************************
1654 void
1655 I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
1656 {
1657  //
1658  // Check the arguments.
1659  //
1660  ASSERT(_I2CBaseValid(ui32Base));
1661 
1662  //
1663  // Clear transmit configuration data.
1664  //
1665  HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000;
1666 
1667  //
1668  // Store new transmit configuration data.
1669  //
1670  HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
1671 }
1672 
1673 //*****************************************************************************
1674 //
1685 //
1686 //*****************************************************************************
1687 void
1688 I2CTxFIFOFlush(uint32_t ui32Base)
1689 {
1690  //
1691  // Check the arguments.
1692  //
1693  ASSERT(_I2CBaseValid(ui32Base));
1694 
1695  //
1696  // Flush the TX FIFO.
1697  //
1698  HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH;
1699 }
1700 
1701 //*****************************************************************************
1702 //
1726 //
1727 //*****************************************************************************
1728 void
1729 I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
1730 {
1731  //
1732  // Check the arguments.
1733  //
1734  ASSERT(_I2CBaseValid(ui32Base));
1735 
1736  //
1737  // Clear receive configuration data.
1738  //
1739  HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff;
1740 
1741  //
1742  // Store new receive configuration data.
1743  //
1744  HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
1745 }
1746 
1747 //*****************************************************************************
1748 //
1759 //
1760 //*****************************************************************************
1761 void
1762 I2CRxFIFOFlush(uint32_t ui32Base)
1763 {
1764  //
1765  // Check the arguments.
1766  //
1767  ASSERT(_I2CBaseValid(ui32Base));
1768 
1769  //
1770  // Flush the TX FIFO.
1771  //
1772  HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH;
1773 }
1774 
1775 //*****************************************************************************
1776 //
1792 //
1793 //*****************************************************************************
1794 uint32_t
1795 I2CFIFOStatus(uint32_t ui32Base)
1796 {
1797  //
1798  // Check the arguments.
1799  //
1800  ASSERT(_I2CBaseValid(ui32Base));
1801 
1802  //
1803  // Return the contents of the FIFO status register.
1804  //
1805  return(HWREG(ui32Base + I2C_O_FIFOSTATUS));
1806 }
1807 
1808 //*****************************************************************************
1809 //
1823 //
1824 //*****************************************************************************
1825 void
1826 I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data)
1827 {
1828  //
1829  // Check the arguments.
1830  //
1831  ASSERT(_I2CBaseValid(ui32Base));
1832 
1833  //
1834  // Wait until there is space.
1835  //
1836  while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
1837  {
1838  }
1839 
1840  //
1841  // Place data into the FIFO.
1842  //
1843  HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
1844 }
1845 
1846 //*****************************************************************************
1847 //
1860 //
1861 //*****************************************************************************
1862 uint32_t
1863 I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data)
1864 {
1865  //
1866  // Check the arguments.
1867  //
1868  ASSERT(_I2CBaseValid(ui32Base));
1869 
1870  //
1871  // If FIFO is full, return zero.
1872  //
1873  if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
1874  {
1875  return(0);
1876  }
1877  else
1878  {
1879  HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
1880  return(1);
1881  }
1882 }
1883 
1884 //*****************************************************************************
1885 //
1898 //
1899 //*****************************************************************************
1900 uint32_t
1901 I2CFIFODataGet(uint32_t ui32Base)
1902 {
1903  //
1904  // Check the arguments.
1905  //
1906  ASSERT(_I2CBaseValid(ui32Base));
1907 
1908  //
1909  // Wait until there is data to read.
1910  //
1911  while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
1912  {
1913  }
1914 
1915  //
1916  // Read a byte.
1917  //
1918  return(HWREG(ui32Base + I2C_O_FIFODATA));
1919 }
1920 
1921 //*****************************************************************************
1922 //
1936 //
1937 //*****************************************************************************
1938 uint32_t
1939 I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data)
1940 {
1941  //
1942  // Check the arguments.
1943  //
1944  ASSERT(_I2CBaseValid(ui32Base));
1945 
1946  //
1947  // If nothing in the FIFO, return zero.
1948  //
1949  if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
1950  {
1951  return(0);
1952  }
1953  else
1954  {
1955  *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA);
1956  return(1);
1957  }
1958 }
1959 
1960 //*****************************************************************************
1961 //
1978 //
1979 //*****************************************************************************
1980 void
1981 I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
1982 {
1983  //
1984  // Check the arguments.
1985  //
1986  ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255));
1987 
1988  //
1989  // Set the burst length.
1990  //
1991  HWREG(ui32Base + I2C_O_MBLEN) = ui8Length;
1992 }
1993 
1994 //*****************************************************************************
1995 //
2009 //
2010 //*****************************************************************************
2011 uint32_t
2012 I2CMasterBurstCountGet(uint32_t ui32Base)
2013 {
2014  //
2015  // Check the arguments.
2016  //
2017  ASSERT(_I2CBaseValid(ui32Base));
2018 
2019  //
2020  // Get burst count.
2021  //
2022  return(HWREG(ui32Base + I2C_O_MBCNT));
2023 }
2024 
2025 //*****************************************************************************
2026 //
2053 //
2054 //*****************************************************************************
2055 void
2056 I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
2057 {
2058  //
2059  // Check the arguments.
2060  //
2061  ASSERT(_I2CBaseValid(ui32Base));
2062 
2063  //
2064  // Configure the glitch filter field of MTPR.
2065  //
2066  HWREG(ui32Base + I2C_O_MTPR) |= ui32Config;
2067 }
2068 
2069 //*****************************************************************************
2070 //
2093 //
2094 //*****************************************************************************
2095 void
2096 I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config)
2097 {
2098  //
2099  // Check the arguments.
2100  //
2101  ASSERT(_I2CBaseValid(ui32Base));
2102 
2103  //
2104  // Enable the FIFOs for the slave.
2105  //
2106  HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA;
2107 }
2108 
2109 //*****************************************************************************
2110 //
2122 //
2123 //*****************************************************************************
2124 void
2125 I2CSlaveFIFODisable(uint32_t ui32Base)
2126 {
2127  //
2128  // Check the arguments.
2129  //
2130  ASSERT(_I2CBaseValid(ui32Base));
2131 
2132  //
2133  // Disable slave FIFOs.
2134  //
2135  HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
2136 }
2137 
2138 //*****************************************************************************
2139 //
2140 // Close the Doxygen group.
2142 //
2143 //*****************************************************************************
bool I2CMasterBusy(uint32_t ui32Base)
Definition: i2c.c:1187
#define I2C_MASTER_CMD_FIFO_BURST_SEND_START
Definition: i2c.h:103
#define INT_I2C7_TM4C129
Definition: hw_ints.h:277
void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)
Definition: i2c.c:307
static const int_fast8_t g_i8I2CIntMapSnowflakeRows
Definition: i2c.c:89
void I2CMasterEnable(uint32_t ui32Base)
Definition: i2c.c:353
void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:2056
#define I2C_SICR_DATAIC
Definition: hw_i2c.h:398
static const uint32_t g_ppui32I2CIntMapSnowflake[][2]
Definition: i2c.c:76
#define I2C_O_PP
Definition: hw_i2c.h:77
#define I2C_O_MCS
Definition: hw_i2c.h:49
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Definition: hw_i2c.h:48
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Definition: i2c.c:1729
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Definition: hw_i2c.h:69
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH
Definition: i2c.h:91
#define I2C_MCS_ADRACK
Definition: hw_i2c.h:105
bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:816
#define HWREG(x)
Definition: hw_types.h:48
void I2CTxFIFOFlush(uint32_t ui32Base)
Definition: i2c.c:1688
#define I2C_SACKCTL_ACKOVAL
Definition: hw_i2c.h:414
#define I2C_O_MICR
Definition: hw_i2c.h:56
#define INT_I2C8_TM4C129
Definition: hw_ints.h:279
static const uint32_t g_ppui32I2CIntMap[][2]
Definition: i2c.c:63
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Definition: i2c.c:1222
#define I2C_O_FIFOSTATUS
Definition: hw_i2c.h:76
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Definition: i2c.c:1901
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Definition: i2c.c:697
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Definition: i2c.c:408
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START
Definition: i2c.h:111
void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1587
#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE
Definition: i2c.h:101
uint32_t I2CSlaveStatus(uint32_t ui32Base)
Definition: i2c.c:1561
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Definition: i2c.c:2012
void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:1655
#define ASSERT(expr)
Definition: debug.h:67
#define I2C_MTPR_HS
Definition: hw_i2c.h:135
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Definition: i2c.c:672
#define I2C_SOAR2_OAR2EN
Definition: hw_i2c.h:405
#define INT_I2C9_TM4C129
Definition: hw_ints.h:280
#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP
Definition: i2c.h:109
#define INT_I2C0_TM4C129
Definition: hw_ints.h:184
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Definition: i2c.c:1762
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Definition: i2c.c:1383
#define I2C_O_SIMR
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#define I2C_MCR_MFE
Definition: hw_i2c.h:239
#define INT_I2C3_TM4C129
Definition: hw_ints.h:238
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Definition: i2c.c:1057
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Definition: i2c.c:1826
#define I2C1_BASE
Definition: hw_memmap.h:70
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Definition: i2c.c:1507
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Definition: i2c.c:1128
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Definition: i2c.c:202
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Definition: i2c.c:854
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Definition: i2c.c:269
#define I2C_MASTER_CMD_BURST_SEND_START
Definition: i2c.h:77
#define I2C_MCS_DATACK
Definition: hw_i2c.h:104
void I2CSlaveIntEnable(uint32_t ui32Base)
Definition: i2c.c:628
#define INT_I2C2_TM4C129
Definition: hw_ints.h:237
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Definition: hw_memmap.h:125
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Definition: hw_i2c.h:54
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH
Definition: i2c.h:115
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Definition: i2c.c:974
#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH
Definition: i2c.h:107
#define INT_I2C1_TM4C123
Definition: hw_ints.h:102
#define I2C_O_FIFOCTL
Definition: hw_i2c.h:75
#define I2C_O_MCLKOCNT
Definition: hw_i2c.h:58
uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:930
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Definition: i2c.c:1863
#define I2C_MASTER_CMD_BURST_RECEIVE_START
Definition: i2c.h:87
#define I2C_O_SCSR
Definition: hw_i2c.h:65
#define I2C_MASTER_ERR_NONE
Definition: i2c.h:147
#define INT_I2C5_TM4C123
Definition: hw_ints.h:145
#define I2C_O_MBMON
Definition: hw_i2c.h:60
#define I2C_MCS_ERROR
Definition: hw_i2c.h:107
static const int_fast8_t g_i8I2CIntMapRows
Definition: i2c.c:73
#define I2C_O_SRIS
Definition: hw_i2c.h:68
void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:2096
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Definition: i2c.c:433
#define INT_I2C0_TM4C123
Definition: hw_ints.h:72
#define I2C5_BASE
Definition: hw_memmap.h:126
#define I2C_MCR_SFE
Definition: hw_i2c.h:238
#define I2C_O_MBLEN
Definition: hw_i2c.h:61
#define I2C_O_MDR
Definition: hw_i2c.h:50
void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value)
Definition: i2c.c:1442
void I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:603
void I2CSlaveFIFODisable(uint32_t ui32Base)
Definition: i2c.c:2125
uint32_t I2CFIFOStatus(uint32_t ui32Base)
Definition: i2c.c:1795
#define I2C_MASTER_CMD_QUICK_COMMAND
Definition: i2c.h:95
#define I2C_FIFOSTATUS_RXFE
Definition: hw_i2c.h:450
void I2CSlaveIntDisable(uint32_t ui32Base)
Definition: i2c.c:754
#define INT_I2C3_TM4C123
Definition: hw_ints.h:126
#define INT_I2C1_TM4C129
Definition: hw_ints.h:213
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Definition: i2c.c:556
#define I2C7_BASE
Definition: hw_memmap.h:128
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Definition: i2c.c:1284
#define INT_I2C5_TM4C129
Definition: hw_ints.h:246
#define I2C_O_SICR
Definition: hw_i2c.h:71
#define I2C_O_MIMR
Definition: hw_i2c.h:52
uint32_t I2CMasterLineStateGet(uint32_t ui32Base)
Definition: i2c.c:1160
bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:892
#define INT_I2C2_TM4C123
Definition: hw_ints.h:125
uint32_t I2CMasterErr(uint32_t ui32Base)
Definition: i2c.c:1334
uint32_t I2CSlaveDataGet(uint32_t ui32Base)
Definition: i2c.c:1613
#define I2C_MASTER_CMD_BURST_SEND_FINISH
Definition: i2c.h:81
#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT
Definition: i2c.h:105
#define I2C6_BASE
Definition: hw_memmap.h:127
#define I2C_MASTER_CMD_SINGLE_RECEIVE
Definition: i2c.h:75
uint32_t I2CMasterDataGet(uint32_t ui32Base)
Definition: i2c.c:1409
uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data)
Definition: i2c.c:1939
#define I2C_O_MRIS
Definition: hw_i2c.h:53
void IntUnregister(uint32_t ui32Interrupt)
Definition: interrupt.c:381
#define I2C0_BASE
Definition: hw_memmap.h:69
#define I2C8_BASE
Definition: hw_memmap.h:123
#define I2C_O_SOAR
Definition: hw_i2c.h:64
void I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
Definition: i2c.c:1981
void I2CSlaveEnable(uint32_t ui32Base)
Definition: i2c.c:378
static uint32_t _I2CIntNumberGet(uint32_t ui32Base)
Definition: i2c.c:131
#define I2C_MCS_ARBLST
Definition: hw_i2c.h:101
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT
Definition: i2c.h:89
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
Definition: i2c.h:93
void I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:729
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
Definition: i2c.h:85
#define I2C_SACKCTL_ACKOEN
Definition: hw_i2c.h:415
#define I2C_PP_HS
Definition: hw_i2c.h:461
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP
Definition: i2c.h:117
#define I2C_FIFOCTL_RXFLUSH
Definition: hw_i2c.h:431
#define I2C_O_MBCNT
Definition: hw_i2c.h:62
#define I2C_MASTER_CMD_SINGLE_SEND
Definition: i2c.h:73
#define I2C_MASTER_CMD_FIFO_SINGLE_SEND
Definition: i2c.h:99
#define I2C_MCS_BUSY
Definition: hw_i2c.h:110
#define I2C_FIFOSTATUS_TXFF
Definition: hw_i2c.h:453
#define I2C3_BASE
Definition: hw_memmap.h:72
#define I2C_SCSR_DA
Definition: hw_i2c.h:311
void I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:1021
#define I2C2_BASE
Definition: hw_memmap.h:71
#define I2C_MASTER_CMD_BURST_SEND_CONT
Definition: i2c.h:79
#define CLASS_IS_TM4C129
Definition: hw_types.h:99
#define INT_I2C4_TM4C129
Definition: hw_ints.h:245
#define I2C_O_SACKCTL
Definition: hw_i2c.h:73
#define INT_I2C6_TM4C129
Definition: hw_ints.h:276
#define I2C_MICR_IC
Definition: hw_i2c.h:230
void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable)
Definition: i2c.c:1472
#define I2C_SLAVE_INT_DATA
Definition: i2c.h:217
#define I2C_O_MTPR
Definition: hw_i2c.h:51
void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
Definition: i2c.c:473
#define I2C_O_FIFODATA
Definition: hw_i2c.h:74
void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:1097
#define I2C_O_MCR
Definition: hw_i2c.h:57
void I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:786
#define I2C_O_SOAR2
Definition: hw_i2c.h:72
#define I2C_MCS_BUSBSY
Definition: hw_i2c.h:98
void IntDisable(uint32_t ui32Interrupt)
Definition: interrupt.c:684
void IntRegister(uint32_t ui32Interrupt, void(*pfnHandler)(void))
Definition: interrupt.c:309
void I2CIntUnregister(uint32_t ui32Base)
Definition: i2c.c:517
void IntEnable(uint32_t ui32Interrupt)
Definition: interrupt.c:610
#define I2C_O_SDR
Definition: hw_i2c.h:66
#define INT_I2C4_TM4C123
Definition: hw_ints.h:144
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT
Definition: i2c.h:113
#define I2C_FIFOCTL_TXFLUSH
Definition: hw_i2c.h:435