emac.c

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//*****************************************************************************
//
// emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class
//          Tiva devices.
//
// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************

#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_emac.h"
#include "driverlib/debug.h"
#include "driverlib/emac.h"
#include "driverlib/sysctl.h"
#include "driverlib/interrupt.h"
#include "driverlib/sw_crc.h"

//*****************************************************************************
//
// Combined defines used in parameter validity checks.
//
//*****************************************************************************

//*****************************************************************************
//
// Combined valid configuration flags.
//
//*****************************************************************************
#define VALID_CONFIG_FLAGS      (EMAC_CONFIG_USE_MACADDR1 |                   \
                                 EMAC_CONFIG_SA_INSERT |                      \
                                 EMAC_CONFIG_SA_REPLACE |                     \
                                 EMAC_CONFIG_2K_PACKETS |                     \
                                 EMAC_CONFIG_STRIP_CRC |                      \
                                 EMAC_CONFIG_JABBER_DISABLE |                 \
                                 EMAC_CONFIG_JUMBO_ENABLE |                   \
                                 EMAC_CONFIG_IF_GAP_MASK |                    \
                                 EMAC_CONFIG_CS_DISABLE |                     \
                                 EMAC_CONFIG_100MBPS |                        \
                                 EMAC_CONFIG_RX_OWN_DISABLE |                 \
                                 EMAC_CONFIG_LOOPBACK |                       \
                                 EMAC_CONFIG_FULL_DUPLEX |                    \
                                 EMAC_CONFIG_CHECKSUM_OFFLOAD |               \
                                 EMAC_CONFIG_RETRY_DISABLE |                  \
                                 EMAC_CONFIG_AUTO_CRC_STRIPPING |             \
                                 EMAC_CONFIG_BO_MASK |                        \
                                 EMAC_CONFIG_DEFERRAL_CHK_ENABLE |            \
                                 EMAC_CONFIG_PREAMBLE_MASK)

//*****************************************************************************
//
// Combined valid frame filter flags.
//
//*****************************************************************************
#define VALID_FRMFILTER_FLAGS   (EMAC_FRMFILTER_RX_ALL |                      \
                                 EMAC_FRMFILTER_VLAN |                        \
                                 EMAC_FRMFILTER_HASH_AND_PERFECT |            \
                                 EMAC_FRMFILTER_SADDR |                       \
                                 EMAC_FRMFILTER_INV_SADDR |                   \
                                 EMAC_FRMFILTER_PASS_NO_PAUSE |               \
                                 EMAC_FRMFILTER_PASS_ALL_CTRL |               \
                                 EMAC_FRMFILTER_PASS_ADDR_CTRL |              \
                                 EMAC_FRMFILTER_BROADCAST |                   \
                                 EMAC_FRMFILTER_PASS_MULTICAST |              \
                                 EMAC_FRMFILTER_INV_DADDR |                   \
                                 EMAC_FRMFILTER_HASH_MULTICAST |              \
                                 EMAC_FRMFILTER_HASH_UNICAST |                \
                                 EMAC_FRMFILTER_PROMISCUOUS)

//*****************************************************************************
//
// Combined valid maskable interrupts.
//
//*****************************************************************************
#define EMAC_MASKABLE_INTS      (EMAC_INT_EARLY_RECEIVE |                     \
                                 EMAC_INT_BUS_ERROR |                         \
                                 EMAC_INT_EARLY_TRANSMIT |                    \
                                 EMAC_INT_RX_WATCHDOG |                       \
                                 EMAC_INT_RX_STOPPED |                        \
                                 EMAC_INT_RX_NO_BUFFER |                      \
                                 EMAC_INT_RECEIVE |                           \
                                 EMAC_INT_TX_UNDERFLOW |                      \
                                 EMAC_INT_RX_OVERFLOW |                       \
                                 EMAC_INT_TX_JABBER |                         \
                                 EMAC_INT_TX_NO_BUFFER |                      \
                                 EMAC_INT_TX_STOPPED |                        \
                                 EMAC_INT_TRANSMIT |                          \
                                 EMAC_INT_NORMAL_INT |                        \
                                 EMAC_INT_ABNORMAL_INT |                      \
                                 EMAC_INT_PHY)

//*****************************************************************************
//
// Combined valid normal interrupts.
//
//*****************************************************************************
#define EMAC_NORMAL_INTS        (EMAC_INT_TRANSMIT |                          \
                                 EMAC_INT_RECEIVE |                           \
                                 EMAC_INT_EARLY_RECEIVE |                     \
                                 EMAC_INT_TX_NO_BUFFER)

//*****************************************************************************
//
// Combined valid abnormal interrupts.
//
//*****************************************************************************
#define EMAC_ABNORMAL_INTS      (EMAC_INT_TX_STOPPED |                        \
                                 EMAC_INT_TX_JABBER |                         \
                                 EMAC_INT_RX_OVERFLOW |                       \
                                 EMAC_INT_TX_UNDERFLOW |                      \
                                 EMAC_INT_RX_NO_BUFFER |                      \
                                 EMAC_INT_RX_STOPPED |                        \
                                 EMAC_INT_RX_WATCHDOG |                       \
                                 EMAC_INT_EARLY_TRANSMIT |                    \
                                 EMAC_INT_BUS_ERROR)

//*****************************************************************************
//
// Interrupt sources reported via the DMARIS register but which are not
// masked (or enabled) via the DMAIM register.
//
//*****************************************************************************
#define EMAC_NON_MASKED_INTS    (EMAC_DMARIS_TT |                             \
                                 EMAC_DMARIS_PMT |                            \
                                 EMAC_DMARIS_MMC)

//*****************************************************************************
//
// The number of MAC addresses the module can store for filtering purposes.
//
//*****************************************************************************
#define NUM_MAC_ADDR            4

//*****************************************************************************
//
// Macros aiding access to the MAC address registers.
//
//*****************************************************************************
#define MAC_ADDR_OFFSET         (EMAC_O_ADDR1L - EMAC_O_ADDR0L)
#define EMAC_O_ADDRL(n)         (EMAC_O_ADDR0L + (MAC_ADDR_OFFSET * (n)))
#define EMAC_O_ADDRH(n)         (EMAC_O_ADDR0H + (MAC_ADDR_OFFSET * (n)))

//*****************************************************************************
//
// A structure used to help in choosing the correct clock divisor for the MII
// based on the current system clock rate.
//
//*****************************************************************************
static const struct
{
    uint32_t ui32SysClockMax;
    uint32_t ui32Divisor;
}
g_pi16MIIClockDiv[] =
{
    { 64000000, EMAC_MIIADDR_CR_35_60 },
    { 104000000, EMAC_MIIADDR_CR_60_100 },
    { 150000000, EMAC_MIIADDR_CR_100_150 }
};

//*****************************************************************************
//
// The number of clock divisors in the above table.
//
//*****************************************************************************
#define NUM_CLOCK_DIVISORS      (sizeof(g_pi16MIIClockDiv) /                  \
                                 sizeof(g_pi16MIIClockDiv[0]))

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACInit(uint32_t ui32Base, uint32_t ui32SysClk, uint32_t ui32BusConfig,
         uint32_t ui32RxBurst, uint32_t ui32TxBurst, uint32_t ui32DescSkipSize)
{
    uint32_t ui32Val, ui32Div;

    //
    // Parameter sanity checks.
    //
    ASSERT(ui32DescSkipSize < 32);
    ASSERT(ui32TxBurst < (32 * 8));
    ASSERT(ui32RxBurst < (32 * 8));

    //
    // Make sure that the DMA software reset is clear before continuing.
    //
    while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR)
    {
    }

    //
    // Set common flags.  Note that this driver assumes we are always using
    // 8 word descriptors so we need to OR in EMAC_DMABUSMOD_ATDS here.
    //
    ui32Val = (ui32BusConfig | (ui32DescSkipSize << EMAC_DMABUSMOD_DSL_S) |
               EMAC_DMABUSMOD_ATDS);

    //
    // Do we need to use the 8X burst length multiplier?
    //
    if((ui32TxBurst > 32) || (ui32RxBurst > 32))
    {
        //
        // Divide both burst lengths by 8 and set the 8X burst length
        // multiplier.
        //
        ui32Val |= EMAC_DMABUSMOD_8XPBL;
        ui32TxBurst >>= 3;
        ui32RxBurst >>= 3;

        //
        // Sanity check - neither burst length should have become zero.  If
        // they did, this indicates that the values passed are invalid.
        //
        ASSERT(ui32RxBurst);
        ASSERT(ui32TxBurst);
    }

    //
    // Are the receive and transmit burst lengths the same?
    //
    if(ui32RxBurst == ui32TxBurst)
    {
        //
        // Yes - set up to use a single burst length.
        //
        ui32Val |= (ui32TxBurst << EMAC_DMABUSMOD_PBL_S);
    }
    else
    {
        //
        // No - we need to use separate burst lengths for each.
        //
        ui32Val |= (EMAC_DMABUSMOD_USP |
                    (ui32TxBurst << EMAC_DMABUSMOD_PBL_S) |
                    (ui32RxBurst << EMAC_DMABUSMOD_RPBL_S));
    }

    //
    // Finally, write the bus mode register.
    //
    HWREG(ui32Base + EMAC_O_DMABUSMOD) = ui32Val;

    //
    // Default the MII CSR clock divider based on the fastest system clock.
    //
    ui32Div = g_pi16MIIClockDiv[NUM_CLOCK_DIVISORS - 1].ui32Divisor;

    //
    // Find the MII CSR clock divider to use based on the current system clock.
    //
    for(ui32Val = 0; ui32Val < NUM_CLOCK_DIVISORS; ui32Val++)
    {
        if(ui32SysClk <= g_pi16MIIClockDiv[ui32Val].ui32SysClockMax)
        {
            ui32Div = g_pi16MIIClockDiv[ui32Val].ui32Divisor;
            break;
        }
    }

    //
    // Set the MII CSR clock speed.
    //
    HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) &
                                         ~EMAC_MIIADDR_CR_M) | ui32Div);

    //
    // Disable all the MMC interrupts as these are enabled by default at reset.
    //
    HWREG(ui32Base + EMAC_O_MMCRXIM) = 0xFFFFFFFF;
    HWREG(ui32Base + EMAC_O_MMCTXIM) = 0xFFFFFFFF;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACReset(uint32_t ui32Base)
{
    //
    // Reset the Ethernet MAC.
    //
    HWREG(ui32Base + EMAC_O_DMABUSMOD) |= EMAC_DMABUSMOD_SWR;

    //
    // Wait for the reset to complete.
    //
    while(HWREG(ui32Base + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR)
    {
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACPHYConfigSet(uint32_t ui32Base, uint32_t ui32Config)
{
    //
    // Write the Ethernet PHY configuration to the peripheral configuration
    // register.
    //
    HWREG(ui32Base + EMAC_O_PC) = ui32Config;

    //
    // If using the internal PHY, reset it to ensure that new configuration is
    // latched there.
    //
    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_INTERNAL)
    {
        SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
        while(!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0))
        {
            //
            // Wait for the PHY reset to complete.
            //
        }

        //
        // Delay a bit longer to ensure that the PHY reset has completed.
        //
        SysCtlDelay(10000);
    }

    //
    // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC
    // Clock Configuration Register.
    //
    if((ui32Config & EMAC_PHY_TYPE_MASK) == EMAC_PHY_TYPE_EXTERNAL_RMII)
    {
        //
        // Select and enable the external clock from the RMII PHY.
        //
        HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN;
    }
    else
    {
        //
        // Disable the external clock.
        //
        HWREG(EMAC0_BASE + EMAC_O_CC) &= ~EMAC_CC_CLKEN;
    }

    //
    // Reset the MAC regardless of whether the PHY connection changed or not.
    //
    EMACReset(EMAC0_BASE);

    SysCtlDelay(1000);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACConfigSet(uint32_t ui32Base, uint32_t ui32Config, uint32_t ui32ModeFlags,
              uint32_t ui32RxMaxFrameSize)
{
    //
    // Parameter sanity check.  Note that we allow TX_ENABLED and RX_ENABLED
    // here because we'll mask them off before writing the value and this
    // makes back-to-back EMACConfigGet/EMACConfigSet calls work without the
    // caller needing to explicitly remove these bits from the parameter.
    //
    ASSERT((ui32Config & ~(VALID_CONFIG_FLAGS |  EMAC_CONFIG_TX_ENABLED |
                           EMAC_CONFIG_RX_ENABLED)) == 0);
    ASSERT(!ui32RxMaxFrameSize || ((ui32RxMaxFrameSize < 0x4000) &&
                                   (ui32RxMaxFrameSize > 1522)));

    //
    // Set the configuration flags as specified.  Note that we unconditionally
    // OR in the EMAC_CFG_PS bit here since this implementation supports only
    // MII and RMII interfaces to the PHYs.
    //
    HWREG(ui32Base + EMAC_O_CFG) =
        ((HWREG(ui32Base + EMAC_O_CFG) & ~VALID_CONFIG_FLAGS) | ui32Config |
         EMAC_CFG_PS);

    //
    // Set the maximum receive frame size.  If 0 is passed, this implies
    // that the default maximum frame size should be used so just turn off
    // the override.
    //
    if(ui32RxMaxFrameSize)
    {
        HWREG(ui32Base + EMAC_O_WDOGTO) = ui32RxMaxFrameSize | EMAC_WDOGTO_PWE;
    }
    else
    {
        HWREG(ui32Base + EMAC_O_WDOGTO) &= ~EMAC_WDOGTO_PWE;
    }

    //
    // Set the operating mode register.
    //
    HWREG(ui32Base + EMAC_O_DMAOPMODE) = ui32ModeFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACConfigGet(uint32_t ui32Base, uint32_t *pui32Config, uint32_t *pui32Mode,
              uint32_t *pui32RxMaxFrameSize)
{
    uint32_t ui32Value;

    //
    // Parameter sanity check.
    //
    ASSERT(pui32Mode);
    ASSERT(pui32Config);
    ASSERT(pui32RxMaxFrameSize);

    //
    // Return the mode information from the operation mode register.
    //
    *pui32Mode = HWREG(ui32Base + EMAC_O_DMAOPMODE);

    //
    // Return the current configuration flags from the EMAC_O_CFG register.
    //
    *pui32Config = (HWREG(ui32Base + EMAC_O_CFG) &
                    (VALID_CONFIG_FLAGS | EMAC_CONFIG_TX_ENABLED |
                     EMAC_CONFIG_RX_ENABLED));

    //
    // Get the receive packet size watchdog value.
    //
    ui32Value = HWREG(ui32Base + EMAC_O_WDOGTO);
    if(ui32Value & EMAC_WDOGTO_PWE)
    {
        //
        // The watchdog is enables so the maximum packet length can be read
        // from the watchdog timeout register.
        //
        *pui32RxMaxFrameSize = ui32Value & EMAC_WDOGTO_WTO_M;
    }
    else
    {
        //
        // The maximum packet size override found in the watchdog timer
        // register is not enabled so the maximum packet size is determined
        // by whether or not jumbo frame mode is enabled.
        //
        if(HWREG(ui32Base + EMAC_O_CFG) & EMAC_CFG_JFEN)
        {
            //
            // Jumbo frames are enabled so the watchdog kicks in at 10240
            // bytes.
            //
            *pui32RxMaxFrameSize = 10240;
        }
        else
        {
            //
            // Jumbo frames are not enabled so the watchdog kicks in at
            // 2048 bytes.
            //
            *pui32RxMaxFrameSize = 2048;
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACAddrSet(uint32_t ui32Base, uint32_t ui32Index, const uint8_t *pui8MACAddr)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Index < NUM_MAC_ADDR);
    ASSERT(pui8MACAddr);

    //
    // Set the high 2 bytes of the MAC address.  Note that we must set the
    // registers in this order since the address is latched internally
    // on the write to EMAC_O_ADDRL.
    //
    HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) =
        ((HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF0000) |
         pui8MACAddr[4] | (pui8MACAddr[5] << 8));

    //
    // Set the first 4 bytes of the MAC address
    //
    HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) =
        (pui8MACAddr[0] | (pui8MACAddr[1] << 8) | (pui8MACAddr[2] << 16) |
         (pui8MACAddr[3] << 24));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACAddrGet(uint32_t ui32Base, uint32_t ui32Index, uint8_t *pui8MACAddr)
{
    uint32_t ui32Val;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Index < NUM_MAC_ADDR);
    ASSERT(pui8MACAddr);

    //
    // Get the first 4 bytes of the MAC address.
    //
    ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index));
    pui8MACAddr[0] = ui32Val & 0xFF;
    pui8MACAddr[1] = (ui32Val >> 8) & 0xFF;
    pui8MACAddr[2] = (ui32Val >> 16) & 0xFF;
    pui8MACAddr[3] = (ui32Val >> 24) & 0xFF;

    //
    // Get the last 2 bytes of the MAC address.
    //
    ui32Val = HWREG(ui32Base + EMAC_O_ADDRH(ui32Index));
    pui8MACAddr[4] = ui32Val & 0xFF;
    pui8MACAddr[5] = (ui32Val >> 8) & 0xFF;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACNumAddrGet(uint32_t ui32Base)
{
    //
    // The only Ethernet controller on Snowflake supports 4 MAC addresses.
    //
    return(NUM_MAC_ADDR);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACAddrFilterSet(uint32_t ui32Base, uint32_t ui32Index, uint32_t ui32Config)
{
    uint32_t ui32Val;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Index < NUM_MAC_ADDR);
    ASSERT((ui32Config & ~(EMAC_FILTER_BYTE_MASK_M |
                           EMAC_FILTER_ADDR_ENABLE |
                           EMAC_FILTER_SOURCE_ADDR)) == 0);
    ASSERT(ui32Index);

    //
    // Set the filter configuration for a particular MAC address.
    //
    HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) =
        (HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) & 0xFFFF) | ui32Config;

    //
    // Read and rewrite the low half of the MAC address register to ensure
    // that the upper half's data is latched.
    //
    ui32Val = HWREG(ui32Base + EMAC_O_ADDRL(ui32Index));
    HWREG(ui32Base + EMAC_O_ADDRL(ui32Index)) = ui32Val;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACAddrFilterGet(uint32_t ui32Base, uint32_t ui32Index)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Index < NUM_MAC_ADDR);
    ASSERT(ui32Index);

    //
    // Read and return the filter settings for the requested MAC address slot.
    //
    return(HWREG(ui32Base + EMAC_O_ADDRH(ui32Index)) &
           (EMAC_FILTER_BYTE_MASK_M | EMAC_FILTER_ADDR_ENABLE |
            EMAC_FILTER_SOURCE_ADDR));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACFrameFilterSet(uint32_t ui32Base, uint32_t ui32FilterOpts)
{
    ASSERT((ui32FilterOpts & ~VALID_FRMFILTER_FLAGS) == 0);

    //
    // Set the Ethernet MAC frame filter according to the flags passed.
    //
    HWREG(ui32Base + EMAC_O_FRAMEFLTR) =
        ((HWREG(ui32Base + EMAC_O_FRAMEFLTR) & ~VALID_FRMFILTER_FLAGS) |
         ui32FilterOpts);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACFrameFilterGet(uint32_t ui32Base)
{
    //
    // Return the current MAC frame filter setting.
    //
    return(HWREG(ui32Base + EMAC_O_FRAMEFLTR) & VALID_FRMFILTER_FLAGS);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACHashFilterSet(uint32_t ui32Base, uint32_t ui32HashHi, uint32_t ui32HashLo)
{
    // Set the hash table with the values provided.
    HWREG(ui32Base + EMAC_O_HASHTBLL) = ui32HashLo;
    HWREG(ui32Base + EMAC_O_HASHTBLH) = ui32HashHi;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACHashFilterGet(uint32_t ui32Base, uint32_t *pui32HashHi,
                  uint32_t *pui32HashLo)
{
    ASSERT(pui32HashHi);
    ASSERT(pui32HashLo);

    //
    // Get the current hash table values.
    //
    *pui32HashLo = HWREG(ui32Base + EMAC_O_HASHTBLL);
    *pui32HashHi = HWREG(ui32Base + EMAC_O_HASHTBLH);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACHashFilterBitCalculate(uint8_t *pui8MACAddr)
{
    uint32_t ui32CRC, ui32Mask, ui32Loop;

    //
    // Parameter sanity check.
    //
    ASSERT(pui8MACAddr);

    //
    // Calculate the CRC for the MAC address.
    //
    ui32CRC = Crc32(0xFFFFFFFF, pui8MACAddr, 6);
    ui32CRC ^= 0xFFFFFFFF;

    //
    // Determine the hash bit to use from the calculated CRC.  This is the
    // top 6 bits of the reversed CRC (or the bottom 6 bits of the calculated
    // CRC with the bit order of those 6 bits reversed).
    //
    ui32Mask = 0;

    //
    // Reverse the order of the bottom 6 bits of the calculated CRC.
    //
    for(ui32Loop = 0; ui32Loop < 6; ui32Loop++)
    {
        ui32Mask <<= 1;
        ui32Mask |= (ui32CRC & 1);
        ui32CRC >>= 1;
    }

    //
    // Return the final hash table bit index.
    //
    return(ui32Mask);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACRxWatchdogTimerSet(uint32_t ui32Base, uint8_t ui8Timeout)
{
    //
    // Set the receive interrupt watchdog timeout period.
    //
    HWREG(ui32Base + EMAC_O_RXINTWDT) = (uint32_t)ui8Timeout;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACStatusGet(uint32_t ui32Base)
{
    //
    // Read and return the MAC status register content.
    //
    return(HWREG(ui32Base + EMAC_O_STATUS));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTxDMAPollDemand(uint32_t ui32Base)
{
    //
    // Any write to the MACTXPOLLD register causes the transmit DMA to attempt
    // to resume.
    //
    HWREG(ui32Base + EMAC_O_TXPOLLD) = 0;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACRxDMAPollDemand(uint32_t ui32Base)
{
    //
    // Any write to the MACRXPOLLD register causes the receive DMA to attempt
    // to resume.
    //
    HWREG(ui32Base + EMAC_O_RXPOLLD) = 0;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACRxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor)
{
    //
    // Parameter sanity check.
    //
    ASSERT(pDescriptor);
    ASSERT(((uint32_t)pDescriptor & 3) == 0);

    //
    // Write the supplied address to the MACRXDLADDR register.
    //
    HWREG(ui32Base + EMAC_O_RXDLADDR) = (uint32_t)pDescriptor;
}

//*****************************************************************************
//
//
//*****************************************************************************
tEMACDMADescriptor *
EMACRxDMADescriptorListGet(uint32_t ui32Base)
{
    //
    // Return the current receive DMA descriptor list pointer.
    //
    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_RXDLADDR));
}

//*****************************************************************************
//
//
//*****************************************************************************
tEMACDMADescriptor *
EMACRxDMACurrentDescriptorGet(uint32_t ui32Base)
{
    //
    // Return the address of the current receive descriptor written by the DMA.
    //
    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSRXDESC));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint8_t *
EMACRxDMACurrentBufferGet(uint32_t ui32Base)
{
    //
    // Return the receive buffer address currently being written by the DMA.
    //
    return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSRXBA));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTxDMADescriptorListSet(uint32_t ui32Base, tEMACDMADescriptor *pDescriptor)
{
    //
    // Parameter sanity check.
    //
    ASSERT(pDescriptor);
    ASSERT(((uint32_t)pDescriptor & 3) == 0);

    //
    // Write the supplied address to the MACTXDLADDR register.
    //
    HWREG(ui32Base + EMAC_O_TXDLADDR) = (uint32_t)pDescriptor;
}

//*****************************************************************************
//
//
//*****************************************************************************
tEMACDMADescriptor *
EMACTxDMADescriptorListGet(uint32_t ui32Base)
{
    //
    // Return the current transmit DMA descriptor list pointer.
    //
    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_TXDLADDR));
}

//*****************************************************************************
//
//
//*****************************************************************************
tEMACDMADescriptor *
EMACTxDMACurrentDescriptorGet(uint32_t ui32Base)
{
    //
    // Return the address of the current transmit descriptor read by the DMA.
    //
    return((tEMACDMADescriptor *)HWREG(ui32Base + EMAC_O_HOSTXDESC));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint8_t *
EMACTxDMACurrentBufferGet(uint32_t ui32Base)
{
    //
    // Return the transmit buffer address currently being read by the DMA.
    //
    return((uint8_t *)HWREG(ui32Base + EMAC_O_HOSTXBA));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACDMAStateGet(uint32_t ui32Base)
{
    //
    // Return the status of the DMA channels.
    //
    return(HWREG(ui32Base + EMAC_O_DMARIS) &
           (EMAC_DMARIS_FBI | EMAC_DMARIS_AE_M | EMAC_DMARIS_RS_M |
            EMAC_DMARIS_TS_M));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTxFlush(uint32_t ui32Base)
{
    //
    // Check to make sure that the FIFO is not already empty.
    //
    if(HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_TXFE)
    {
        //
        // Flush the transmit FIFO since it is not currently empty.
        //
        HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_FTF;

        //
        // Wait for the flush to complete.
        //
        while(HWREG(ui32Base + EMAC_O_DMAOPMODE) & EMAC_DMAOPMODE_FTF)
        {
        }
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTxEnable(uint32_t ui32Base)
{
    //
    // Enable the MAC transmit path in the opmode register.
    //
    HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_ST;

    //
    // Enable transmission in the MAC configuration register.
    //
    HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_TE;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTxDisable(uint32_t ui32Base)
{
    //
    // Disable transmission in the MAC configuration register.
    //
    HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE;

    //
    // Disable the MAC transmit path in the opmode register.
    //
    HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACRxEnable(uint32_t ui32Base)
{
    //
    // Enable the MAC receive path.
    //
    HWREG(ui32Base + EMAC_O_DMAOPMODE) |= EMAC_DMAOPMODE_SR;

    //
    // Enable receive in the MAC configuration register.
    //
    HWREG(ui32Base + EMAC_O_CFG) |= EMAC_CFG_RE;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACRxDisable(uint32_t ui32Base)
{
    //
    // Disable reception in the MAC configuration register.
    //
    HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_RE;

    //
    // Disable the MAC receive path.
    //
    HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
{
    //
    // Check the arguments.
    //
    ASSERT(pfnHandler != 0);

    //
    // Register the interrupt handler.
    //
    IntRegister(INT_EMAC0_TM4C129, pfnHandler);

    //
    // Enable the Ethernet interrupt.
    //
    IntEnable(INT_EMAC0_TM4C129);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACIntUnregister(uint32_t ui32Base)
{
    //
    // Disable the interrupt.
    //
    IntDisable(INT_EMAC0_TM4C129);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(INT_EMAC0_TM4C129);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    //
    // Parameter sanity check.
    //
    ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0);

    //
    // Enable the normal interrupt if any of its individual sources are
    // enabled.
    //
    if(ui32IntFlags & EMAC_NORMAL_INTS)
    {
        ui32IntFlags |= EMAC_INT_NORMAL_INT;
    }

    //
    // Similarly, enable the abnormal interrupt if any of its individual
    // sources are enabled.
    //
    if(ui32IntFlags & EMAC_ABNORMAL_INTS)
    {
        ui32IntFlags |= EMAC_INT_ABNORMAL_INT;
    }

    //
    // Set the MAC DMA interrupt mask appropriately if any of the sources
    // we've been asked to enable are found in that register.
    //
    if(ui32IntFlags & ~EMAC_INT_PHY)
    {
        HWREG(ui32Base + EMAC_O_DMAIM) |= ui32IntFlags & ~EMAC_INT_PHY;
    }

    //
    // Enable the PHY interrupt if we've been asked to do this.
    //
    if(ui32IntFlags & EMAC_INT_PHY)
    {
        HWREG(ui32Base + EMAC_O_EPHYIM) |= EMAC_EPHYIM_INT;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    uint32_t ui32Mask;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT((ui32IntFlags & ~EMAC_MASKABLE_INTS) == 0);

    //
    // Get the current interrupt mask.
    //
    ui32Mask = HWREG(ui32Base + EMAC_O_DMAIM);

    //
    // Clear the requested bits.
    //
    ui32Mask &= ~(ui32IntFlags & ~EMAC_INT_PHY);

    //
    // If none of the normal interrupt sources are enabled, disable the
    // normal interrupt.
    //
    if(!(ui32Mask & EMAC_NORMAL_INTS))
    {
        ui32Mask &= ~EMAC_INT_NORMAL_INT;
    }

    //
    // Similarly, if none of the abnormal interrupt sources are enabled,
    // disable the abnormal interrupt.
    //
    if(!(ui32Mask & EMAC_ABNORMAL_INTS))
    {
        ui32Mask &= ~EMAC_INT_ABNORMAL_INT;
    }

    //
    // Write the new mask back to the hardware.
    //
    HWREG(ui32Base + EMAC_O_DMAIM) = ui32Mask;

    //
    // Disable the PHY interrupt if we've been asked to do this.
    //
    if(ui32IntFlags & EMAC_INT_PHY)
    {
        HWREG(ui32Base + EMAC_O_EPHYIM) &= ~EMAC_EPHYIM_INT;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACIntStatus(uint32_t ui32Base, bool bMasked)
{
    uint32_t ui32Val, ui32PHYStat;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Get the unmasked interrupt status and clear any unwanted status fields.
    //
    ui32Val = HWREG(ui32Base + EMAC_O_DMARIS);
    ui32Val &= ~(EMAC_DMARIS_AE_M | EMAC_DMARIS_TS_M | EMAC_DMARIS_RS_M);

    //
    // This peripheral doesn't have a masked interrupt status register
    // so perform the masking manually.  Note that only the bottom 16 bits
    // of the register can be masked so make sure we take this into account.
    //
    if(bMasked)
    {
        ui32Val &= (EMAC_NON_MASKED_INTS | HWREG(ui32Base + EMAC_O_DMAIM));
    }

    //
    // Read the PHY interrupt status.
    //
    if(bMasked)
    {
        ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYMISC);
    }
    else
    {
        ui32PHYStat = HWREG(ui32Base + EMAC_O_EPHYRIS);
    }

    //
    // If the PHY interrupt is reported, add the appropriate flag to the
    // return value.
    //
    if(ui32PHYStat & EMAC_EPHYMISC_INT)
    {
        ui32Val |= EMAC_INT_PHY;
    }

    return(ui32Val);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Mask in the normal interrupt if one of the sources it relates to is
    // specified.
    //
    if(ui32IntFlags & EMAC_NORMAL_INTS)
    {
        ui32IntFlags |= EMAC_INT_NORMAL_INT;
    }

    //
    // Similarly, mask in the abnormal interrupt if one of the sources it
    // relates to is specified.
    //
    if(ui32IntFlags & EMAC_ABNORMAL_INTS)
    {
        ui32IntFlags |= EMAC_INT_ABNORMAL_INT;
    }

    //
    // Clear the maskable interrupt sources.  We write exactly the value passed
    // (with the summary sources added if necessary) but remember that only
    // the bottom 17 bits of the register are actually clearable.  Only do
    // this if some bits are actually set that refer to the DMA interrupt
    // sources.
    //
    if(ui32IntFlags & ~EMAC_INT_PHY)
    {
        HWREG(ui32Base + EMAC_O_DMARIS) = (ui32IntFlags & ~EMAC_INT_PHY);
    }

    //
    // Clear the PHY interrupt if we've been asked to do this.
    //
    if(ui32IntFlags & EMAC_INT_PHY)
    {
        HWREG(ui32Base + EMAC_O_EPHYMISC) |= EMAC_EPHYMISC_INT;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACPHYWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr,
             uint16_t ui16Data)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Parameter sanity check.
    //
    ASSERT(ui8PhyAddr < 32);

    //
    // Make sure the MII is idle.
    //
    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
    {
    }

    //
    // Write the value provided.
    //
    HWREG(ui32Base + EMAC_O_MIIDATA) = ui16Data;

    //
    // Tell the MAC to write the given PHY register.
    //
    HWREG(ui32Base + EMAC_O_MIIADDR) =
        ((HWREG(ui32Base + EMAC_O_MIIADDR) &
          EMAC_MIIADDR_CR_M) | (ui8RegAddr << EMAC_MIIADDR_MII_S) |
         (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIW |
         EMAC_MIIADDR_MIIB);

    //
    // Wait for the write to complete.
    //
    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
    {
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
uint16_t
EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui8PhyAddr < 32);
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Make sure the MII is idle.
    //
    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
    {
    }

    //
    // Tell the MAC to read the given PHY register.
    //
    HWREG(ui32Base + EMAC_O_MIIADDR) =
        ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
         (ui8RegAddr << EMAC_MIIADDR_MII_S) |
         (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);

    //
    // Wait for the read to complete.
    //
    while(HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB)
    {
    }

    //
    // Return the result.
    //
    return(HWREG(ui32Base + EMAC_O_MIIDATA) & EMAC_MIIDATA_DATA_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint16_t
EMACPHYExtendedRead(uint32_t ui32Base, uint8_t ui8PhyAddr,
                    uint16_t ui16RegAddr)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui8PhyAddr < 32);
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Set the address of the register we're about to read.
    //
    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F);
    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr);

    //
    // Read the extended register value.
    //
    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F);
    return(EMACPHYRead(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACPHYExtendedWrite(uint32_t ui32Base, uint8_t ui8PhyAddr,
                     uint16_t ui16RegAddr, uint16_t ui16Value)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui8PhyAddr < 32);
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Set the address of the register we're about to write.
    //
    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x001F);
    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16RegAddr);

    //
    // Write the extended register.
    //
    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_REGCTL, 0x401F);
    EMACPHYWrite(EMAC0_BASE, ui8PhyAddr, EPHY_ADDAR, ui16Value);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACPHYPowerOff(uint32_t ui32Base, uint8_t ui8PhyAddr)
{
    //
    // Set the PWRDN bit and clear the ANEN bit in the PHY, putting it into
    // its low power mode.
    //
    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR,
                 (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) &
                  ~EPHY_BMCR_ANEN) | EPHY_BMCR_PWRDWN);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACPHYPowerOn(uint32_t ui32Base, uint8_t ui8PhyAddr)
{
    //
    // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into
    // normal operating mode.
    //
    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_BMCR,
                 (EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_BMCR) &
                  ~EPHY_BMCR_PWRDWN) | EPHY_BMCR_ANEN);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampConfigSet(uint32_t ui32Base, uint32_t ui32Config,
                       uint32_t ui32SubSecondInc)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Ensure that the PTP module clock is enabled.
    //
    HWREG(ui32Base + EMAC_O_CC) |= EMAC_CC_PTPCEN;

    //
    // Write the subsecond increment value.
    //
    HWREG(ui32Base + EMAC_O_SUBSECINC) = ((ui32SubSecondInc <<
                                           EMAC_SUBSECINC_SSINC_S) &
                                          EMAC_SUBSECINC_SSINC_M);

    //
    // Set the timestamp configuration.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACTimestampConfigGet(uint32_t ui32Base, uint32_t *pui32SubSecondInc)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(pui32SubSecondInc);

    //
    // Read the current subsecond increment value.
    //
    *pui32SubSecondInc = (HWREG(ui32Base + EMAC_O_SUBSECINC) &
                          EMAC_SUBSECINC_SSINC_M) >> EMAC_SUBSECINC_SSINC_S;

    //
    // Return the current timestamp configuration.
    //
    return(HWREG(ui32Base + EMAC_O_TIMSTCTRL));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampEnable(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Enable IEEE 1588 timestamping.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSEN;

    //
    // If necessary, initialize the timestamping system.  This bit self-clears
    // once the system time is loaded.  Only do this if initialization is not
    // currently ongoing.
    //
    if(!(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT))
    {
        HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampDisable(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Disable IEEE 1588 timestamping.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_TSEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampSysTimeSet(uint32_t ui32Base, uint32_t ui32Seconds,
                        uint32_t ui32SubSeconds)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Write the new time to the system time update registers.
    //
    HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds;
    HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds;

    //
    // Wait for any previous update to complete.
    //
    while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSINIT)
    {
        //
        // Spin for a while.
        //
    }

    //
    // Force the system clock to reset.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSINIT;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampSysTimeGet(uint32_t ui32Base, uint32_t *pui32Seconds,
                        uint32_t *pui32SubSeconds)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(pui32Seconds);
    ASSERT(pui32SubSeconds);

    //
    // Read the two-part system time from the seconds and nanoseconds
    // registers.  We do this in a way that should guard against us reading
    // the registers across a nanosecond wrap.
    //
    do
    {
        *pui32Seconds = HWREG(ui32Base + EMAC_O_TIMSEC);
        *pui32SubSeconds = HWREG(ui32Base + EMAC_O_TIMNANO);
    }
    while(*pui32SubSeconds > HWREG(ui32Base + EMAC_O_TIMNANO));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampSysTimeUpdate(uint32_t ui32Base, uint32_t ui32Seconds,
                           uint32_t ui32SubSeconds, bool bInc)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Write the new time to the system time update registers.
    //
    HWREG(ui32Base + EMAC_O_TIMSECU) = ui32Seconds;
    HWREG(ui32Base + EMAC_O_TIMNANOU) = ui32SubSeconds |
                                        (bInc ? 0 : EMAC_TIMNANOU_ADDSUB);

    //
    // Wait for any previous update to complete.
    //
    while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_TSUPDT)
    {
        //
        // Spin for a while.
        //
    }

    //
    // Force the system clock to update by the value provided.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_TSUPDT;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampAddendSet(uint32_t ui32Base, uint32_t ui32Increment)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    HWREG(ui32Base + EMAC_O_TIMADD) = ui32Increment;

    //
    // Wait for any previous update to complete.
    //
    while(HWREG(ui32Base + EMAC_O_TIMSTCTRL) & EMAC_TIMSTCTRL_ADDREGUP)
    {
        //
        // Spin for a while.
        //
    }

    //
    // Force the system clock to update by the value provided.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_ADDREGUP;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampTargetSet(uint32_t ui32Base, uint32_t ui32Seconds,
                       uint32_t ui32SubSeconds)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Wait for any previous write to complete.
    //
    while(HWREG(ui32Base + EMAC_O_TARGNANO) & EMAC_TARGNANO_TRGTBUSY)
    {
    }

    //
    // Write the new target time.
    //
    HWREG(ui32Base + EMAC_O_TARGSEC) = ui32Seconds;
    HWREG(ui32Base + EMAC_O_TARGNANO) = ui32SubSeconds;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampTargetIntEnable(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Set the bit to enable the timestamp target interrupt.  This bit clears
    // automatically when the interrupt fires after which point, you must
    // set a new target time and re-enable the interrupts.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) |= EMAC_TIMSTCTRL_INTTRIG;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampTargetIntDisable(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Clear the bit to disable the timestamp target interrupt.  This bit 
    // clears automatically when the interrupt fires, so it only must be
    // disabled if you want to cancel a previously-set interrupt.
    //
    HWREG(ui32Base + EMAC_O_TIMSTCTRL) &= ~EMAC_TIMSTCTRL_INTTRIG;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACTimestampIntStatus(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Return the current interrupt status from the timestamp module.
    //
    return(HWREG(ui32Base + EMAC_O_TIMSTAT));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampPPSSimpleModeSet(uint32_t ui32Base, uint32_t ui32FreqConfig)
{
    bool bDigital;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Are we currently running the clock in digital or binary rollover mode?
    //
    bDigital = (HWREG(ui32Base + EMAC_O_TIMSTCTRL) &
                EMAC_TS_DIGITAL_ROLLOVER) ? true : false;

    //
    // Weed out some unsupported frequencies.  The hardware can't produce a
    // 1Hz output when we are in binary rollover mode and can't produce a
    // 32KHz output when we are digital rollover mode.
    //
    ASSERT(bDigital || (ui32FreqConfig != EMAC_PPS_1HZ));
    ASSERT(!bDigital || (ui32FreqConfig != EMAC_PPS_32768HZ));

    //
    // Adjust the supplied frequency if we are currently in binary update mode
    // where the control value generates an output that is twice as fast as
    // in digital mode.
    //
    if((ui32FreqConfig != EMAC_PPS_SINGLE_PULSE) && !bDigital)
    {
        ui32FreqConfig--;
    }

    //
    // Write the frequency control value to the PPS control register, clearing
    // the PPSEN0 bit to ensure that the PPS engine is in simple mode and not
    // waiting for a command.  We also clear the TRGMODS0 field to revert to
    // the default operation of the target time registers.
    //
    HWREG(ui32Base + EMAC_O_PPSCTRL) = ui32FreqConfig;
}

//*****************************************************************************
//

//
//*****************************************************************************
void
EMACTimestampPPSCommandModeSet(uint32_t ui32Base, uint32_t ui32Config)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(!(ui32Config & (EMAC_PPS_TARGET_INT | EMAC_PPS_TARGET_PPS |
                           EMAC_PPS_TARGET_BOTH)));

    //
    // Wait for any previous command write to complete.
    //
    while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M)
    {
        //
        // Wait a bit.
        //
    }

    //
    // Write the configuration value to the PPS control register, setting the
    // PPSEN0 bit to ensure that the PPS engine is in command mode and
    // clearing the command in the PPSCTRL field.
    //
    HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui32Config);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampPPSCommand(uint32_t ui32Base, uint8_t ui8Cmd)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Wait for any previous command write to complete.
    //
    while(HWREG(ui32Base + EMAC_O_PPSCTRL) & EMAC_PPSCTRL_PPSCTRL_M)
    {
        //
        // Wait a bit.
        //
    }

    //
    // Write the command to the PPS control register.
    //
    HWREG(ui32Base + EMAC_O_PPSCTRL) = (EMAC_PPSCTRL_PPSEN0 | ui8Cmd);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACTimestampPPSPeriodSet(uint32_t ui32Base, uint32_t ui32Period,
                          uint32_t ui32Width)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Write the desired PPS period and pulse width.
    //
    HWREG(ui32Base + EMAC_O_PPS0INTVL) = ui32Period;
    HWREG(ui32Base + EMAC_O_PPS0WIDTH) = ui32Width;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACVLANRxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Write the VLAN tag register.
    //
    HWREG(ui32Base + EMAC_O_VLANTG) =
        ui32Config | (((uint32_t)ui16Tag) << EMAC_VLANTG_VL_S);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACVLANRxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag)
{
    uint32_t ui32Value;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(pui16Tag);

    //
    // Read the VLAN tag register.
    //
    ui32Value = HWREG(ui32Base + EMAC_O_VLANTG);

    //
    // Extract the VLAN tag from the register.
    //
    *pui16Tag = (ui32Value & EMAC_VLANTG_VL_M) >> EMAC_VLANTG_VL_S;

    //
    // Return the configuration flags.
    //
    return(ui32Value & ~EMAC_VLANTG_VL_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACVLANTxConfigSet(uint32_t ui32Base, uint16_t ui16Tag, uint32_t ui32Config)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Write the VLAN Tag Inclusion or Replacement register.
    //
    HWREG(ui32Base + EMAC_O_VLNINCREP) =
        ui32Config | ((uint32_t)ui16Tag << EMAC_VLNINCREP_VLT_S);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACVLANTxConfigGet(uint32_t ui32Base, uint16_t *pui16Tag)
{
    uint32_t ui32Value;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(pui16Tag);

    //
    // Read the VLAN Tag Inclusion or Replacement register.
    //
    ui32Value = HWREG(ui32Base + EMAC_O_VLNINCREP);

    //
    // Extract the tag.
    //
    *pui16Tag = (uint16_t)((ui32Value & EMAC_VLNINCREP_VLT_M) >>
                           EMAC_VLNINCREP_VLT_S);

    //
    // Return the configuration flags.
    //
    return(ui32Value & ~EMAC_VLNINCREP_VLT_M);
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACVLANHashFilterBitCalculate(uint16_t ui16Tag)
{
    uint32_t ui32CRC, ui32Mask, ui32Loop;

    //
    // Calculate the CRC for the MAC address.
    //
    ui32CRC = Crc32(0xFFFFFFFF, (uint8_t *)&ui16Tag, 2);
    ui32CRC ^= 0xFFFFFFFF;

    //
    // Determine the hash bit to use from the calculated CRC.  This is the
    // top 4 bits of the reversed CRC (or the bottom 4 bits of the calculated
    // CRC with the bit order of those 4 bits reversed).
    //
    ui32Mask = 0;

    //
    // Reverse the order of the bottom 4 bits of the calculated CRC.
    //
    for(ui32Loop = 0; ui32Loop < 4; ui32Loop++)
    {
        ui32Mask <<= 1;
        ui32Mask |= (ui32CRC & 1);
        ui32CRC >>= 1;
    }

    //
    // Return the final hash filter bit index.
    //
    return(ui32Mask);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACVLANHashFilterSet(uint32_t ui32Base, uint32_t ui32Hash)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Write the VLAN Hash Table register.
    //
    HWREG(ui32Base + EMAC_O_VLANHASH) = ui32Hash;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACVLANHashFilterGet(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Return the VLAN Hash Table register.
    //
    return(HWREG(ui32Base + EMAC_O_VLANHASH));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACRemoteWakeUpFrameFilterSet(uint32_t ui32Base,
                               const tEMACWakeUpFrameFilter *pFilter)
{
    uint32_t *pui32Data;
    uint32_t ui32Loop;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(pFilter);

    //
    // Make sure that the internal register counter for the frame filter
    // is reset.  This bit automatically resets after 1 clock cycle.
    //
    HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST;

    //
    // Get a word pointer to the supplied structure.
    //
    pui32Data = (uint32_t *)pFilter;

    //
    // Write the 8 words of the wake-up filter definition to the hardware.
    //
    for(ui32Loop = 0; ui32Loop < 8; ui32Loop++)
    {
        //
        // Write a word of the filter definition.
        //
        HWREG(ui32Base + EMAC_O_RWUFF) = pui32Data[ui32Loop];
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACRemoteWakeUpFrameFilterGet(uint32_t ui32Base,
                               tEMACWakeUpFrameFilter *pFilter)
{
    uint32_t *pui32Data;
    uint32_t ui32Loop;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(pFilter);

    //
    // Make sure that the internal register counter for the frame filter
    // is reset.  This bit automatically resets after 1 clock cycle.
    //
    HWREG(ui32Base + EMAC_O_PMTCTLSTAT) |= EMAC_PMTCTLSTAT_WUPFRRST;

    //
    // Get a word pointer to the supplied structure.
    //
    pui32Data = (uint32_t *)pFilter;

    //
    // Read the 8 words of the wake-up filter definition from the hardware.
    //
    for(ui32Loop = 0; ui32Loop < 8; ui32Loop++)
    {
        //
        // Read a word of the filter definition.
        //
        pui32Data[ui32Loop] = HWREG(ui32Base + EMAC_O_RWUFF);
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
EMACPowerManagementControlSet(uint32_t ui32Base, uint32_t ui32Flags)
{
    uint32_t ui32Value;

    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);
    ASSERT(~(ui32Flags & ~(EMAC_PMT_GLOBAL_UNICAST_ENABLE |
                           EMAC_PMT_WAKEUP_PACKET_ENABLE |
                           EMAC_PMT_MAGIC_PACKET_ENABLE |
                           EMAC_PMT_POWER_DOWN)));

    //
    // Read the control/status register, clear all the bits we can set, mask
    // in the new values then rewrite the new register value.
    //
    ui32Value = HWREG(ui32Base + EMAC_O_PMTCTLSTAT);
    ui32Value &= ~(EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN |
                   EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN);
    ui32Value |= ui32Flags;
    HWREG(ui32Base + EMAC_O_PMTCTLSTAT) = ui32Value;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACPowerManagementControlGet(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Read the control/status register and mask off the control bits to return
    // them to the caller.
    //
    return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) &
           (EMAC_PMTCTLSTAT_GLBLUCAST | EMAC_PMTCTLSTAT_WUPFREN |
            EMAC_PMTCTLSTAT_MGKPKTEN | EMAC_PMTCTLSTAT_PWRDWN));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
EMACPowerManagementStatusGet(uint32_t ui32Base)
{
    //
    // Parameter sanity check.
    //
    ASSERT(ui32Base == EMAC0_BASE);

    //
    // Read the control/status register and mask off the status bits to return
    // them to the caller.
    //
    return(HWREG(ui32Base + EMAC_O_PMTCTLSTAT) &
           (EMAC_PMTCTLSTAT_WUPRX | EMAC_PMTCTLSTAT_MGKPRX |
            EMAC_PMTCTLSTAT_PWRDWN));
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************