lcd.c

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//*****************************************************************************
//
// lcd.c - Defines and Macros for the LCD Controller module.
//
// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************

//*****************************************************************************
//
//
//*****************************************************************************

#include <stdint.h>
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_ints.h"
#include "inc/hw_lcd.h"
#include "driverlib/interrupt.h"
#include "driverlib/sysctl.h"
#include "driverlib/lcd.h"
#include "driverlib/debug.h"

//*****************************************************************************
//
// These are currently missing from hw_lcd.h and included here as a stopgap
// until the hardware header is updated.
//
//*****************************************************************************
#ifndef LCD_RASTRTIM0_MSBPPL_S
#define LCD_RASTRTIM0_MSBPPL_S   3
#endif
#ifndef LCD_RASTRTIM2_MSBLPP_S
#define LCD_RASTRTIM2_MSBLPP_S   26
#endif

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
LCDModeSet(uint32_t ui32Base, uint8_t ui8Mode, uint32_t ui32PixClk,
           uint32_t ui32SysClk)
{
    uint32_t ui32Div;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui8Mode & ~(LCD_MODE_RASTER | LCD_MODE_LIDD |
                        LCD_MODE_AUTO_UFLOW_RESTART)) == 0);

    //
    // Enable clocks to the LCD controller submodules.
    //
    HWREG(ui32Base + LCD_O_CLKEN) = (LCD_CLKEN_DMA | LCD_CLKEN_CORE |
                                     LCD_CLKEN_LIDD);

    //
    // Determine the clock divider to use to get as close as possible to the
    // desired pixel clock.  Note that we set the division up so that we
    // round the divisor up and ensure that the clock used is never faster
    // than the requested rate.
    //
    ui32Div = (ui32SysClk + (ui32PixClk - 1)) / ui32PixClk;

    //
    // Check that the calculated value is valid.
    //
    ASSERT(ui32Div);
    ASSERT(ui32Div < 256);
    ASSERT(!((ui8Mode & LCD_MODE_RASTER) && (ui32Div < 2)));

    //
    // Write the LCDCTL register to set the mode.
    //
    HWREG(ui32Base + LCD_O_CTL) = (uint32_t)ui8Mode |
                                  (ui32Div << LCD_CTL_CLKDIV_S);

    //
    // Return the selected clock rate.  Finding ui32Div set to 0 should not
    // happen unless someone passed pathological arguments and builds without
    // the ASSERTS, but we guard against it just in case.
    //
    return(ui32Div ? (ui32SysClk / ui32Div) : ui32SysClk);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDClockReset(uint32_t ui32Base, uint32_t ui32Clocks)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!(ui32Clocks & ~(LCD_CLOCK_MAIN | LCD_CLOCK_LIDD | LCD_CLOCK_DMA |
                            LCD_CLOCK_CORE)));

    //
    // Reset the required LCD controller sub-module(s).
    //
    HWREG(LCD0_BASE + 0x70) = ui32Clocks;

    //
    // Wait a while.
    //
    SysCtlDelay(10);

    //
    // Remove software reset.
    //
    HWREG(LCD0_BASE + 0x70) = 0x00000000;

    //
    // Wait a while.
    //
    SysCtlDelay(10);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!(ui32Config & ~(LIDD_CONFIG_SYNC_MPU68 | LIDD_CONFIG_ASYNC_MPU68 |
                            LIDD_CONFIG_SYNC_MPU80 | LIDD_CONFIG_ASYNC_MPU80 |
                            LIDD_CONFIG_ASYNC_HITACHI |
                            LIDD_CONFIG_INVERT_ALE |
                            LIDD_CONFIG_INVERT_RS_EN |
                            LIDD_CONFIG_INVERT_WS_DIR |
                            LIDD_CONFIG_INVERT_CS0 | LIDD_CONFIG_INVERT_CS1)));

    //
    // Write the LIDD Control Register.
    //
    HWREG(ui32Base + LCD_O_LIDDCTL) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIDDTimingSet(uint32_t ui32Base, uint32_t ui32CS,
                const tLCDIDDTiming *pTiming)
{
    uint32_t ui32Val;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));
    ASSERT(pTiming);
    ASSERT(pTiming->ui8WSSetup < 32);
    ASSERT(pTiming->ui8WSDuration && (pTiming->ui8WSDuration < 64));
    ASSERT(pTiming->ui8WSHold && (pTiming->ui8WSHold < 16));
    ASSERT(pTiming->ui8RSSetup < 32);
    ASSERT(pTiming->ui8RSDuration && (pTiming->ui8RSDuration < 64));
    ASSERT(pTiming->ui8RSHold && (pTiming->ui8RSHold < 16));
    ASSERT(pTiming->ui8DelayCycles && (pTiming->ui8DelayCycles < 5));

    //
    // Convert the timings provided into a value ready for the register.
    //
    ui32Val =
        (((uint32_t)(pTiming->ui8WSSetup) << LCD_LIDDCS0CFG_WRSU_S) |
         ((uint32_t)(pTiming->ui8WSDuration) << LCD_LIDDCS0CFG_WRDUR_S) |
         ((uint32_t)(pTiming->ui8WSHold) << LCD_LIDDCS0CFG_WRHOLD_S) |
         ((uint32_t)(pTiming->ui8RSSetup) << LCD_LIDDCS0CFG_RDSU_S) |
         ((uint32_t)(pTiming->ui8RSDuration) << LCD_LIDDCS0CFG_RDDUR_S) |
         ((uint32_t)(pTiming->ui8RSHold) << LCD_LIDDCS0CFG_RDHOLD_S) |
         ((uint32_t)(pTiming->ui8DelayCycles - 1) << LCD_LIDDCS0CFG_GAP_S));

    //
    // Write the appropriate LCD LIDD CS configuration register.
    //
    if(!ui32CS)
    {
        HWREG(ui32Base + LCD_O_LIDDCS0CFG) = ui32Val;
    }
    else
    {
        HWREG(ui32Base + LCD_O_LIDDCS1CFG) = ui32Val;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIDDDMADisable(uint32_t ui32Base)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Disable DMA.
    //
    HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIDDCommandWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Cmd)
{
    uint32_t ui32Reg;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));

    //
    // Determine the register to write based on the CS value supplied.
    //
    ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;

    //
    // Write the command/address to the register.
    //
    HWREG(ui32Base + ui32Reg) = ui16Cmd;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIDDDataWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Data)
{
    uint32_t ui32Reg;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));

    //
    // Determine the register to write based on the CS value supplied.
    //
    ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;

    //
    // Write the data value to the register.
    //
    HWREG(ui32Base + ui32Reg) = ui16Data;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIDDIndexedWrite(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr,
                   uint16_t ui16Data)
{
    uint32_t ui32Addr;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));

    //
    // Determine the address register to write.
    //
    ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;

    //
    // Write the address.
    //
    HWREG(ui32Base + ui32Addr) = ui16Addr;

    //
    // Determine the data register to write.
    //
    ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;

    //
    // Write the data.
    //
    HWREG(ui32Base + ui32Addr) = ui16Data;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint16_t
LCDIDDStatusRead(uint32_t ui32Base, uint32_t ui32CS)
{
    uint32_t ui32Reg;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));

    //
    // Determine the register to read based on the CS value supplied.
    //
    ui32Reg = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;

    //
    // Read the relevant status register.
    //
    return((uint16_t)HWREG(ui32Base + ui32Reg));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint16_t
LCDIDDDataRead(uint32_t ui32Base, uint32_t ui32CS)
{
    uint32_t ui32Reg;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));

    //
    // Determine the register to read based on the CS value supplied.
    //
    ui32Reg = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;

    //
    // Read the relevant data register.
    //
    return((uint16_t)HWREG(ui32Base + ui32Reg));
}

//*****************************************************************************
//
//
//*****************************************************************************
uint16_t
LCDIDDIndexedRead(uint32_t ui32Base, uint32_t ui32CS, uint16_t ui16Addr)
{
    uint32_t ui32Addr;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));

    //
    // Determine the address register to write.
    //
    ui32Addr = ui32CS ? LCD_O_LIDDCS1ADDR : LCD_O_LIDDCS0ADDR;

    //
    // Write the address.
    //
    HWREG(ui32Base + ui32Addr) = ui16Addr;

    //
    // Determine the data register to read.
    //
    ui32Addr = ui32CS ? LCD_O_LIDDCS1DATA : LCD_O_LIDDCS0DATA;

    //
    // Return the data read.
    //
    return((uint16_t)HWREG(ui32Base + ui32Addr));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIDDDMAWrite(uint32_t ui32Base, uint32_t ui32CS, const uint32_t *pui32Data,
               uint32_t ui32Count)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32CS == 0) || (ui32CS == 1));
    ASSERT(!((uint32_t)pui32Data & 3));
    ASSERT(!(ui32Count & 1));

    //
    // Make sure DMA is disabled so that enabling it triggers this new
    // transfer.
    //
    HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMAEN;

    //
    // Set up the transfer.  Note that the ceiling register must contain the
    // address of the last word which contains data we want transfered and NOT
    // the first location after the data we want written.
    //
    HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Data;
    HWREG(ui32Base + LCD_O_DMACAFB0) = ((uint32_t)pui32Data +
                                        (ui32Count * 2) - 4);

    //
    // Tell the controller which CS to use for the DMA transaction.
    //
    if(!ui32CS)
    {
        //
        // Use CS0.
        //
        HWREG(ui32Base + LCD_O_LIDDCTL) &= ~LCD_LIDDCTL_DMACS;
    }
    else
    {
        //
        // Use CS1.
        //
        HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMACS;
    }

    //
    // Enable the DMA engine and start the transaction.
    //
    HWREG(ui32Base + LCD_O_LIDDCTL) |= LCD_LIDDCTL_DMAEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterConfigSet(uint32_t ui32Base, uint32_t ui32Config,
                   uint8_t ui8PalLoadDelay)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!(ui32Config & ~(RASTER_FMT_ACTIVE_24BPP_PACKED |
                            RASTER_FMT_ACTIVE_24BPP_UNPACKED |
                            RASTER_FMT_ACTIVE_PALETTIZED_12BIT |
                            RASTER_FMT_ACTIVE_PALETTIZED_16BIT |
                            RASTER_FMT_PASSIVE_MONO_4PIX |
                            RASTER_FMT_PASSIVE_MONO_8PIX |
                            RASTER_FMT_PASSIVE_PALETTIZED |
                            RASTER_FMT_PASSIVE_COLOR_12BIT |
                            RASTER_FMT_PASSIVE_COLOR_16BIT |
                            RASTER_ACTVID_DURING_BLANK |
                            RASTER_NIBBLE_MODE_ENABLED |
                            RASTER_LOAD_DATA_ONLY |
                            RASTER_LOAD_PALETTE_ONLY |
                            RASTER_READ_ORDER_REVERSED)));

    //
    // Write the raster control register.
    //
    HWREG(ui32Base + LCD_O_RASTRCTL) = (ui32Config |
                                        ((uint32_t)ui8PalLoadDelay <<
                                         LCD_RASTRCTL_REQDLY_S));
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterTimingSet(uint32_t ui32Base, const tLCDRasterTiming *pTiming)
{
    uint32_t ui32T0, ui32T1, ui32T2;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(pTiming);
    ASSERT(!(pTiming->ui32Flags & ~(RASTER_TIMING_SYNCS_OPPOSITE_PIXCLK |
                                    RASTER_TIMING_SYNCS_ON_FALLING_PIXCLK |
                                    RASTER_TIMING_SYNCS_ON_RISING_PIXCLK |
                                    RASTER_TIMING_ACTIVE_LOW_OE |
                                    RASTER_TIMING_ACTIVE_LOW_PIXCLK |
                                    RASTER_TIMING_ACTIVE_LOW_HSYNC |
                                    RASTER_TIMING_ACTIVE_LOW_VSYNC)));
    ASSERT(pTiming->ui16PanelWidth && (pTiming->ui16PanelWidth <= 2048) &&
           ((pTiming->ui16PanelWidth % 16) == 0));
    ASSERT(pTiming->ui16PanelHeight && (pTiming->ui16PanelHeight <= 2048));
    ASSERT(pTiming->ui16HFrontPorch && (pTiming->ui16HFrontPorch <= 1024));
    ASSERT(pTiming->ui16HBackPorch && (pTiming->ui16HBackPorch <= 1024));
    ASSERT(pTiming->ui16HSyncWidth && (pTiming->ui16HSyncWidth <= 1024));
    ASSERT(pTiming->ui8VSyncWidth && (pTiming->ui8VSyncWidth <= 64));

    //
    // Construct the values we need for the three raster timing registers.
    //
    ui32T0 = ((uint32_t)((pTiming->ui16HBackPorch - 1) & 0xFF) <<
              LCD_RASTRTIM0_HBP_S) |
             ((uint32_t)((pTiming->ui16HFrontPorch - 1) & 0xFF) <<
              LCD_RASTRTIM0_HFP_S) |
             ((uint32_t)((pTiming->ui16HSyncWidth - 1) & 0x3F) <<
              LCD_RASTRTIM0_HSW_S) |
             (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x3F0) >> 4) <<
              LCD_RASTRTIM0_PPL_S) |
             (((uint32_t)((pTiming->ui16PanelWidth - 1) & 0x400) >> 10) <<
              LCD_RASTRTIM0_MSBPPL_S);
    ui32T1 = ((uint32_t)pTiming->ui8VBackPorch << LCD_RASTRTIM1_VBP_S) |
             ((uint32_t)pTiming->ui8VFrontPorch << LCD_RASTRTIM1_VFP_S) |
             ((uint32_t)((pTiming->ui8VSyncWidth - 1) & 0x3F) <<
              LCD_RASTRTIM1_VSW_S) |
             ((uint32_t)(pTiming->ui16PanelHeight - 1) & 0x3FF) <<
             LCD_RASTRTIM1_LPP_S;
    ui32T2 = pTiming->ui32Flags |
             ((((pTiming->ui16HSyncWidth - 1) & 0x3C0) >> 6) <<
              LCD_RASTRTIM2_HSW_S) |
             ((((pTiming->ui16PanelHeight - 1) & 0x400) >> 10) <<
              LCD_RASTRTIM2_MSBLPP_S) |
             ((((pTiming->ui16HBackPorch - 1) & 0x300) >> 8) <<
              LCD_RASTRTIM2_MSBHBP_S) |
             ((((pTiming->ui16HFrontPorch - 1) & 0x300) >> 8) <<
              LCD_RASTRTIM2_MSBHFP_S) |
             (pTiming->ui8ACBiasLineCount << LCD_RASTRTIM2_ACBF_S);

    //
    // Write the timing registers, taking care to preserve any existing value
    // in the AC Bias interrupt field of RASTRTIM2.
    //
    HWREG(ui32Base + LCD_O_RASTRTIM0) = ui32T0;
    HWREG(ui32Base + LCD_O_RASTRTIM1) = ui32T1;
    HWREG(ui32Base + LCD_O_RASTRTIM2) = (HWREG(ui32Base + LCD_O_RASTRTIM2) &
                                         LCD_RASTRTIM2_ACBI_M) | ui32T2;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterACBiasIntCountSet(uint32_t ui32Base, uint8_t ui8Count)
{
    uint32_t ui32Val;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(ui8Count < 16);

    //
    // Get the existing raster timing 2 register value and mask in the new
    // AC Bias interrupt count.
    //
    ui32Val = HWREG(ui32Base + LCD_O_RASTRTIM2);
    ui32Val &= ~LCD_RASTRTIM2_ACBI_M;
    ui32Val |= ((ui8Count << LCD_RASTRTIM2_ACBI_S) & LCD_RASTRTIM2_ACBI_M);

    //
    // Write the new value back to the register.
    //
    HWREG(ui32Base + LCD_O_RASTRTIM2) = ui32Val;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterEnable(uint32_t ui32Base)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Reset the module prior to starting the raster.  This is required to
    // ensure correct operation of the raster engine.
    //
    LCDClockReset(ui32Base, LCD_CLOCK_MAIN);

    //
    // Enable the raster engine.
    //
    HWREG(ui32Base + LCD_O_RASTRCTL) |= LCD_RASTRCTL_LCDEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
bool
LCDRasterEnabled(uint32_t ui32Base)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Return the current raster engine status.
    //
    return((HWREG(ui32Base + LCD_O_RASTRCTL) & LCD_RASTRCTL_LCDEN) ?
           true : false);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterDisable(uint32_t ui32Base)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Disable the raster engine.
    //
    HWREG(ui32Base + LCD_O_RASTRCTL) &= ~LCD_RASTRCTL_LCDEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterSubPanelConfigSet(uint32_t ui32Base, uint32_t ui32Flags,
                           uint32_t ui32BottomLines, uint32_t ui32DefaultPixel)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT((ui32Flags == LCD_SUBPANEL_AT_TOP) ||
           (ui32Flags == LCD_SUBPANEL_AT_BOTTOM));
    ASSERT(ui32BottomLines && (ui32BottomLines <= 2048));

    //
    // Adjust the line count into the 0-2047 range.
    //
    ui32BottomLines--;

    //
    // Set the first subpanel configuration register, taking care to leave the
    // subpanel enabled if it already was.
    //
    HWREG(ui32Base + LCD_O_RASTRSUBP1) = (HWREG(ui32Base + LCD_O_RASTRSUBP1) &
                                          LCD_RASTRSUBP1_SPEN) | ui32Flags |
                                         ((ui32DefaultPixel & 0xFFFF) <<
                                          LCD_RASTRSUBP1_DPDLSB_S) |
                                         ((ui32BottomLines <<
                                           LCD_RASTRSUBP1_LPPT_S) &
                                          LCD_RASTRSUBP1_LPPT_M);

    //
    // Set the second subpanel configuration register.
    //
    HWREG(ui32Base + LCD_O_RASTRSUBP2) =
        ((ui32DefaultPixel >> 16) & LCD_RASTRSUBP2_DPDMSB_M) |
        (((ui32BottomLines >> LCD_RASTRSUBP1_LPPT_S) & 1) << 8);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterSubPanelEnable(uint32_t ui32Base)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Enable the subpanel.
    //
    HWREG(ui32Base + LCD_O_RASTRSUBP1) |= LCD_RASTRSUBP1_SPEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterSubPanelDisable(uint32_t ui32Base)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Disable the subpanel.
    //
    HWREG(ui32Base + LCD_O_RASTRSUBP1) &= ~LCD_RASTRSUBP1_SPEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDDMAConfigSet(uint32_t ui32Base, uint32_t ui32Config)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!(ui32Config & ~(LCD_DMACTL_FIFORDY_M | LCD_DMACTL_BURSTSZ_M |
                            LCD_DMACTL_BYTESWAP | LCD_DMACTL_BIGDEND |
                            LCD_DMACTL_FMODE)));

    //
    // Write the DMA control register.
    //
    HWREG(ui32Base + LCD_O_DMACTL) = ui32Config;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDRasterPaletteSet(uint32_t ui32Base, uint32_t ui32Type, uint32_t *pui32Addr,
                    const uint32_t *pui32SrcColors, uint32_t ui32Start,
                    uint32_t ui32Count)
{
    uint16_t *pui16Pal;
    uint16_t *pui16Src;
    uint32_t ui32Loop;

    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(ui32Start < 256);
    ASSERT((ui32Start + ui32Count) <= 256);
    ASSERT(pui32Addr);
    ASSERT((pui32SrcColors) || (ui32Count == 0));
    ASSERT(!(ui32Type & ~(LCD_PALETTE_SRC_24BIT | LCD_PALETTE_TYPE_DIRECT |
                          LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_4BPP |
                          LCD_PALETTE_TYPE_2BPP | LCD_PALETTE_TYPE_1BPP)));

    //
    // Get a pointer to the start of the palette.
    //
    pui16Pal = (uint16_t *)pui32Addr;

    //
    // Are we converting the palette color format?
    //
    if(ui32Type & LCD_PALETTE_SRC_24BIT)
    {
        //
        // Yes - loop through each of the supplied 24-bit colors converting
        // and storing each.
        //
        ui32Loop = 0;
        while(ui32Count)
        {
            pui16Pal[ui32Start + ui32Loop] =
                PAL_FROM_RGB(pui32SrcColors[ui32Loop]);
            ui32Loop++;
            ui32Count--;
        }
    }
    else
    {
        //
        // No - loop through the supplied 12-bit colors storing each.
        //

        pui16Src = (uint16_t *)pui32SrcColors;
        while(ui32Count)
        {
            pui16Pal[ui32Start] = pui16Src[ui32Start];
            ui32Start++;
            ui32Count--;
        }
    }

    //
    // Write the pixel type into the first palette entry.
    //
    pui16Pal[0] &= ~(LCD_PALETTE_TYPE_8BPP | LCD_PALETTE_TYPE_DIRECT);
    pui16Pal[0] |= (ui32Type & ~LCD_PALETTE_SRC_24BIT);
}

//*****************************************************************************
//
//*****************************************************************************
void
LCDRasterFrameBufferSet(uint32_t ui32Base, uint8_t ui8Buffer,
                        uint32_t *pui32Addr, uint32_t ui32NumBytes)
{
    //
    // Sanity check parameters.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!((uint32_t)pui32Addr & 3));
    ASSERT(!(ui32NumBytes & 3));
    ASSERT(ui8Buffer < 2);

    //
    // Are we setting the values for frame buffer 0?
    //
    if(!ui8Buffer)
    {
        //
        // Yes - set the registers for frame buffer 0.
        //
        HWREG(ui32Base + LCD_O_DMABAFB0) = (uint32_t)pui32Addr;
        HWREG(ui32Base + LCD_O_DMACAFB0) = (uint32_t)pui32Addr +
                                           ui32NumBytes - 4;
    }
    else
    {
        //
        // No - set the registers for frame buffer 1.
        //
        HWREG(ui32Base + LCD_O_DMABAFB1) = (uint32_t)pui32Addr;
        HWREG(ui32Base + LCD_O_DMACAFB1) = (uint32_t)pui32Addr +
                                           ui32NumBytes - 4;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST |
                              LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW |
                              LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 |
                              LCD_INT_RASTER_FRAME_DONE)));

    //
    // Enable the interrupt sources by setting the appropriate bits in the
    // mask register.
    //
    HWREG(ui32Base + LCD_O_IM) = ui32IntFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST |
                              LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW |
                              LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 |
                              LCD_INT_RASTER_FRAME_DONE)));

    //
    // Disable the interrupt sources by clearing the appropriate bits in the
    // mask register.
    //
    HWREG(ui32Base + LCD_O_IENC) = ui32IntFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
uint32_t
LCDIntStatus(uint32_t ui32Base, bool bMasked)
{
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Were we asked for the masked or raw interrupt status?
    //
    if(bMasked)
    {
        //
        // Return the masked interrupt status.
        //
        return(HWREG(ui32Base + LCD_O_MISCLR));
    }
    else
    {
        //
        // Return the raw interrupts status.
        //
        return(HWREG(ui32Base + LCD_O_RISSET));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
{
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(!(ui32IntFlags & ~(LCD_INT_DMA_DONE | LCD_INT_SYNC_LOST |
                              LCD_INT_AC_BIAS_CNT | LCD_INT_UNDERFLOW |
                              LCD_INT_PAL_LOAD | LCD_INT_EOF0 | LCD_INT_EOF1 |
                              LCD_INT_RASTER_FRAME_DONE)));

    //
    // Clear the requested interrupts.
    //
    HWREG(ui32Base + LCD_O_MISCLR) = ui32IntFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == LCD0_BASE);
    ASSERT(pfnHandler);

    //
    // Register the interrupt handler.
    //
    IntRegister(INT_LCD0_TM4C129, pfnHandler);

    //
    // Enable the interrupt in the interrupt controller.
    //
    IntEnable(INT_LCD0_TM4C129);
}

//*****************************************************************************
//
//
//*****************************************************************************
void
LCDIntUnregister(uint32_t ui32Base)
{
    //
    // Check the arguments.
    //
    ASSERT(ui32Base == LCD0_BASE);

    //
    // Disable the interrupt in the interrupt controller.
    //
    IntDisable(INT_LCD0_TM4C129);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(INT_LCD0_TM4C129);
}

//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************